of Name:____________________
Department Electrical and Computer Engineering University of Wisconsin Madison
ECE601 Digital System Design and Synthesis
MIDTERM EXAM
Spring 2001, Instructor: Professor Lei He
Open Book and Notes 80 minutes
There are totally eight pages including this cover page. No page is blank. Please make sure that you have all pages. Raise your hand now if any page is missing. Allocate your time appropriately. Good luck.
Problem 1 2 3 4 Total
Points 20 30 25 25 100
Score _____ _____ _____ _____ _____
1
Problem 1 (20 points) Circle TRUE or FALSE to answer each of the following questions (total 10 points):
TRUE FALSE (1) The inertial delay of the following gate is 3.78ns `timescale 1ns /10ps #3.777 and(a, b, c); TRUE FALSE (2) The value loaded into an 8-bit register Y by the execution of the following statement is xxxx_x101. Y=5'bx101
TRUE FALSE (3) Symbol * for waveform transition in a UDP stands for don't care, i.e., it is an iteration of an input over the values 0, 1, and x. TRUE FALSE (4) if A has a value 2'b10, and B has a value 3'b110, an 8-bit register C is loaded with value 8'b1111_1011 after the execution of the following statement C = A-B. TRUE FALSE (5) The following code is correct. module nand3 (o1, in1, in2, in3) input in1, in2, in3; output o1; reg o1; o1 = in1 & in2 & in3; endmodule
Provide clear answers to the following questions (total 10 points): (6) The comparison 4'bxx10 = = = 4'bx110 produces a one-bit value ___. (7) according to statement buf_if1 G1 #(3:4:5, 6:7:8, 5:8:9) (yout, xin, enable) the typical falling delay of G1 is ________, and the best case turnoff delay is ________.
(8) Use continuous assignments to rewrite the following module, without instantiation of any primitive or module.
2
module random_logic (o1, in1, in2, in3); input in1, in2, in3; output o1; wire y; xor(y, in1, in3); nand (o1, y, in2); endmodule
module random_logic (o1, in1, in2, in3);
endmodule (9) Complete the following delay specification block for a D-type flip-flop with edge-sensitive path delay. The delay between Data and Q is qualified by the positive clock edge and is 100ps, and the delay between Preset and Q is asynchronous and is 40ps. module D_FF(clk, Data, Preset, Q) input clk, Data, Preset; output Q; `timescale 20ps/10ps specify
endspecify // description of behavior FF here, omitted endmodule (10) Sketch the waveforms of clk1 and clk2 fork #0 clk1 = 0; #10 clk1 = 1; #20 clk1 = 0; #25 clk1 = 1; #10 clk2 = 0; #15 clk2 = 1; join
3
Problem 2 (30 points) (1) Write a UDP for a one-bit comparator whose output is 1 if and only if A >= B, considering 0, 1, and x for A and B. Caution should be used to reduce the pessimism when dealing with unknown input x. primitive comparator(comp_out, A, B) output comp_out; input A, B; table // A
B
:
comp_out
endtable endprimitive (2) Implement another comparator using continuous assignment, and then write a testbench to verify that the new comparator and the above UDP have identical functionality over all input combinations. module comp_testbench;
//define clock reg clock, error; reg A, B; initial clock = 0; always begin #5 clock = ~clock;
4
end //implement a comparator using continuous assignments. wire comp_out1;
//instantiate a comparator using the above UDP wire comp_out2;
//define all input combinations initial begin A=0; B=0; #
end //output error = 1 if the two comparators do not have identical functionality
always @ (posedge clock) begin error = end endmodule
5
Problem 3 (25 points) For the following modules gate1, gate2 and gate3, find output waveform for the given input waveforms. module gate1(o1, o2, i1, i2); input i1, i2 output o1, o2; reg o1, o2; always @ (i1 or i2) begin ...