FPGA An Software-Dened Ultra Wideband Transceiver
Matthew Bruce Blanton
Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulllment of the requirements for the degree of
Master of Science in Computer Engineering
Dr. Peter M. Athanas, Chair Dr. Mark T. Jones Dr. Cameron D. Patterson
August 28, 2006 Bradley Department of Electrical and Computer Engineering Blacksburg, Virginia
Keywords: ultra-wideband, FPGA, software dened radio, high-speed Copyright 2006 , Matthew Bruce Blanton
An FPGA Software-Dened Ultra Wideband Transceiver
Matthew Bruce Blanton
(ABSTRACT)
Increasing interest in ultra-wideband (UWB) communications has engendered the need for a test bed for UWB systems. An FPGA-based software-dened radio provides both postfabrication denition of the radio and ample parallel processing power. This thesis presents the FPGA design for a software-dened radio targeted to impulse ultra-wideband signals. The system is capable of an eective sampling frequency of up to 8 G-samples/s using timeinterleaved sampling with eight 1-GHz ADCs. The system is also capable of transmitting UWB pulses using a transmitter board controlled by the FPGA. In this thesis, the FPGA design used to capture and export data from the eight ADCs is presented, along with two systems which make use of the transceiver: a pilot-based matched lter communications system, and a remote vital signs monitor.
Acknowledgements
I must rst thank my advisor Dr. Peter Athanas for inviting me to join the Congurable Computing Lab and for guiding me throughout my time at the CCM Lab. Thanks also must go to my committee members, Dr. Mark Jones and Dr. Cameron Patterson, for knowledge gained from them both in the classroom and at lab. I am indebted to my parents for all of the love and support they have given me throughout my time here at Virginia Tech. I would not be where I am today without them. Thank you also to Amy for always being there for me. Thank you to all of my friends and colleagues at the CCM Lab for helping me learn and making this past year fun.
iii
Contents
1 Introduction 1.1 1.2 1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 1 2 2
2 Background 2.1 2.2 2.3 High-Speed Recongurable Signal Processing . . . . . . . . . . . . . . . . . . Software-Dened Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ultra-Wideband Communications . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 2.3.2 2.3.3 2.4 Impulse Ultra-Wideband Signals . . . . . . . . . . . . . . . . . . . . . Impulse Ultra-Wideband Modulation Schemes . . . . . . . . . . . . . FCC Regulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 4 6 9 10 10 12 14
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Ultra-Wideband Transceiver System 3.1 Time-Interleaved Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15 16
iv
3.2 3.3 3.4 3.5 3.6 3.7 3.8
Analog to Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Bus Timing Budget . . . . . . . . . . . . . . . . . . . . . . . . . Field-Programmable Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . RF Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prototype Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Final Radio Receiver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 18 18 20 20 21 23
4 FPGA Subsystem Design 4.1 4.2 4.3 ADC Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Uncertainty and Synchronization . . . . . . . . . . . . . . . . . . . . . 4.3.1 4.3.2 4.4 FPGA Clock Uncertainty . . . . . . . . . . . . . . . . . . . . . . . . ADC Reset Uncertainty . . . . . . . . . . . . . . . . . . . . . . . . .
24 24 28 29 29 35 38 39 41 43 44 45 45 46
Pilot-Based Matched Filtering Receiver . . . . . . . . . . . . . . . . . . . . . 4.4.1 Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coarse Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fine Acquisition 4.4.2 4.4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pilot Pulse Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partial Correlation Unit . . . . . . . . . . . . . . . . . . . . . . . . . Schedule and Coecient Generation . . . . . . . . . . . . . . . . . .
Adder Tree and Comparator . . . . . . . . . . . . . . . . . . . . . . . 4.4.4 4.5 Real-Time Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48 48 49
Vital Signs Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Results 5.1 5.2 5.3 5.4 5.5 5.6 Initial System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Reset Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pilot-Based Matched Filter Receiver . . . . . . . . . . . . . . . . . . . . . . Vital Signs Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 50 52 57 59 59 62
6 Conclusion 6.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64 65
Bibliography
66
List of Figures
2.1 2.2 2.3 2.4 2.5 3.1 3.2 Block Diagrams of SDR Receivers . . . . . . . . . . . . . . . . . . . . . . . . Typical Impulse UWB Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Position Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . On O Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Amplitude Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Interleaved Sampling with Four ADCs . . . . . . . . . . . . . . . . . . Eects of ADC Mismatches on a Two-ADC Time-Interleaved Sampling System [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 3.4 3.5 4.1 4.2 4.3 4.4 Xilinx Virtex-II Pro FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Board System Conguration . . . . . . . . . . . . . . . . . . . . . . . . Final Board System Conguration [1] . . . . . . . . . . . . . . . . . . . . . . Data Capture Hardware Data Flow Diagram . . . . . . . . . . . . . . . . . . Data Synchronizer Circuit [2] . . . . . . . . . . . . . . . . . . . . . . . . . . Data Synchronizer Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . System Conguration for the Two-ADC Testboard . . . . . . . . . . . . . . 19 20 21 22 25 27 27 28 7 11 12 13 13 17
vii
4.5 4.6
System Conguration for the Eight-ADC Radio Board . . . . . . . . . . . . The two ways in which the FPGA can generate the 250 MHz clock from the ADC data ready signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
31 32
4.7 4.8
Relative phases between dierent FPGA-generated clocks . . . . . . . . . . . Input of Samples from Local Clock Domain with Correct and Incorrect Local Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
4.9
Method to Determine if Local Clock is Relatively In Phase with Master Clock 34 34 36 37 38 39 40 46 47 49 51 53 54
4.10 Waveforms from Phase Checking Circuit . . . . . . . . . . . . . . . . . . . . 4.11 Method to correct DCM phase . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 ADC Sample Queue for ADC Reset Correction . . . . . . . . . . . . . . . . . 4.13 PBMF Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 PBMF Receiver Dataow Diagram . . . . . . . . . . . . . . . . . . . . . . . 4.15 PBMF Receiver FPGA Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 Partial Correlation Unit [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Schedule Register for Pulse Beginning at Sample 0 . . . . . . . . . . . . . . . 4.18 Vital Signs System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 5.2 5.3 5.4 Radio Receiver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 MHz Sine Wave Input Captured With 6.4 GHz Sampling Rate [1] . . . . 793 MHz Sine Wave Input Captured With 6.4 GHz Sampling Rate [1] . . . . Comparison of UWB Pulse Captured by 6.4 GHz Data Capture and an Oscilloscope [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
5.5
UWB Positive Pulse Including Multipath Captured with 6.4 G-samples/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.6
UWB Negative Pulse Including Multipath Captured with 6.4 G-samples/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 58 58 59 61 63
5.7 5.8 5.9
Chipscope Output Showing ADC Sample Misalignment . . . . . . . . . . . . Graph of Chipscope Output Showing ADC Sample Misalignment . . . . . . Transmitter Board UWB Pulse Output . . . . . . . . . . . . . . . . . . . . .
5.10 Results of Acquisition Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Time Domain Response of Pulse Multipath to Oscillation of a Metal Plate .
5.12 Frequency Domain Response of Pulse Multipath to Oscillation of a Metal Plate 63
List of Tables
5.1 Actual Breathing Rate vs. Recorded Breathing Rate in Breaths Per Minute . 62
x
Chapter 1 Introduction
1.1
Motivation
As noted in [3, 4, 5], ultra-wideband communications are suitable for use in several applications. UWB is a blanket term used for systems that use large instantaneous spectral bandwidth, particularly those systems whose bandwidth is much greater than their information rate. The FCC has allocated a large spectral range for unlicensed UWB communications. This increasing interest in UWB technology has created the need for a powerful, congurable test bed for UWB applications. Specically, a test bed for areas such as ultrawideband communications, precision ranging, and position-location is needed. Researchers need the ability to test new modulation schemes, multiple access protocols, and applications in real time, without having to create custom systems. A system with a very high sampling frequency and signicant computational power is required in order to allow for software-dened processing of UWB waveforms. In the past, work has been done to create custom RF front-ends which reduce the sampling rate for a UWB system enough to allow for conventional SDR processing [6], but there does not exist a system with a multi-gigahertz sampling rate designed for real-time software-dened processing of UWB waveforms. This thesis presents an FPGA-based software-dened radio that uses time-interleaved sampling to 1
2 digitize the received signal. An FPGA-based software-dened radio system oers the benet of easy reconguration and the power of massively parallel computation. Time-interleaved sampling increases the eective sampling frequency without the need for an increase in the FPGA clock frequency and oers a considerable cost savings.
1.2
Contributions
This thesis describes a exible transceiver that is geared towards ultra-wideband communications and oers a maximum eective sampling frequency of 8 G-samples/s. The focus of the thesis is on the FPGA design for this system. Two applications are discussed, a pilot-based matched lter receiver and a vital signs monitor. This thesis presents several contributions. Methods for ensuring the synchronization of the FPGA clocks and ADC sample data were developed, as was the base hardware needed to capture data with eight time-interleaved ADCs. An interface from a host PC to the FPGA hardware was implemented. The software required to implement the acquisition phase of the pilot-based matched lter hardware was developed. The hardware for the pilot-based matched lter was debugged and interfaced with the data capture hardware and acquisition software. A vital signs monitoring application which allowed for the remote measurement of a subjects breathing rate was targeted to the transceiver and tested.
1.3
Thesis Organization
Chapter 2 of this thesis provides background for this work, including past eorts in congurable signal processing, software-dened radio trends, and an overview of ultra-wideband technology. Chapter 3 discusses the time-interleaved sampling method used to digitize the RF input. It also reviews the major parts of the transceiver system and provides specications for the transceiver and for the test system which was constructed previously. Chapter
3 4 discusses the FPGA subsystem design, including the hardware and software needed to implement the pilot-based matched lter receiver and the vital signs monitor. Chapter 5 details the results gained, including the success of the data capture hardware in receiving information from eight time-interleaved ADCs, the correct demodulation of data by the matched lter receiver, and the ability of the vital signs monitoring application to accurately measure a subjects breathing rate.
Chapter 2 Background
A high-speed yet congurable processor is needed for a high data rate software-dened radio (SDR) such as an ultra-wideband SDR. This chapter discusses previous eorts in research areas pertaining to this work, including high-speed recongurable signal processing, software-dened radio, and ultra-wideband communications. An overview of ultra-wideband technology and modulation schemes is also presented.
2.1
High-Speed Recongurable Signal Processing
The need for high-speed yet congurable digital signal processing has been addressed by researchers in the past. Some have chosen to use ne-grained, commercial o-the-shelf (COTS) FPGAs, while others have chosen to implement custom, coarse-grained architectures. One project that took the latter approach was the Dynamically Recongurable Architecture for Mobile Systems (DReaM). The DReaM architecture was an eort to target signal processing for mobile systems with a coarse-grained, domain-specic approach [7]. DReaM combined congurable routing with 8-bit integer operators, dual-ported RAMs, and Spreading Data Path (SDP) units to implement radio functionality. The SDP was used to perform
4
5 communication-specic tasks such as CDMA-based spreading or complex correlation used in QPSK modulation. One application for the DReaM architecture was a CDMA RAKE receiver that was able to accommodate a symbol rate of 32 M-symbols/s. Another architecture that uses a custom coarse-grained architecture is detailed in [8]. This system combined a custom recongurable parallel processor with a DSP and an FPGA for congurable routing. The custom processor was the XPP-64A, which implemented an array of ALU Processing Array Elements (ALU-PAEs). The ALU-PAEs implemented a DSP-based instruction set that operated on 24-bit words. The ALE-PAEs also included dual-ported RAM and congurable routing. This architecture was targeted to a RAKE receiver and an OFDM decoder. Other systems such as the Berkeley Emulation Engine (BEE) and BEE2 have exploited the ability of FPGAs to quickly process large amounts of data in parallel. The BEE and BEE2 platforms were designed to oer massively parallel processing of data with an emphasis on hardware emulation [9, 10]. The original BEE system was comprised of BEE Processing Units (BPUs), each of which contained 20 Xilinx Virtex-E FPGAs. Sixteen FPGAs in each BPU were used for computation and the remaining four were used as congurable crossbar switches. Tool ows using Simulink and Xilinx System Generator allowed for emulation of ASIC designs with a high level of design abstraction. One test of the BEE system was an emulation of a TDMA receiver with a 806 kHz symbol rate. This design used three processing FPGAs and one crossbar FPGA and was able to operate at a maximum frequency of 25.0 MHz [9]. A single-channel 2.4 GHz radio system tested on the BEE platform was able to operate in real-time with a 32 MHz system clock rate [11]. The BEE2 platform expanded on the BEE concept and took advantage of newer technologies. Each BEE2 compute module contained ve Xilinx Virtex-II Pro FPGAs. Each FPGA was connected to four 400 MHz DDR DRAM DIMMs, giving up to 4 GB of memory per FPGA with a memory bandwidth of up to 12.8 Gbps. In each module, four FPGAs were used for computation, and one was used for control. The control FPGA had additional con-
6 nectors for o-board communication. The FPGAs were connected together on-board with parallel LVCMOS connections and could communicate to o-board entities with high-speed serial transceivers. BEE2 was designed not only for emulation but also for implementation of high-speed DSP applications. One use of the BEE2 system was a cognitive radio test bed [12]. BEE2 performed signal processing functions for the test bed. In another application, the BEE2 processed 16 Gbps of digital data to implement a spectrometer with sub-hertz spectral resolution over 800 MHz. While BEE2 has been shown to be useful in circuit emulation and in signal processing, there exists a drawback to using such a general computation engine. Because BEE2 was designed to use high-speed serial links for o-board communications, complex front-end boards were needed to interface with BEE2. In [12], the front end board contained a Xilinx Virtex-II Pro FPGA in addition to the analog lters, the ADC, and the DAC. The FPGA was needed for communication with the BEE2 board. A more application-specic processing system could use the FPGA connected to the ADC and DAC as the processing element, instead of ooading the processing to another system.
2.2
Software-Dened Radio
The goal of a software-dened radio is to move as much of the processing in the radio from xed hardware to software, with the intention of making the function of the radio more congurable. Ideally, a software-dened radio consists of an analog-to-digital converter (ADC) connected to an antenna. The digital output is fed into a congurable computation device for processing. In practice, however, an analog front-end is necessary. RF processing and down conversion are performed in the analog domain before the ADCs [13]. Softwaredened radio is evolving towards the ideal. Future SDRs might replace xed analog hardware with an intelligent software-controlled RF front end [13]. The benets of of a software-dened radio are evident. The operation of the radio can be
7
(a) Typical SDR Receiver
(b) Advanced SDR Receiver with Software-Controlled Front End
Figure 2.1: Block Diagrams of SDR Receivers changed without signicant hardware changes. As a test platform for wireless communications researchers, an SDR allows for the testing of dierent modulation and demodulation schemes, multiple access protocols, and any other aspect of the radio processing that can be done in the digital domain. As a nal product, an SDR is attractive to several groups [14]:
Wireless handset creators want to x bugs more easily and to remotely re-ash devices. Military organizations are interested in interoperability, cost eectiveness, exibility,
and remote network management.
Civil government and public safety groups want access to new services and new fre-
quencies.
Radio vendors want reduced costs and increased exibility. The FCC is interested in the possibility of SDR-enabled spectrum sharing [15].
The original software-dened radio concepts came out of the defense sector [15]. One of
8 the rst major SDR projects was SPEAKeasy. SPEAKeasy was a military undertaking with the goal of creating a modular, reprogrammable modem with an open architecture [16]. At the end of Phase-2 for the SPEAKeasy project, the radio was able to handle AM and FM voice communications over a range of 4 MHz to 400 MHz. Both FPGAs and DSPs were used for digital processing. The units were so popular that production was initiated immediately instead of continued research and development. Other projects such as FM3TR, SoRDS, PMCS, and JCIT continued the research into SDR technology [15, 17, 18]. Recent developments in SDR have pushed for more standardization and interoperability [19]. The Joint Tactical Radio System (JTRS) is a government program which aims to replace legacy radio systems and to create a mobile ad-hoc networking program [20]. JTRS uses a open software architecture, the Software Communications Architecture (SCA), to dene the communication between the various hardware and software processing elements in a software-dened radio. The SCA is designed to [21]:
allow for portability of applications between SCA-compliant designs, use commercial standards, reduce software development time through module reuse, allow for evolving frameworks and architectures.
The SCA uses the Common Object Request Broker Architecture (CORBA) to allow an SCA-compliant radio system to perform its software processing across multiple processing elements. Although the SCA software is created to be run on general-purpose processors, the SCA acknowledges the use of FPGAs and DSPs as part of the digital processing in an SCA-compliant radio. Eorts are being made to standardize the interface between the general-purpose software of the SCA and specialized processors such as DSPs, FPGAs, and ASICs [22].
9
2.3
Ultra-Wideband Communications
A UWB signal, as dened by the FCC, is a signal with a minimum bandwidth of 500 MHz or a fractional bandwidth of at least 0.20 as measured from the -10dB emission points [23]. Fractional bandwidth is calculated as 2 fH fL fH + fL (2.1)
Where fH is the upper frequency of the -10dB emission point fL is the lower frequency of the -10dB emission point There has been much interest shown in UWB technology. UWB has been used for low probability of detection (LPD) radar, precision location, and communications [24, 4]. The DRACO system used UWB as the underlying technology for its radio transceiver. DRACO was able to operate over a distance of up to 2km and supported encrypted or unencrypted voice and data. An FPGA was used to perform the transceiver functions. Other systems such as the ORION transceiver and the SPIDER radar altimeter also leveraged UWB [24]. Other groups are interested in UWB as a good t for short-range communications. The WiMedia Alliance, with members including Intel, HP, Microsoft, Texas Instruments, Sony, and many others, has a mission of promoting worldwide UWB adoption and standardization [25]. UWB is the driving technology behind the Wireless USB specication [26, 27]. Wireless USB developers appreciate the ability of UWB to provide low cost and low power communications for consumer electronics. Wireless USB aims to provide 480 Mbps data rate at a range of 3 meters and 110 Mbps at 10 meters.
10
2.3.1
Impulse Ultra-Wideband Signals
There are two main types of UWB signals: multicarrier UWB (MC-UWB) and impulse UWB(I-UWB). Multicarrier UWB uses multiple carrier frequencies concurrently, whereas impulse UWB uses very short duration pulses. Because the transceiver described in this work is designed for use with I-UWB signals, MC-UWB is not discussed here. In the literature, the most popular I-UWB pulses are the Gaussian pulse and the derivatives thereof, so called because they are based on the Gaussian function [28]. The Gaussian pulse function is given as: G(x) = 1 2 2 ex
2 /(2 2 )
(2.2)
where =
pulse width . 2
Graphs of a Gaussian pulse, a Gaussian monocycle, and a Gaussian doublet can be found in Figure 2.2. In practice, an I-UWB transmitter does not generate a true Gaussian pulse, monocycle, or doublet. Instead, an approximation to the pulse, monocycle, or doublet is generate by analog hardware. Future transmitters may use high-speed direct digital synthesis to generate pulse waveforms. For an overview of analog UWB pulse generator circuits, see [29].
2.3.2
Impulse Ultra-Wideband Modulation Schemes
The modulation schemes available for an I-UWB system include Pulse Position Modulation (PPM), On-O Keying (OOK), and Pulse Amplitude Modulation (PAM). With pulse position modulation, information is stored in the time at which each pulse is received. Given a known base arrival time for each pulse, a pulse which arrives at the base arrival time is demodulated as a 1 and a pulse which arrives before or after the base arrival time is demodulated as a 0. The base arrival time for each pulse is equal to the last pulses base
11
0.8 0.8 0.7 0.6 0.6 0.4 0.5 Amplitude Amplitude 0.4 0.3 0.2 0.6 0.1 0.8 0 3 2 1 0 time (ns) 1 2 3 3 2 1 0 time (ns) 1 2 3 0.2 0 0.2 0.4
(a) Gaussian Pulse
(b) Gaussian Monocycle
0.4
0.2
0 Amplitude
0.2
0.4
0.6
0.8 3 2 1 0 time (ns) 1 2 3
(c) Gaussian Doublet
Figure 2.2: Typical Impulse UWB Pulses
12
"1"
"1"
"0"
"1"
amplitude
time
Figure 2.3: Pulse Position Modulation arrival time plus the pulse rate. An example of PPM can be seen in Figure 2.3. On-O Keying is a very simple modulation scheme that stores information in the absence or presence of a pulse. For each expected pulse arrival time, if a pulse is detected, then the signal is demodulated as a 1. If no pulse is detected, then the signal is demodulated as a 0. An example of OOK can be seen in Figure 2.4. Pulse Amplitude Modulation stores information in the amplitude of the transmitted pulse. For binary pulse amplitude modulation, either a positive or negative pulse is sent. A positive pulse is demodulated as a 1, whereas a negative pulse is demodulated as a 0. An example of PAM can be seen in Figure 2.5.
2.3.3
FCC Regulations
On February 14, 2002, the FCC adopted changes to its Part 15 rules to allow for the operation of UWB devices [23]. The Part 15 rules govern the emissions of unlicensed transmitters [30]. These rules were amended to allow for the use of UWB signals in a number of specic areas,
13
"1"
"1"
"0"
"1"
amplitude
time
Figure 2.4: On O Keying
"1"
"1"
"0"
"1"
amplitude
time
Figure 2.5: Pulse Amplitude Modulation
14 including:
Imaging systems
Ground penetrating radar Wall imaging Through-wall imaging Surveillance systems Medical systems
Vehicular Radar Communications and Measurement
The transmissions for systems in each of these areas are limited to specic frequency ranges [23]. For instance, ground penetrating radar systems and wall imaging systems must operate below 960 MHz or between 3.1 GHz and 10.6 GHz. Through-wall imaging systems can operate below 960 MHz or between 1.99 GHz and 10.6 GHz. Surveillance systems can operate in the 1.99-10.6 GHz band. Communications and measurement systems are limited to the 3.1-10.6 GHz band, as are medical systems.
2.4
Summary
Software-dened radio is a promising solution to the need for exible radio systems. As a testbed for radio research, SDR oers the ability to perform experiments in real time without the need for application-specic hardware. SDR can be leveraged to create a exible testbed for ultra-wideband communications, a technology which continues to gain interest from military and commercial sectors. FPGAs have been shown to be eective in signal processing tasks and are well suited to be used as the processing element in a softwaredened radio.
Chapter 3 Ultra-Wideband Transceiver System
This chapter presents an overview of the UWB SDR system, including the concept of timeinterleaved sampling, a discussion of the major parts of the system, and specications for the system. The two-ADC testbed system built previously is discussed, along with the eight-ADC receiver system and the UWB transmitter system. The main requirement that has driven the design and implementation of this SoftwareDened Radio platform is the need for a exible testbed for impulse ultra-wideband communications. To simplify the system design process, only COTS parts have been used. A Xilinx Virtex-II Pro FPGA has been chosen to handle the digital processing for the receiver. The design objectives for this system are as follows:
The receiver should be able to handle multiple modulation schemes: Pulse Amplitude
Modulation (PAM), Pulse Position Modulation (PPM), and On-O Keying (OOK).
The system should be able to operate at a maximum range of 10 meters. The receiver should be able to handle dierent receiver topologies: Leading Edge
Detection and Matched Filter.
Control over modulation and multiple access schemes, frame structure, and receiver
15
16 topology should be possible using software.
The system should also be able to operate with waveforms other than UWB.
Portions of this chapter are adapted from [1] with permission by the author. For a more in-depth analysis of the design and implementation of the transceiver system, see [1].
3.1
Time-Interleaved Sampling
This radio receiver platform uses Time-Interleaved (TI) sampling to digitize the analog input into the system. TI sampling uses an array of ADCs sampling the same signal consecutively at dierent instances in time to increase the sampling rate over a one-ADC conguration. If n ADCs are each sampling at a rate of f , then each ADCs clock signal is delayed by =
1 , fn
as compared to the preceding ADC. Figure 3.1 illustrates the use of TI sampling with a four ADC system. Using TI sampling increases the sampling rate without increasing the ADC clock rate. This allows for a greater data rate without an increase in the ADC-to-digital processor bus rate. Instead of one high-speed data bus, the ADCs present the processing element with multiple lower-speed data buses. TI sampling allows for easy parallel processing of the ADC data, because each ADC provides its own data stream. Both of these properties are attractive for an FPGA-based system. For multi-gigahertz sampling rates, single-ADC sampling is infeasible with an FPGA implementation without additional interface hardware.
3.2
Analog to Digital Converters
The ADC chosen for use in the radio receiver is the Maxim MAX104CHC. The MAX104CHC has a maximum sample rate of 1 G-samples/s and an input bandwidth of 2.2 GHz. This input bandwidth limits the UWB pulses that the receiver can receive to those with a bandwidth
17
(a) Block Diagram
(b) ADC Outputs [1]
Figure 3.1: Time-Interleaved Sampling with Four ADCs of 2.2 GHz or less. The ADC provides its digital output in two eight-bit buses, each running at half of the sample clock rate. The clock and reset inputs are fed to each ADC through delay chips; this implements the time-interleaved sampling. Instead of connecting the delay chips in series, as in Figure 3.1(a), each ADCs delay is controlled directly by one delay chip, as shown in Figure 3.4. This allows for the correction of delay mismatches between ADCs. The use of multiple ADCs introduces errors in the sampled signal, which would not be present in a single-ADC system. Gain or oset mismatches between ADCs distort the output. Variations in the aperture delay and the time between the ADC clock rising edge and the time at which the ADC samples the signal distort the signal. If the variation in the aperture delay between two ADCs is greater than or equal to the delay between ADC clock rising edges, then ADCs can sample at the same time or out of order. These phenomena all result in a degradation in the signal-to-noise ratio (SNR) of the receiver. These eects are illustrated in Figure 3.2. In this gure, ADC1 has ideal oset, gain, and timing characteristics while ADC2 has non-ideal characteristics. The input is a 100 Hz sine wave and each ADC samples
18 at a rate of 5 kHz. Tests show that these problems do not degrade the receiver SNR to an unacceptable level.
3.3
ADC Data Bus Timing Budget
In addition to the timing requirements introduced by the use of time-interleaved sampling, the window of time in which the FPGA must clock in the the ADC data puts stringent limits on the skew and jitter associated with the components in the system. At a data rate of 500 MHz, the FPGA has 2 ns to clock in each sample. Simulations show an ADC data bus rise time of 300 ps. The FPGA register setup time for a Virtex-II Pro -7 speed grade is 840 ps. The FPGA register hold time is negative and does not aect the timing budget. The worst-case ADC-to-FPGA data bus skew is 160 ps. The DCM skew, DCM granularity, and DCM jitter add up to a total of 415 ps. All of these factors plus an additional 10% timing margin add up to a total of 1885 ps to clock in data, giving a margin of error of 115 ps.
3.4
Field-Programmable Gate Array
A Xilinx Virtex-II Pro FPGA provides the digital processing for the radio receiver. The Virtex-II Pro has programmable logic fabric, embedded PowerPC processors, fast hardware multipliers, and Block RAMs. This allows for both hardware and software processing of the ADC sample data. The Virtex-II Pro also has Digital Clock Managers (DCMs) that synchronize the FPGA clocks to the external ADC clocks and generate the system clocks needed by the hardware and PowerPCs.
19
(a) Oset Mismatch Model
(b) Oset Mismatch Eects
(c) Gain Mismatch Model
(d) Gain Mismatch Eects
(e) Timing Mismatch Model
(f) Timing Mismatch Eects
Figure 3.2: Eects of ADC Mismatches on a Two-ADC Time-Interleaved Sampling System [1]
20
Figure 3.3: Xilinx Virtex-II Pro FPGA
3.5
RF Front End
The RF front end is designed with the objective of operating at a maximum range of 10 meters, while preserving the dynamic range of the system. The gain of the front end was chosen given the maximum tolerable input strength of the ADCs, the expected path loss at a range of 10 m, and the noise gure of the RF front end parts. A low pass lter prevents overdriving of the ADCs or ampliers by out-of-band signals. A variable attenuator is used to ne tune the gain of the RF front end. The front end is implemented using MiniCircuits parts in order to save cost and development time.
3.6
Prototype Board
Before beginning the design of the eight-ADC radio receiver board, a two-ADC prototype board was created. This board was created to test the feasibility of an FPGA-based timeinterleaved sampling radio receiver. The two-ADC prototype boards allowed for the testing of the TI sampling approach and served as a development platform for FPGA code. This
21
Figure 3.4: Test Board System Conguration board used two 1 GHz Maxim MAX104CHC ADCs and a Xilinx Virtex-II Pro XC2VP30-6 FPGA. The programmable delay chips were controlled by DIP-switches.
3.7
Final Radio Receiver Board
The nal radio receiver board is a scaled-up version of the test board. Instead of two ADCs, the radio receiver board uses eight Maxim MAX104CHC 1 GHz ADCs, for a maximum eective sampling rate of 8 G-samples/s. These ADCs are time-interleaved as they were on the test board. The programmable delay chips can be controlled by DIP switches or by the FPGA. A larger FPGA is used, the Virtex-II Pro XC2VP70-7. The XC2VP30 provides 13,696 logic slices, while the XC2VP70 provides 33,088 [31]. The XC2VP30 is insucient for the eight-ADC system, since more logic cells are needed than the XC2VP30 provides. A basic design using eight ADCs that receives the ADC sample data and exports the data over RS-232 uses almost 12,000 slices. Whereas the XC2VP30 part would be almost full, the XC2VP70 part has many slices left unused that can be used to implement radio receiver functionality. The XC2VP70 also provides more Block RAMs, hardware multipliers, and I/O pins than the XC2VP30.
22
Figure 3.5: Final Board System Conguration [1]
23
3.8
Transmitter Board
The radio receiver board controls an impulse-UWB transmitter board. The transmitter produces a 2 ns positive or negative UWB pulse when given a trigger pulse. These pulses are generated by an analog circuit whose main component is a step recovery diode. An in-depth discussion of the transmitter electronics is beyond the scope of this work. For more information, refer to [1]. A header on the receiver board that is connected to FPGA I/O pins is also connected via a ribbon cable to the transmitter board trigger signal inputs. This gives the FPGA control of the transmitter board. A positive pulse is produced on the falling edge of the positive trigger signal and a negative pulse is produced on the rising edge of the negative trigger signal. Because the FPGA controls the transmitter board, changes to the modulation scheme can be made in software. The FPGA can choose whether to transmit a positive or negative pulse and can also choose when to transmit a pulse. This allows the FPGA to select modulation schemes such as On-O Keying, Pulse Amplitude Modulation, and Pulse Position Modulation.
Chapter 4 FPGA Subsystem Design
The FPGA performs all of the digital processing in the radio receiver system. This chapter discusses the FPGA hardware and embedded PowerPC software for two systems: the pilotbased matched lter receiver and the vital signs monitoring application. Also discussed are issues involved in clock synchronization, which impact the time-interleaved sampling system.
4.1
ADC Data Capture
To process the ADC data samples, the FPGA must rst move all of the ADC samples over into one master clock domain. In this system, the ADCs are each presented with a 1 GHz input clock. This input clock is used to clock in 1 G-samples/s of data; however, the ADCs do not present this data to the FPGA as a single 1 G-samples/s stream of data. Instead, each ADC presents the FPGA with two 500 M-sample/s data streams, the ABus and PBus data buses. The ABus and PBus data buses are in-phase with each other and the ADC presents a data ready signal to announce the presence of the next data samples on the buses. The FPGA uses the data ready signal from each ADC as a clock. This clock is further reduced to half of its frequency inside the FPGA and each 500 M-sample/s
24
25
Figure 4.1: Data Capture Hardware Data Flow Diagram
26 bus is moved into two 250 M-sample/s buses, the 0 degrees bus and 180 degrees bus. A double-data rate (DDR) register inside an FPGA Input-Output Block (IOB) clocks data into the ABus0 and PBus0 buses on the rising edge of the 250 MHz clock generated by the FPGA and the ABus180 and PBus180 buses are clocked in on the falling edge of the same clock. These samples are then in eight dierent clock domains, one for each ADC. The samples from these clock domains are then moved to one master clock domain. The master clock domain is chosen to be the clock which is generated from the data ready signal from the earliest-sampling ADC. The samples are moved to the master clock domain by way of a synchronizer circuit, illustrated in Figure 4.2. This circuit breaks up the incoming 250 MHz data stream into two 125 MHz data streams, each clocked by the local clock. Each master clock cycle, the 125 MHz data stream which changed the earliest is clocked into the global clock domain. Moving the local data stream into two slower buses increases the amount of time from the change in the local bus to the global clock rising edge. This is illustrated in Figure 4.3.In this diagram, the top data stream is the local clock data stream. The middle two data streams are the two slower data streams created by the synchronizer circuit. The nal data stream is the global clock domain data stream. After all data streams have been moved into the global clock domain, a state machine moves the samples into Block RAMs (BRAMs) on the chip. The BRAMs are dual-ported memories that are connected to the hardware state machine on one port and a Processor Local Bus (PLB) on the other port so that the PowerPC can access the BRAMs. Section 4.2 describes this microprocessor system architecture. Figure 4.1 illustrates the ow of data from the ADCs to the BRAM, including synchronization steps discussed in the following sections.
27
Figure 4.2: Data Synchronizer Circuit [2]
Figure 4.3: Data Synchronizer Timing Diagram
28
BRAM PLB BUS
BRAM
BRAM
BRAM
PowerPC
BRAM PLBTOOPB BRIDGE OPB BUS RS232
BRAM
BRAM
BRAM
Figure 4.4: System Conguration for the Two-ADC Testboard
4.2
Processor System Architecture
The radio platform uses both congurable FPGA fabric and the internal PowerPC cores to process the ADC sample data. The internal dual-ported Block RAMs (BRAMs) are used to provide access to the sample data from the hardware to the processor. The PowerPC accesses the BRAMs and other peripherals through a Processor Local Bus (PLB). An RS-232 UART is accessed through a PLB-to-On-Chip Peripheral (OPB) bus bridge. The FPGA generates four data streams for each ADC and each data stream has its own Block RAM. Therefore, for the test board, which has two ADCs, eight BRAM controllers are needed. These eight BRAMs, along with the PLB-to-OPB bridge, are connected to the PLB bridge accessible by the PowerPC as illustrated in Figure 4.4. This system architecture is not scalable to the eight-ADC radio board. For the eight-ADC system, 32 BRAM controllers are needed. The PLB bus core available for the Virtex-II Pro FPGA allows for a maximum of 16 slaves on a single PLB bus. A novel PLB-to-PLB bridge developed by Eric Lorden [32] allows the PowerPC to connect to the 32 BRAMs and the RS-232 UART. The PLB-to-PLB bridge is used to increase the maximum number of slaves
29 accessible by the PowerPC over the PLB bus. Three additional PLB buses are needed to connect all of the PLB slaves. Two PLB buses connect to 16 BRAM controllers each, and a third bus connects to the PLB-to-OPB bridge which connects to the RS-232 UART. Each of these PLB buses connects to the PowerPC PLB bus via a PLB-to-PLB bridge. The PLB-to-OPB bridge is placed on its own PLB bus rather than the PowerPC PLB bus. This is done because only PLB-to-PLB bridges may be connected to the PowerPC PLB bus if PLB-to-PLB bridges are to be used. Figure 4.5 illustrates this new system architecture.
4.3
Clock Uncertainty and Synchronization
A time-interleaved software-dened radio relies on the dierence in phase between multiple clocks with the same frequency. When these clocks are reduced to half of their original frequency, uncertainty in the phase of the clocks is introduced. Steps must be taken to eliminate this uncertainty. There should be no uncertainty introduced into the system by the ADCs because the ADCs guarantee that at each data ready positive edge, the ABus is one sample older than the PBus. However, a problem with the ADC reset signals causes uncertainty to be introduced in the relative position of the ADC samples in their respective data streams. Individual ADCs reset at dierent clock cycles, causing the data streams for individual ADCs to be moved forward or backward in time. This problem is described in Section 4.3.2. A dierent problem dealing with clock uncertainty introduced by the FPGA is described in Section 4.3.1.
4.3.1
FPGA Clock Uncertainty
The generation of the 250 MHz clocks in the FPGA introduces uncertainty into the system. Figure 4.6 illustrates the two ways in which each 250 MHz clock can be generated by each 500 MHz ADC data ready signal. Each clock is generated by a dierent Digital Clock Manager (DCM) inside the FPGA. The DCM uses a divide-by-2 attribute to automatically divide
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
PLB BUS BRAM BRAM BRAM BRAM BRAM BRAM PLBTOPLB BRIDGE
BRAM
BRAM
PowerPC
OPB BUS RS232 PLBTOOPB BRIDGE PLBTOPLB BRIDGE
PLB BUS
PLB BUS
PLBTOPLB BRIDGE BRAM BRAM BRAM BRAM BRAM BRAM PLB BUS
BRAM
BRAM
Figure 4.5: System Conguration for the Eight-ADC Radio Board
BRAM BRAM BRAM BRAM BRAM BRAM
BRAM
BRAM
30
31
a) b) c)
a) 500 MHz data ready output from ADC b) 250 MHz clock generated by the FPGA, idealized with no skew c) Alternate 250 MHz clock generated by the FPGA Figure 4.6: The two ways in which the FPGA can generate the 250 MHz clock from the ADC data ready signal the input clock to half of its frequency. A feedback path is used to lock the output clock to the phase of the input clock. The DCM lock output is asserted when the phase of the DCM output clock matches that of the input clock. Because the output clock has twice the period of the input clock, the DCM has two input clock rising edges to every one output clock rising edge with which to lock. Locking to one input clock rising edge as opposed to another gives a 180 phase dierence on the output clock. The FPGA generates eight clocks, one for each ADC. Because the system is using timeinterleaved sampling, the ADC data ready clocks are out of phase with each other. Consequently, the FPGA-generated clocks are out of phase with each other. Ignoring skew, each ADC clocks rising edge occurs 125 ps later than previous clocks rising edge. If any of the FPGA-generated clocks are generated with the rising edge locked to the wrong edge of the input clock, then that clocks rising edge is 125 ps + 2 ns later than the previous clocks rising edge. This scenario is illustrated in Figure 4.7. All eight FPGA-generated clocks must be relatively in phase, as in Figure 4.7-a. If they are not, then the out-of-phase clocks place the samples meant for the ABus0 and PBus0 buses into the ABus180 and buses PBus180 instead. This causes the ABus data and the PBus data
32
a)
b)
a) Three clocks relatively in phase b) Two clocks relatively in phase, one clock 180 out of phase Figure 4.7: Relative phases between dierent FPGA-generated clocks to be one master clock cycle ahead relative to the other clocks. Figure 4.8 illustrates this problem. Figures 4.8-a and 4.8-b show the ADC data ready clock signal and the ABus and PBus data buses. Figure 4.8-c shows the FPGA DCM-generated clock with the correct phase relative to the master FPGA, which is shown in Figure 4.8-k. The ABus0, PBus0, ABus180, and PBus180 buses receive the data as shown in Figures 4.8-d and 4.8-e. These buses are clocked into the same local clock domain as in Figure 4.83-f. The same process occurs in Figures 4.8-h through 4.8-j, except the local clock is 180 out of phase from its correct phase. As seen in Figure 4.8-j, ABus0 receives the next ABus180 signal and ABus180 receives the next ABus0 signal. PBus0 receives the next PBus180 signal and PBus180 receives the next PBus0 signal. As shown in Figures 4.8-l and 4.8-m, when the samples are moved to the master clock domain, the correct FPGA clock causes ABus samples 1 and 2 and PBus samples 2 and 3 to be read. The incorrect FPGA clock causes ABus samples 2 and 3 and PBus samples 3 and 4 to be read. The solution to this problem is to determine whether the phase of each clock is correct with respect to a master clock and to change the phase if it is incorrect. To determine if
33
500 MHz Clock from ADC a)
b)
ABUS 1 PBUS 2
ABUS 2 PBUS 3
ABUS 3 PBUS 4
ABUS 4 PBUS 5
ABUS 5 PBUS 6
ADC ABUS and PBUS
250 MHz FPGA DCMGenerated Clock c)
d)
ABUS 1 PBUS 2 ABUS 2 PBUS 3
ABUS 3 PBUS 4 ABUS 4 PBUS 5 ABUS 1 PBUS 2 ABUS 2 PBUS 3
ABUS 5 PBUS 6
ABUS 0 Degree PBUS 0 Degree ABUS 180 Degree PBUS 180 Degree Locally Clocked Buses
e)
f)
250 MHz FPGA DCMGenerated Clock 1/2 period behind g)
h) ABUS 1 PBUS 2
ABUS 2 PBUS 3 ABUS 3 PBUS 4
ABUS 4 PBUS 5 ABUS 5 PBUS 6
ABUS 0 Degree PBUS 0 Degree ABUS 180 Degree PBUS 180 Degree
i)
j)
ABUS 2 PBUS 3 ABUS 3 PBUS 4
Locally Clocked Buses
k)
250 MHz Master FPGA Clock
l)
ABUS 1 PBUS 2 ABUS 2 PBUS 3 ABUS 2 PBUS 3 ABUS 3 PBUS 4
From Correct Local Clock
m)
Buses Clocked to Master Clock From Incorrect Local Clock
Figure 4.8: Input of Samples from Local Clock Domain with Correct and Incorrect Local Clocks
34
Local Clock
D
Q
Change Clock?
Master Clock
Figure 4.9: Method to Determine if Local Clock is Relatively In Phase with Master Clock
Correct Local Clock
a)
Incorrect Local Clock
b)
c)
a) Master Clock b) Local Clock c) Change Phase Output Figure 4.10: Waveforms from Phase Checking Circuit
35 a local clock is relatively in phase with the master clock, the local clock is clocked into a ip-op which is clocked by the master clock. The master clock is the clock generated from the ADC1 data ready signal. This clocks rising edge will always occur before the other clocks edges. If the local clock has the correct phase, then, when the master clocks rising edge occurs, the local clock is low. If the local clock has the incorrect phase, then, when the master clocks rising edge occurs, the local clock is high. These two scenarios are illustrated in Figure 4.10. On the left, the local clock has the correct phase, while on the right, the local clock has the incorrect phase. The signal generated by this ip-op can then be used to change the phase of the DCM. This can be accomplished in two dierent ways. The DCM reset signal can be used to change the phase of the DCM. When the DCM is reset, there is a 50% chance that the DCM will lock to the correct phase. If the DCM does not lock to the correct phase then the DCM is reset again. As shown in Figure 4.11, this can be accomplished by conditionally resetting the DCM if the DCM is locked and if the DCMs phase is incorrect. Correcting the DCM phase can also be accomplished by manually adjusting the phase. The DCM provides ne phase adjust signals which allow the user to adjust the phase by 1/256th of the clock period at a time. When a clock is found to have the incorrect phase, a state machine controlling the DCM phase adjust signals can cause the DCM to adjust its phase 128 times to shift the phase by 180. Either of these methods will solve the DCM phase uncertainty problem. The DCM reset solution is implemented in this system.
4.3.2
ADC Reset Uncertainty
As introduced earlier, the ADCs should not introduce any uncertainty into the system. Each ADC guarantees that its ABus contains the sample that is one sample earlier than its PBus during each data ready cycle. They are also reset using one master reset signal which is fed through the delay chips to the ADCs. This should ensure that each ADC comes out of reset at the correct time. However, there is an issue with the receiver board which causes
36
DCM CLK OUT
MASTER CLK
CLK IN
D
Q
RESET FEEDBACK CLK LOCK
Figure 4.11: Method to correct DCM phase the ADCs to reset at dierent ADC input clock cycles. Section 5.3 describes tests performed which show that this problem does not arise in the FPGA. If an ADC resets one clock cycle later than it should, then its ABus output contains the sample which should go in the current PBus output. The PBus contains the sample which should go in the next ABus. Testing has shown that there can be as much as a two-cycle dierence between ADC sample streams. Because the relationship between the ADCs is dierent each time the ADCs are reset, a x for this problem cannot be determined a priori. The solution chosen to counteract this problem is a queue in the FPGA for each ADC data stream. Each queue receives one ADCs ABus0, ABus180, PBus0, and PBus180 signals every clock cycle. The queue stores three cycles worth of samples and a pointer tells the queue what four signals to send out. The pointer is initialized to point to the middle cycles samples, which allows the queue to move the ADCs data stream forward or backward up to four samples. Figure 4.12 shows an ADC sample queue pointing to the middle samples PBus0 sample, PBus0 1. Assuming all other ADC queues point to ABus0 1 then this ADCs samples will be moved forward in time by one sample. The same can be done to move an ADCs sample backward in time by one sample by setting the pointer for that ADC to point to PBus180 0. These queues each receive an initial pointer value when the FPGA is reset, but the pointer must be set correctly to counteract osets in the ADC data streams created by incorrect
37
PBUS180 2 ABUS180 2 PBUS0 2 ABUS0 2 PBUS180 1 ABUS180 1 POINTER PBUS0 1 ABUS0 1 PBUS180 INPUT ABUS180 INPUT PBUS0 INPUT ABUS0 INPUT PBUS180 0 ABUS180 0 PBUS0 0 ABUS0 0 PBUS180 OUTPUT ABUS180 OUTPUT PBUS0 OUTPUT ABUS0 OUTPUT
Figure 4.12: ADC Sample Queue for ADC Reset Correction
38 ADC resets. This is accomplished by giving the PowerPC inside the FPGA control over the queue pointers via the Device Control Register (DCR) bus. The DCR bus is a bus for which the PowerPC is a master and the FPGA hardware is a slave. Instructions exist which give the PowerPC software access to the DCR bus. The queue pointer values can be determined manually by an operator by analyzing the output of the data capture hardware given a known signal such as a sinusoid. The operator can then inform the PowerPC of the ADC queue pointer values via a serial port interface. It is also possible to create PowerPC software to automatically determine the ADC queue pointer values at startup given a known training sequence. Manual selection of the queue pointer values is implemented in this system. After the DCM phases have been corrected, the samples are moved from the ADC ABuses and PBuses, through DDR registers, clock domain synchronizers, and the ADC sample queues, and into the BRAMs.
Figure 4.13: PBMF Receiver Block Diagram
4.4
Pilot-Based Matched Filtering Receiver
The receiver topology chosen for the UWB receiver is Pilot-Based Matched Filtering (PBMF). Pilot-Based matched ltering creates a stored copy of the incoming pulse to account for any
39
Shaded Area Performed in Software Figure 4.14: PBMF Receiver Dataow Diagram multipath signals or distortions. This stored version of the pulse is used as the waveform against which the incoming samples are correlated using a matched lter operation. There are four steps involved in the PBMF receiver system: acquisition, pilot pulse reception, data demodulation, and real-time tracking. Figure 4.13 shows the communication block diagram for the system and Figure 4.14 shows the data ow diagram. These two gures are related to elements in the FPGA in Figure 4.15. An input data rate of 6.4 GHz is used for the PBMFR. This corresponds to an ADC input clock rate of 800 MHz. This data rate was chosen to make the creation of the FPGA bitstream more feasible in the allotted time. A decreased data rate equates to a decreased FPGA clock rate.
4.4.1
Acquisition
Before pulses can be demodulated correctly, the receiver must discover the arrival time of the incoming pulses. This is accomplished by nding the arrival time of a maximal-length sequence (m-sequence) sent by the transmitter. An m-sequence is used because m-sequences have attractive autocorrelation functions; the correlation between the m-sequence and itself is high whereas the correlation between the m-sequence and a shifted version of itself is very low [33]. This m-sequence is sent by the transmitter until the receiver acknowledges correct
40
Figure 4.15: PBMF Receiver FPGA Diagram
41 reception of the sequence. To do so, the receiver captures a number of samples into the BRAMs so that the PowerPC can perform a sliding window matched lter operation on the samples. The receiver captures twice the number of samples per m-sequence so that any possible starting location can be tried against the matched lter. The hardware and PowerPC software maintain synchronization with a hardware counter, sampleCount which wraps around at N P , where N is the number of pulses per m-sequence and P is the number of samples per pulse. For this particular implementation, a seven-pulse m-sequence is used, with 80 samples per pulse. Thirty-two samples are collected each master clock cycle, so the m-sequence repeats itself every 17.5 master clock cycles. To simplify the hardware, sampleCount is implemented as a modulo-35 counter in the master clock domain. This causes sampleCount to wrap around after two m-sequences have arrived. The PowerPC synchronizes with sampleCount using a DCR bus-controlled register, triggerCount. The PowerPC writes a value to triggerCount and, using another DCR bus register, signals the hardware to begin lling the BRAMs the next time triggerCount equals sampleCount.
Coarse Acquisition The properties of the m-sequence were chosen given that the transmitters oscillator and the receivers oscillator are not perfectly synchronized. This imperfect synchronization causes them to drift apart during acquisition. Thus there is an upper bound on the time which acquisition can take. This uncertainty window is given by Equation 4.1 [2]: Umax = 2 fosc Sosc telapsed 106 (4.1)
where Umax is the uncertainty window [Number of Samples], fosc is the frequency of the master oscillators [Hz], Sosc is the stability of the master oscillators [Parts Per Million], and telapsed is the time required to complete acquisition [s].
42 The following is adapted from [2]. The maximum tolerable uncertainty window is found experimentally to be half the number of samples per pulse (40 samples for this system). The oscillators operate at 800 MHz with an estimated stability of 26.67 PPM stability. These parameters give an upper bound of 937.5 s to the initial acquisition time. The PowerPC, operating at 300 MHz, is thus given 281,249 cycles to complete the initial acquisition. The sliding window correlation function is given by Equation 4.2 [2]:
80N 1
CK =
i=0
xi+K yi
(4.2)
where K is the starting index in the captured data, CK is the correlation magnitude, xi is the captured data at position i, yi is the template data at position i, and N is the number of pulses in the acquisition m-sequence. Because the UWB pulse is only 2ns long, which equates to 13 samples, the correlation only needs to be performed on 13 out of every 80 samples. For a N length m-sequence, the PowerPC performs 13N correlations. In [2] the authors estimate that each iteration requires 25 cycles. Because a starting location of several samples shifted from the correct starting location will still correlate strongly with the template waveform, the starting index can be incremented by more than one. The starting index K is chosen to be incremented by 8, giving an error of 4 samples from the correct starting sample in the m-sequence. This gives KM AX possible starting indices [2]: KM AX = N ( 80 ) = 10N 8 (4.3)
This gives a total number of PowerPC cycles of [2]: M axCycles = (25)(13N )(10N ) = 3250N 2 (4.4)
43 The m-sequences can only have 2x 1 pulses, where x is a positive integer. A seven-pulse m-sequence takes 159,250 PowerPC cycles to perform initial acquisition whereas a fteenpulse m-sequence requires 731,250 PowerPC cycles. Thus, a seven-pulse m-sequence is used, giving an uncertainty window of 22.65 samples. To perform this coarse acquisition step, the PowerPC instructs the hardware to begin lling the BRAMs the next time sampleCount equals zero. The hardware signals the PowerPC via the DCR bus that at least 2N P samples have been put into the BRAMs. The PowerPC then uses the sliding window correlation function described in Equation 4.2 to nd the approximate index of the start of the next m-sequence. This index is then used to perform the ne acquisition step.
Fine Acquisition As described above, the coarse acquisition stage nds the start of the next m-sequence with an error of 11.32 samples. The ne acquisition stage reduces the error in the start index to 3 samples. In order to do so, the PowerPC performs another sliding window correlation. First, a new set of samples is acquired. Given the start index calculated by the coarse acquisition phase, the PowerPC sets triggerCount such that: triggerCount = iC 32
U 2
(4.5)
where iC is the start index computed by the coarse acquisition phase, U is the uncertainty window, N is the number of pulses per m-sequence, and P is the number of samples per pulse. This gives triggerCount =
iC 14 32
for this systems parameters. After setting the triggerCount
register and triggering the hardware to capture new data, the PowerPC performs the sliding
44 window correlation. However, instead of incrementing the start index by 8, the PowerPC increments the start index by 4 after each correlation. The PowerPC only searches the uncertainty window for the start of the m-sequence, so for an uncertainty window length of 22.64, the PowerPC will perform seven correlations will require (13 6 correlations/pulse 7 pulses 25 cycles/correlation) (4.6)
28 4
= 7 correlations in the ne acquisition phase. These
cycles, approximately 13,600 cycles, to complete. After nding the new starting index for the next m-sequence, the PowerPC updates triggerCount so that the data demodulation hardware knows the starting location of the incoming pulses. The triggerCount register will only be updated if the ne acquisition phase nds that the actual start of the m-sequence is in a dierent cycles set of 32 samples. The updated triggerCount is set such that: triggerCount = (triggerCount + iF /32) mod SM AX (4.7)
where iF is the start index computed by the ne acquisition and SM AX is the number before which sampleCount wraps around. The next m-sequence will start when sampleCount equals triggerCount, at sample number iF mod SM AX in that set of 32 samples. The oscillator drift that occurs during the ne acquisition phase leaves an uncertainty window of two samples and the correlations only guarantee to nd the true starting index within a 2 sample margin of error. These phase errors are corrected by a real-time tracking component which is described later.
4.4.2
Pilot Pulse Reception
After the receiver successfully nds the starting index of the next m-sequence, it signals the transmitter to begin sending test frames. Each frame consists of a known pilot pulse sequence
45 and data symbols. The pilot pulse sequence serves two purposes. The aforementioned realtime tracking component has a chance to correct any phase error. Also, the receiver is able to average several pilot pulses into a new template which accounts for any distortions and takes advantage of any multipath energy. The PowerPC is used to average the pilot pulses to create a template for the matched lter hardware. After processing the test frames, the receiver signals the transmitter to begin sending data frames which will be demodulated by the hardware.
4.4.3
Data Demodulation
The data demodulation hardware performs a matched lter operation on the incoming data samples. Because each incoming pulse is 80 samples wide and 32 samples are received each master clock cycle, specialized hardware is required to implement the multipliers and adder tree needed to perform the matched lter function. The matched lter function is [2]:
79
Z=
i=0
xi yi
(4.8)
Where Z is the output of the matched lter function, xi is the ith ADC sample value for the current pulse, and yi is the ith template coecient value for the current pulse.
Partial Correlation Unit Each of the 32 data streams is given a dedicated multiply and accumulate module whose inputs are the current incoming sample, the current template sample associated with that data stream, and a schedule which controls the modules operation. The incoming sample and the template sample are both signed 8-bit values. This module, called the Partial Correlation Unit (PCU), is illustrated in Figure 4.16. When the schedule input to the PCU
46
Figure 4.16: Partial Correlation Unit [2] equals 1, the PCU adds the current multiplier output to the accumulator register. When the schedule input equals zero, the PCUs accumulator output contains the partial sum for that data streams samples in the current pulse. Next cycle, the PCU will reset the accumulator register to the output of the multiplier. The partial sums generated by the 32 PCUs are fed to an adder tree which adds together the partial sums to generate a full sum for the current pulse.
Schedule and Coecient Generation The PCUs are each controlled by a schedule input. These schedule inputs are generated so that when a PCU encounters its rst sample for a given pulse, its schedule input is 0, otherwise its schedule input is a 1. Because there are 80 samples per pulse and 32 samples per cycle, the 32-bit schedule register cycles between ve dierent values. Figure 4.17 shows what the schedule register will be if even-numbered pulses begin at ABus0 for ADC0, which is the zeroth data stream. Each set of 32 bits represents the schedule register value for a
47
PULSE 0 SAMPLES 0x0000 0000 0xFFFF FFFF PULSE 1 SAMPLES 0x0000 FFFF 0xFFFF
0x0000
0xFFFF FFFF
Figure 4.17: Schedule Register for Pulse Beginning at Sample 0 given cycle. If the even-numbered pulses begin n samples into the rst set of 32 samples, then the schedule register will contain the same values, circular shifted to the right n times. The PowerPC determines the initial value of this schedule register during the acquisition phase. The schedule register will be shifted to the right iF mod 32 times, where iF is the start index computed by the ne acquisition. The coecients are generated in the same way. The PowerPC circular right shifts the standard pulse template by the same amount as the schedule register. The total schedule chain and coecient chain are not stored as 160-sample chains. Only 80 samples are needed to store them; the last 80 schedule bits and coecient values are the same as the rst 80. After creating the schedule chain and the coecient chain, the PowerPC sends them to the hardware one by one via the DCR bus. As the hardware receives the schedule and coecient data it shifts them into the hardware scheduleReg and coefficientReg. These are the registers used to generate the schedules and coecients for the 32 PCUs. As stated, these values cycle between ve dierent states. Using the schedule register as an example, for PCU number i, the schedule input cycles between: scheduleReg(i), scheduleReg(i + 32), scheduleReg((i + 64) mod 80), scheduleReg(i + 16), and scheduleReg((i + 48) mod 80). The PowerPC sets triggerCount as shown in Equation 4.7 and triggers the schedule and coecient generator to initialize its outputs when triggerCount equals sampleCount. This synchronizes the PowerPC to the schedule and coecient generator. Using these values, the PCUs demodulate the incoming data samples.
48 Adder Tree and Comparator The partial sums generated by the PCUs are added together into the full sum for the current pulse using a multi-stage adder tree. This full sum, a 16-bit signed value, is fed to a comparator which decides the value of the current bit given the full sum value. The threshold against which the full sum is compared is controllable by the PowerPC via the DCR bus. Given a full sum of Z, for binary pulse-amplitude modulation (2-PAM), Z > 0 indicates that a 1 was transmitted, while Z < 0 indicates that a 0 was transmitted. For On-O Keying (OOK), Z > a set threshold value indicates a 1 was transmitted while Z < the threshold indicates a 0 was transmitted.
4.4.4
Real-Time Tracking
The receiver and transmitter oscillators will continuously drift apart due to imperfect synchronization. The real-time tracking module helps the receiver and transmitter maintain synchronization after the acquisition phase. To do so, the data demodulator provides three outputs instead of one: the on-time full sum, the full sum for the samples correlated to a template one sample late, and the full sum for the samples correlated to a template one sample early. The two additional coecient and schedule registers are provided by the schedule and coecient generator. The comparator module that determines the output bits from the on-time full sum also determines if the early template sum correlates better with the incoming samples. If so, the schedule and coecient generator is signaled to shift its outputs so that the on-time template is set to the former early template. The same occurs if the late template is found to correlate better than the on-time template.
49
Figure 4.18: Vital Signs System Overview
4.5
Vital Signs Monitor
This system is also t for use in problem domains other than communications, such as biomedical analysis. In [34], it is shown that Impulse-UWB can be used to remotely detect changes in a persons breathing rate or heart rate. A displacement of the chest causes a change in the multipath of an Impulse-UWB signal. Multiple pulses are sent and received and the average of all the pulses is subtracted out from each pulse to remove the static information. For a Fast Fourier Transform taken along the time where the multipath changes, the frequency that contains the peak of the FFT output is equal to the breathing rate of the subject. To perform this function, the data capture receiver hardware is used in conjunction with the transmitter board. FPGA hardware triggers the transmitter board to send pulses at a rate of 8 MHz. The pulse generator hardware also signals the BRAMs to begin capturing samples each time a pulse is generated. These pulses bounce o of the chest of the subject and the initial pulse and multipath signals are received by the FPGA and placed in the BRAMs. After multiple pulses have been acquired, the PowerPC averages the pulses together and subtracts the average from the captured data. The result is sent to a host PC connected via serial port. The host PC performs the FFT operation to nd the breathing rate.
Chapter 5 Results
This chapter reports the results gained from the UWB SDR system. The eight-ADC system was fabricated and tests were constructed to demonstrate correct operation of the board and the FPGA. Time-interleaved data capture using eight ADCs with an eective sampling frequency of 6.4 G-samples/s was performed. The vital signs monitoring system was implemented and tested and the pilot-based matched lter receiver was partially implemented.
5.1
Initial System Testing
To test the functionality of the eight-ADC system after its fabrication, several basic FPGA bitstreams were created. First, an empty bitstream was created in Xilinx FPGA Editor to ensure that the FPGA could be programmed correctly. Another set of bitstreams tested the clocking resources on the board. One bitstream used several counters, each one clocked by a dierent ADC data ready clock. These counters were connected to the LEDs on the receiver board to demonstrate operation of the ADC clocks. A similar bitstream also connected a counter to the LEDs on the receiver board. However, this counter was clocked
50
51
Figure 5.1: Radio Receiver Board
52 by the on-board 100 MHz oscillator to ensure that this oscillator was operational. Because of a shortage of DCMs on the FPGA, this oscillator was not used to generate the PowerPC clock as was intended, although the oscillator could be used for other systems which require a 100 MHz clock. Overall, these tests showed that the FPGA had at least rudimentary functionality.
5.2
Data Capture
The data capture hardware was built and tested for an ADC input clock rate of 800 MHz resulting in an eective sampling frequency of 6.4 G-samples/s. The hardware was built for 800 MHz, rather than 1 GHz to save development time, meaning that the data capture hardware inside the FPGA ran at 200 MHz instead of 250 MHz. Increasing the maximum frequency to 250 MHz would require much more processing time to create a valid bitstream. Many more runs of the Xilinx tool place-and-route would be needed to nd a solution whose placement and routing allowed for a maximum frequency of 250 MHz. The data capture hardware required 35% of slices in the Xilinx XC2VP70 FPGA. The dynamic range of the receiver system is illustrated in Figures 5.2 and 5.3. A 393 MHz sine wave was captured with a dynamic range of 37 dB. A 793 MHz sine wave was captured with a dynamic range of 28 dB. The theoretical maximum dynamic range, or signal-to-noise ratio, is: SN R = (B 6.02) + 1.76 (5.1)
where SN R is the signal to noise ratio, B is the number of bits of precision for the ADC. This gives a maximum SNR of 49.92 dB. The reduction in SNR from the ideal best case is partially caused by ADC timing, gain, and oset mismatches introduced by the TI sampling
53
250
0
ADC Output Code
200
Relative Power (dB)
10 20 30 40 50 60 70 80
37 dB
150
100
50
0 0
2
4
6
8
10
90 0
500
1000
1500
2000
2500
3000
time (ns)
Frequency (MHz)
(a) Time Domain Output
(b) Frequency Domain Output
Figure 5.2: 393 MHz Sine Wave Input Captured With 6.4 GHz Sampling Rate [1] system [1, 35, 36, 37, 38]. An input data rate of 6.4 GHz was sucient to accurately sample and reconstruct a UWB pulse. Figure 5.4 shows the dierence in a UWB pulse captured by the 6.4 GHz input bandwidth data capture and the sample pulse captured by an oscilloscope. Fig...