Manual
January HSP50215EVAL
Semiconductor
Users 1999
File Number
4463.3
DSP Modulator Evaluation Board
Evaluation Kit
The HSP50215EVAL Kit provides the necessary tools to evaluate the HSP50215 Digital Upconverter integrated circuit and consists of a circuit board and a software program. The kit is designed for evaluation of Digital Quadrature Amplitude, FM, and Shaped FM modulation for IF Communications Applications. The circuit board uses baseband I and Q data patterns loaded through the 8-bit parallel interface or the ISAbus interface. Data is output as either a digital or analog modulated composite IF signal. Up to four channels can be included in the composite IF output. To facilitate the use of the board during evaluation, the kit includes example les for conguration, shaping lters and input stimulus.
Features
Multi-Channel Composite IF Output with 1-4 Channels Digital or Analog Composite Output Baseband Pattern Stimulus Files with Lengths to 64Kbits Example Baseband Patterns for BPSK, QPSK, /4QPSK, 16QAM, FM, GMSK and AWG Noise Baseband Patterns Loaded to RAM Via PC ISAbus or Parallel Port, for Use as Modulator Baseband Data DOS Based Conguration/Status Software
Applications
Evaluation Tool for the Performance of the Digital UpConverter Congured as PSK, Quadrature Amplitude (QAM), FM and Shaped FM (MSK) Modulators at Rates from <1 KBPS to 1.5 MBPS Performance Evaluation Tool for Digital Upconversion Communications Test Equipment
Circuit Board
The Functional Block Diagram illustrates the major functions of the circuit board. The circuit board is a ISAbus form factor with 40 pin I/O header/connectors for cascade and output signals. Baseband test patterns are loaded through the ISAbus or 8-bit parallel interface. The external Cascade Input allows expansion of the number of channels in the composite signal. The board outputs data through both the RF connector and the 40 pin header. Test connectors are provided at key signal and control locations in the circuit.
Functional Block Diagram
HSP50215 DIGITAL UPCONVERTER CHANNEL 4 HSP50215 DIGITAL UPCONVERTER CHANNEL 3 HSP50215 DIGITAL UPCONVERTER CHANNEL 2 HSP50215 DIGITAL UPCONVERTER CHANNEL 1 ANALOG DIGITAL IF OUTPUT IF OUTPUT 40 PIN CONNECTOR 16 40 PIN CONNECTOR 16 16 16 16 14 D/A VCC -12V RAM DATA ADDRESS PARALLEL 8 RAM RAM INTERFACE BUS (INPUT DATA PATH AND CONTROL/STATUS INTERFACE) RAM FPGA FPGA FPGA FPGA HI5741
(CASCADE INPUT)
(OPTIONAL FINAL STAGE BASEBAND DATA INPUT PATH) DATA ADDRESS WR
8 ISABUS
DATA ADDRESS WR VCC -12V ADDRESS DECODE CLK
OSC
INTERNAL CLOCKS
3-443
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-800-4-HARRIS or 407-727-9207 | Copyright Harris Corporation 1999
HSP50215EVAL Table of Contents
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Software Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 1. MENU TREE FOR THE CONTROL/STATUS SOFTWARE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conguration/Test Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Evaluation Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evaluation Circuit Board Conguration and Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Requirements for the Control Software Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installing the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 2. TYPICAL MODULATOR PERFORMANCE EVALUATION CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verifying the Control Software and Board Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 3. MAIN MENU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 4. BOARD INTERFACE SUBMENU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 5. TEST SUBMENU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running the Control Software for Evaluation Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 6. MODULATOR CHANNEL CONFIGURATION SUBMENU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 7. BOARD INTERFACE SUBMENU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 8. CONFIGURE CHANNEL 1 SUBMENU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Learning Your Way Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exercise #1: Generating A CW Tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exercise #2: Adjusting the level of the CW Tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exercise #3: Modulating the CW Tone with PN Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exercise #4: CW and a Modulated Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exercise #5: A Fourier Series Composite Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exercise #6: Generating Additive White Gaussian Noise (AWGN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Background on Eb/No and SNR Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . An Example Eb/No Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exercise #7: PRBS Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generating User Congurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation Channel 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation Channel 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation Channel 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation Channel 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC/Controller Interface Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISA Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Interface Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jumpered Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Evaluation Congurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non ISA (PC installed) Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Modulator Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using SERINADE Designed Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A - Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix B - Initial Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix C - Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix D - Test Header Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix E - Detailed Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix F - Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix G - Descriptive File List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Conguration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Filter Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 9. IS136B.IMP FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 10. RRC2A4X.IMP FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 11. GS5T16X.IMP FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 12. S95MOD.IMP FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 13. AMPS2.IMP FREQUENCY RESPONSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 14. RRC35A4X.IMP FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 15. GP1.IMP FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIGURE 16. GP2.IMP FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Stimulus Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix H - Detailed Menu Item Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE
3-443 3-445 3-445 3-446 3-446 3-446 3-446 3-446 3-446 3-446 3-447 3-447 3-447 3-447 3-448 3-448 3-448 3-448 3-449 3-449 3-450 3-450 3-451 3-451 3-451 3-452 3-453 3-453 3-453 3-454 3-454 3-454 3-454 3-454 3-454 3-455 3-455 3-455 3-455 3-455 3-455 3-455 3-455 3-456 3-456 3-456 3-457 3-459 3-461 3-464 3-476 3-477 3-477 3-479 3-480 3-480 3-481 3-481 3-482 3-482 3-483 3-483 3-484 3-485
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HSP50215EVAL Control Software Program
The control software program, written for DOS based PCs, is included in the evaluation kit. This software supports operation of the evaluation circuit board in basic quadrature ASK and FM modulation configurations The control software MAIN MENU offers six submenus for various configuration selections and three command actions. The menu tree is illustrated in Figure 1. The 7 configuration submenus are: Board Configuration Menu Modulator Channel 1 Configuration Menu Modulator Channel 2 Configuration Menu Modulator Channel 3 Configuration Menu Modulator Channel 4 Configuration Menu Configure Board Menu Test Menu The four command actions are: Load Configuration File Save Configuration File Compute Registers Exit A typical operational sequence is: A. Load Configuration File Executing MAIN MENU item (5) brings up a screen with the current file name and requests the name of the file to be loaded. Once the new file name is entered, this command loads the configuration setup and returns to the MAIN MENU screen. This command allows the user to select a previously saved configuration file for display, review and editing. B. Edit Configuration File This is done by sequencing through each of the configuration submenus and adjusting the parameters for the desired hardware configuration. - The BOARD CONFIGURATION MENU is used to select control interface type, printer port (PRN) number, FPGA addressing, and oscillator frequency. - The MODULATOR CHANNEL CONFIGURATION MENUS are used to select carrier center frequency, input sample rate, modulation type, coefficient file name, interpolation factor, impulse response length, Stimulus file name, number of data samples, output attenuation, output enabling, cascade input control, synchronization, synchronization polarity, FIFO depth, Output Format, and test register settings. There is a menu for each of the four modulator channels on the evaluation board. C. Save Configuration File Executing MAIN MENU item (6) brings up a screen with the current file name and a request for a file name to be saved. Once the new file name is entered, this command stores the configuration setup to the new file.
WARNING: Failure to change the .cfg file name may result in overwriting of an example file with an edited version of that file.
D. Compute Registers This command will use the configuration data entered in MAIN menu items 0-4, and generate a number of files which contain the register values for the ICs on the evaluation circuit board. The computation is based on a .cfg file, which contains filter (.imp) and stimulus (.imp) files for each of the 4 channels. The computed register values are stored in a set of files identified by the suffix of .1, .2, .3 and .4, indicating the channel to which the parameters apply. The actual filename preceding the .1, .2, .3 or .4 suffix is automatically assigned to be the Configuration file filename.
MAIN MENU (5) LOAD CONFIGURATION FILE (6) SAVE CONFIGURATION FILE (0) (1) (2) (7) COMPUTE REGISTERS (10) EXIT (3) (4) (8) (9)
BOARD CONFIGURATION
MODULATOR CHANNEL 1 CONFIGURATION
MODULATOR CHANNEL 2 CONFIGURATION
MODULATOR CHANNEL 3 CONFIGURATION
MODULATOR CHANNEL 4 CONFIGURATION
CONFIGURE BOARD
TEST
(1)
ENTER NEW VALUE MENU
(1)
ENTER NEW VALUE MENU
(1)
ENTER NEW VALUE MENU
(1)
ENTER NEW VALUE MENU
(1)
ENTER NEW VALUE MENU
(1)
COMMAND (1) #1
COMMAND #1
(7)
ENTER NEW VALUE MENU
(16)
ENTER NEW VALUE MENU
(16)
ENTER NEW VALUE MENU
(16)
ENTER NEW VALUE MENU
(16)
ENTER NEW VALUE MENU
(5)
COMMAND (3) #2
COMMAND #2
FIGURE 1. MENU TREE FOR THE CONTROL/STATUS SOFTWARE
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HSP50215EVAL
E. Congure Board Menu This command accesses a menu called the BOARD, INTERFACE MENU. The BOARD, INTERFACE MENU is used to select among several board congure command options, including congure channel 1, congure channel 2, congure channel 3, congure channel 4, or congure all modulator channels. D. Test Menu This command accesses a menu called the TEST MENU. The TEST MENU is used to select among several run options, including reset the board, write to a location while reset, read to a location while reset, write to a location while running, or read from a location while running. For a detailed listing of every Menu screen, with selection item denitions, refer to Appendix G - Descriptive File List.
Evaluation Circuit Board Conguration and Set Up
1. ___ Power down the host PC and remove the cover to allow access to the motherboard empty slots. 2. ___ Review the jumper configuration of the HSP50215EVAL Board to verify that the jumpers are properly set for the configuration desired. Appendices B (especially the jumper diagram at the end of the appendix), D and E will be helpful in this verification. 3. ___ Install the HSP50215EVAL into one of the empty ISA slots on the host PC motherboard. Make sure that a good connection is made with the motherboard and that the connectors fit in the slots in the rear of the PC chassis properly. Record the oscillator frequency for future reference: ____ ____ ____Hz 4. ___ Re-install the PC chassis cover and power up the computer. The circuit board is ready for use.
Conguration/Test Headers
Fifteen dual row test headers located on the evaluation circuit board are used to monitor signals and set control pins. The pin assignments for each of these headers are found in Appendix D - Test Header Pin Assignments.
Requirements for the Control Software Program
In order to properly operate the HSP50215EVAL Control Software Program included in the evaluation kit, the PC must meet the following requirements: PC/XT/AT or 100% compatible with a minimum of 640K of RAM DOS Version 3.0 or higher. One parallel port with 25 pin connector.
Typical Evaluation Conguration
Figure 2 identies the conguration of a typical performance evaluation setup. A test PRBS data pattern is created via a stimulus le and used by a modulator to generate a modulated IF signal. Noise and other signal impairment stimulus les can be used with additional channels to create a cascaded/summed composite IF signal that is routed to a D/A converter (DAC), generating an output analog signal. The digitized IF signal is also routed out of the circuit board allowing multiple boards to be cascaded together. To check out a complete communication systems, the modulator output can be routed to a demodulator, whose baseband output is connected to a Bit Error Rate Tester (BERT) for measuring the Bit Error Rate (BER) performance.
Installing the Software
The instructions that follow will load both the HSP50215EVAL software onto the C drive of the computer. If you do not wish to run the software from the C drive, consult your computer users manual for operation from another drive. It is good practice to backup original disks prior to installing the software on your computer. 1. ___ Insert the HSP50215EVAL distribution disk in Drive A and copy the contents of the distribution diskette to the target directory on Drive C. Note: This must be done in such
a way as to retain the file structure of the distribution disk.
Getting Started
PERSONAL COMPUTER CHANNEL #1 STIMULUS FILE CHANNEL #1 FILTER FILE CHANNEL #1 STIMULUS FILE CHANNEL #1 FILTER FILE HSP50215EVAL EVALUATION BOARD
ANALOG IF OUTPUT
CHANNEL #4 STIMULUS FILE CHANNEL #4 FILTER FILE CONFIGURATION FILE
CHANNEL #4 STIMULUS FILE CHANNEL #4 FILTER FILE CONFIGURATION FILE
DIGITAL IF OUTPUT
FIGURE 2. TYPICAL MODULATOR PERFORMANCE EVALUATION CONFIGURATION
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2. ___ If a FIR filter design software tool is desired, then downloading SERINADE from the Harris Semiconductor website into the target directory is recommended. The web site is found at www.semi.harris.com and SERINADE is found under the Products column of the home page. Select Digital Signal Processing Products Listing menu item. Select the Development Tools menu item. Select the SERINADE menu item. Download of SERINADE can be done from this location. The software must be run from the new target directory established on the C drive. results. If all the items have passed the test, the board and software have been properly installed and you are ready to begin evaluation testing. Skip to step 12. If any test failed, proceed to step 9. 9. ___ If one of the tests shown on the screen for step 8 did not pass, then the board jumper configuration should be reviewed, as it is the most likely culprit.
+-------------------------------------+ | HSP50215 EVALUATION BOARD SOFTWARE | +------------------------------------+ BOARD INTERFACE MENU File Name ................ EXAMPLES\EX01QPSK (1) Interface ...................... ISA (2) ISA Base Address ............... 0x300 (3) (4) (5) (6) Channel Channel Channel Channel 1 2 3 4 FPGA FPGA FPGA FPGA Address Address Address Address ......... ......... ......... ......... 0 1 2 3
Verifying the Control Software and Board Installation
1. ___ On the PC, change the directory to the target directory where the control software has been installed. 2. ___ Start the program by typing: HSP50215 <Enter>. 3. ___ The MAIN MENU screen will appear. It will look like Figure 3.
+------------------------------------+ | HSP50215 EVALUATION BOARD SOFTWARE | +------------------------------------+ MAIN MENU (0) Board Configuration (1) Modulator Channel 1 Configuration (2) Modulator Channel 2 Configuration (3) Modulator Channel 3 Configuration (4) Modulator Channel 4 Configuration (5) Load Configuration File (6) Save Configuration File (7) Compute Registers (8) Configure Board (9) Test Menu (10) Exit ENTER SELECTION: = (C) Harris Semiconductor 1997 Version 1.0
(7) Oscillator Freq ........... 50000000 Hz (0) Main Menu ENTER SELECTION: (C) Harris Semiconductor 1997 Version 1.0
FIGURE 4. BOARD INTERFACE SUBMENU +------------------------------------+ | HSP50215 EVALUATION BOARD SOFTWARE | +------------------------------------+ TEST MENU File Name................... EXAMPLES\EX01QPSK (1) Reset Board (2) Write to Location While Reset (3) Read from Location While Reset (4) Write to Location While Running (5) Read from Location While Running (6) Test Board (0) Main Menu ENTER SELECTION: (C) Harris Semiconductor 1997 Version 1.0
FIGURE 3. MAIN MENU
4. ___ Select item (0) for board configuration and type <Enter>. The BOARD INTERFACE MENU will appear as shown in Figure 4. Use the menu items to change the default board configuration to match the evaluation board interface, printer, FPGA addressing and oscillator frequency that you desire. Verify that these settings match the jumper configuration of your evaluation board. 5. ___ When you have completed making your modifications, select item (0) and type <Enter> to return to the MAIN MENU. 6. ___ Select Main Menu item (9) and type <Enter> to enter the Test Menu. The Test Menu is shown in Figure 5. 7. ___ Select Test Menu Item (6) and type <Enter> to enter the Test Board submenu. 8. ___ A screen appears that indicates the RAM Address/Data Bus test results and the HSP50215 data bus test
FIGURE 5. TEST SUBMENU
10. ___ Next, the physical installation should be checked. 11. ___ If the board is properly installed, then a verify that no ISAbus card addressing contention exists. Steps 9, 10, AND 11 are the leading causes of board test failure.
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Running the Control Software for Evaluation Testing
12. ___ From the MAIN MENU, select the first MODULATOR CONFIGURATION MENU, item (1), by typing: 1<Enter>. The MODULATOR CHANNEL 1 CONFIGURATION MENU will appear. It should match the entry found in Figure 6. 13. ___ Make any adjustments to the parameters by entering the desired item number for parameter selection and editing each item via the respective parameter entry submenu. When editing is complete, select item (0) and type <Enter> to return to the MAIN MENU.
+------------------------------------+ | HSP50215 EVALUATION BOARD SOFTWARE | +------------------------------------+ File Name............. EXAMPLES\EXO1QPSK Channel 1 (1) Carrier Center Freq....... 5000000 Hz (2) Input Sample Rate......... 24300 Hz (3) Modulation Type........... QASK (4) Coef File.............. FILTERS\ISA135B (5) Interpolation (IP)........ 16 phase (6) Impulse Response Length (DS).16 samples (7) Stimulus File......... STIMULUS\QPSKPN (8) # Data Samples:........... 1022 (9) Output Attenuation........ +15dB (10) Output.................... Enabled (11) Cascade Input............. Enabled (12) Sync...................... Internal (13) Sync Polarity............. L -> H (14) FIFO Depth................ 3 (15) Output Format........... Offset Binary (16) Test Register............. 0 (0) Main Menu ENTER SELECTION: (C) Harris Semiconductor 1997 Version 1.0
17. ___ Select MAIN MENU item (8) by typing 8 <Enter>. The Board Interface Menu will appear as shown in Figure 7. 18. ___ If you have identified more than one channel for operation, selection of menu item (5) will load all the channels with one command. See step 25 for this action. In testing, there are times when most of the channels will remain the same and one channel or one channel input will change. Menu items (1) through (4) are for selective channel or channel input configuration. Select the menu item (1), CONFIGURE CHANNEL 1 MENU, of the BOARD INTERFACE MENU by typing 1<Enter>. A menu will appear with three execution options, as shown in Figure 8. This is the same menu that will appear when BOARD INTERFACE MENU items (2) through (5) are selected.
+------------------------------------+ | HSP50215 EVALUATION BOARD SOFTWARE | +------------------------------------+ BOARD INTERFACE MENU File Name................... EXAMPLES\EXO1QPSK (1) (2) (3) (4) (5) Configure Configure Configure Configure Configure Channel 1 Channel 2 Channel 3 Channel 4 All Channels
(0) Main Menu ENTER SELECTION: (C) Harris Semiconductor 1997 Version 1.0
FIGURE 7. BOARD INTERFACE SUBMENU
19. ___ Select the desired action from the three choices in
FIGURE 6. MODULATOR CHANNEL CONFIGURATION SUBMENU (1) Modulator (2) Pattern RAM (3) Both ENTER NEW VALUE [1]:
14. ___ Repeat Steps 12 and 13 for MAIN MENU items (2), (3), and (4). These submenus control Modulator Channels 2 through 4. These submenus are identical to those found under MAIN MENU (1) with the exception of the Channel Number and the names of the coefficient file, and stimulus file. 15. ___ Select MAIN MENU item (6) by typing 6 <Enter>. This will save the edited configuration file. You are prompted for a file name for your new configuration.
WARNING: Failure to change the .cfg file name may result in overwriting of an example file with an edited version of that file.
FIGURE 8. CONFIGURE CHANNEL 1 SUBMENU
16. ___ Select MAIN MENU item (7) by typing 7<Enter>. This will compute the configuration register values and generate the .1, .2, .3, and .4 files. (Filter and stimulus files with .imp file extensions must be created prior to running the HSP50215EVAL software - See Appendix G - Descriptive File List) Note that MAIN MENU items 1 through 7 can be executed without the evaluation circuit board installed.
the BOARD INTERFACE submenu. The MODULATOR item does an initialization of the designated channel and begins normal operation of that channel. The PATTERN RAM menu item allows individual STIMULUS files to be downloaded. Selecting item (3), allows both channel and stimulus configuration with one command. Selection of an item will return the user to the BOARD INTERFACE submenu. 20. ___ Items (2), (3), and (4) of the BOARD INTERFACE submenu, configure only channel 2, 3, and 4 on the board, respectively. Configure these channels and return to the main BOARD INTERFACE submenu.
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21. ___ Item (5) of the main BOARD INTERFACE submenu does a full initialization and configuration of all four channels on the board. Item (5) should be selected whenever the board has been reset. After that, items (2), (3) or (4) can be selected for a faster update. 22. ___ Select HARDWARE INTERFACE submenu item (0) by typing 0 <Enter>. This returns the user to the MAIN MENU. You have now configured your board for its first test configuration. You may look at the output with a scope or spectrum analyzer to verify that the board is operating as desired. 23. ___ If the output is not as expected, review the configuration of all of the channels to be sure that you have properly selected the stimulus, filtering and configuration. 24. ___ When designing a new configurations or new stimulus, it is best to begin by editing the example file that most closely matches the desired signal or configuration. with 3dB attenuation. The filter has a data span of 16 samples and 16 interpolation phases, and is referenced by the filter filename IS136B. Notice that it was setting item (8) to 1 that repeatedly sent a single bit to the modulator, creating the CW. Select main menu item (2) and set the following parameters: (1)250,000Hz (2)25,000Hz (3)QASK (7)Stimulus\bpskpn (See note below before entering this item)
Note: If you have not properly identied the stimulus le or the path to that le, then the program will not download when you command the software to congure the board, and will return you to the DOS prompt at which point you will need to restart the control software and start from scratch on the conguration.
(8)511 (9)48 (0)Returns to main menu This congures channel two to be a 25Kbps PSK modulator at 250kHz, but with the RF severely attenuated so as to be effectively turned off. The IS136B lter is used here, as well as in Channel 1. Select main menu item (3) and set the following parameters: (1)750,000Hz (2)75,000Hz (3)QASK (7)Stimulus\bpskpn (See note below before leaving this item).
Note: If you have not properly identied the stimulus le or the path to that le, then the program will not download when you command the software to congure the board, and will return you to the DOS prompt at which point you will need to restart the control software and start from scratch on the conguration.
Learning Your Way Around
This Section provides a step by step walk through of some exercises to familiarize the user with the software screens and the techniques used to generate a variety of stimulus and congurations of the HSP50215EVAL Board. If the DAC output is routed to a scope or a spectrum analyzer, then a visual verication can be made of the conguration changes. Note that these exercises assume that the concluding conguration of the previous exercise is the conguration of the board at the start of the next exercise. The rst exercise congures all channels to ensure success.
Exercise #1: Generating A CW Tone
This exercise will demonstrate the creation of a CW test tone. The purpose of this exercise is to illustrate the generation of a signal that is useful in a variety of testing congurations. Go to the main menu. Select Item (5), Load Conguration File, and enter the following le name and path: examples/ex01qpsk <Enter). Select Item (1), Modulator Channel 1 Conguration, and enter the following parameters: (1)500,000Hz (2)50,000Hz (3)QASK (7)Stimulus\bpskpn (See note below before leaving this item).
Note: If you have not properly identied the stimulus le or the path to that le, then the program will not download when you command the software to congure the board, and will return you to the DOS prompt at which point you will need to restart the control software and start from scratch on the conguration.
(8)511 (9)48 (0)Returns to main menu This congures channel three to be a 75Kbps PSK modulator at 750kHz, but with the RF severely attenuated so as to be effectively turned off. Once again, the IS136B lter is used. Select Item (4) and set the following parameters: (1)500,000Hz (2)501,000Hz (3)QASK (5)0 (6)4 (7)Stimulus\gn16k (See note below before leaving this item)
Note: If you have not properly identied the stimulus le or the path to that le, then the program will not download when you command the software to congure the board, and will return you to the DOS prompt at which point you will need to restart the control software and start from scratch on the conguration.
(8)1 (9)3 (0)Returns to main menu This configures channel one input stimulus to be a single bit, sampled at 50kHz, and applied to a 500kHz QASK modulator
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(8)16384 (9)48 (0)Returns to main menu This congures channel four to be a 351Kbps PSK modulator at 500kHz with a Gaussian White Noise input and with the RF severely attenuated so as to be effectively turned off. Select main menu item (6), save conguration le and enter the following le name and path: examples/exercise. Select main menu (7) to compute the register values. Select main menu (8) to congure the board. Select submenu item (5) to congure all channels. Select submenu item (3) to load both the modulator and Pattern RAM. When the submenu reappears, the download is complete and the scope or spectrum analyzer should show a single CW tone at 500kHz at approximately 0.4Vpp.
Exercise #3: Modulating the CW Tone with PN Data
This exercise will demonstrate the creation a BPSK signal using a Random PN sequence as a stimulus. The BPSK stimulus will write the following values as (I,Q) pairs into the modulator: (-0.707, -0.707), (+0.707, +0.707). This will generate a BPSK signal. The purist may wish to edit this le to have the values (+1,0), (-1,0), but the 45o phase offset is not of concern, in general. The purpose of this exercise is to demonstrate BPSK and provide insight into creating useful test stimulus les, as well as to learn techniques for quick test conguration. Go to the main menu. Select Item (1) and set the following parameters: (8)24 (9)3 (0)Returns to main menu This will return the output level to the original setting. Select main menu (7) to compute the register values. Select main menu (8) to congure the board. Select submenu item (1) to congure channel 1. Select submenu item (1) to load the modulator. When the submenu reappears, the download is complete and the scope or spectrum analyzer should show a ltered, modulated signal at an output level of approximately 0.4Vpp. There should be 10 IF cycles per baud and the baud rate is 50kHz. Notice that it was setting item (8) to 24 that sent a PN sequence to the modulator. The previous value of 1, held the modulator at CW using an input of either a (-0.707, -0.707) or (+0.707, +0.707). Note that if a particular data pattern is required, copying and editing the PN stimulus le for the number of data samples that you desire, is a quick way to perform an impulse response or some other useful test pattern such as 1/0 or 1000. Just remember to use the channel conguration menu to only select the number of data samples to match the entries that you have altered in the new le. Also, selecting a standard PN length (29-1, 215-1) allows a commercial Bit Error Rate Tester to be used in conjunction with this modulator in evaluation of the communication link. Notice also, that the various options for conguring the board are designed to save time during evaluation. If the only parameters that have changed involve one modulator, then the quickest conguration update downloads only the parameters for that modulator. The next quickest update is if the Pattern RAM and modulator for that single channel are all that need downloading. You will appreciate this as you apply the larger stimulus les, like the AWGN les. The longest download involves updating the modulator and Pattern RAM les for all channels.
Exercise #2: Adjusting the level of the CW Tone
This exercise will demonstrate the technique used in adjusting the output amplitude of the CW test tone via the Gain Control signal of the Digital Upconverter. This is but one technique that can be used to set the level, noting that scaling the input le can achieve the same result. The HSP50215 data sheet notes that care must be taken in setting the signal level at the input to the shaping lter, at the input to the interpolation lter, at the input to the mixer, and at the cascade summer. Attention to these points will eliminate the unwanted limiting or roll-over. The purpose of this exercise is to introduce the user to a technique for setting test signal levels. Go to the main menu. Select Item (1), Modulator Channel 1 Conguration, and enter the following parameters: (9)9 (0)Returns to main menu This will reduce the output level by 6dB. Select main menu (7) to compute the register values. Select main menu (8) to congure the board. Select submenu item (1) to congure channel 1. Select submenu item (1) to load the modulator. When the submenu reappears, the download is complete and the scope or spectrum analyzer should show a single CW tone at 500kHz at with half the amplitude of the signal in Exercise 1. Note that if we had set the value to 48, the channel is effectively turned off. Setting the value to 0 is the maximum output level, but there is the risk that clipping will occur when other signals are added into the CW tone.
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Exercise #4: CW and a Modulated Signal
This exercise simulates a CW jammer interferer with a signal of interest. The affect of interference is determined by how close in frequency the CW is to the desired signal and what the relative amplitude is to the signal of interest. We will use the pre-congured channel 1 as the modulated signal and congure channel 2 to be the interfering CW. The purpose of this exercise is to introduce the user to simple dual channel operation. Go to the main menu. Select Item (2) and set the following parameters: (8)1 (9)6 When the submenu reappears, the download is complete. (0)Returns to main menu This will set channel 2 to CW at 3dB lower than the modulated signal level and at half the frequency. Select main menu (7) to compute the register values. Select main menu (8) to congure the board. Select submenu item (2) to congure channel 2. Select submenu item (3) to load both the modulator and Pattern RAM. When the submenu reappears, the download is complete. This particular signal is easier seen on the spectrum analyzer than the scope. The CW is set at half the frequency of the modulated signal. By turning one of the signals on and off you can convince yourself that the desired combination of signals is present. The power of the four channel modulator should now be apparent. For signal testing, it is possible to generate the signal of interest, two adjacent signals, and an interferer signal. This test conguration is ideal for high signal to noise, multi-channel applications. The output is the composite of three CW tones related by harmonics and set at decreasing amplitude. The result is a cyclical output. Note that the relative start phase of each CW tone on each channel is determined by the relative time of the channel conguration load. For example, by reconguring individual channels (modulator only) you can change the relative phase of the CWs, changing the Fourier Series, resulting in a different shape output waveform. You may also nd it interesting to adjust the amplitudes to try and approximate a square wave. Adding the fourth modulator will improve the approximation, remembering that these exercises depend on the conguration returning to the last one called out, in order for the next exercise to work. (0)Returns to main menu Select Item (3) and set the following parameters: (8)1 (9)24 (0)Returns to main menu Select main menu (7) to compute the register values. Select main menu (8) to congure the board. Select submenu item (5) to congure all channels. Select submenu item (3) to load both the modulator and Pattern RAM.
Exercise #6: Generating Additive White Gaussian Noise (AWGN)
This exercise will demonstrate the use of the gn stimulus les. Noise will be considered alone, at rst, then a modulated signal will be added. The Gaussian Noise stimulus les were generated with MATLAB using the code commands: a = randn(8192,2); b = 0.25*[a(:,1)/std(a(:,1)),a(:,2)/std(a(:,2))]; This is a sequence of numbers that are randomly selected in the range of [-1 to +1], scaled by 0.25 for 4 limiting, normalized to set the standard deviation to exactly 0.25. This baseband signal is input at the sample rate and will be modulated to the IF set in parameter (1) of the modulator channel being used for noise generation. As a rule of thumb, set the AWGN sample rate to either a value that is at least 10 times the data sample rate, or at a value close to the IF BW, but make it a prime number not an even multiple of the data sample rate. The other parameter that determines the randomness of the noise is setting (8), the number of data samples. Two stimulus les have been created and the le name includes the number of samples. The pn16k le has 16K data samples and the pn8K has 8K data samples. Since the noise is averaged over the number of samples, once the number becomes relatively large, the differences is primarily
MATLAB is a registered trademark of The MathWorks, Inc.
Exercise #5: A Fourier Series Composite Signal
This exercise will demonstrate the use of 3 modulator channels congured as CW tones. The fundamental will be set at 12dB attenuation, the second harmonic at 18dB attenuation and the third harmonic at 24dB attenuation. The purpose is to introduce the operator to multiple channel congurations. Go to the main menu. Select Item (1) and set the following parameters: (8)1 (9)18 (0)Returns to main menu Select Item (2) and set the following parameters: (8)1 (9)12
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the amount of time you care to wait to load the le. A rule of thumb is to use as large a number as possible. Note that the start of the noise sequence is determined by when the stimulus le for that channel is loaded. If multiple channels are required to be started together, then the board should be set to use the internal synchronization logic to respond to a single external SYNCIN command. In noise applications, a random start on the various channels is often the desired condition. The purpose of this example is to demonstrate both using noise stimulus for lter shape evaluation and for establishing signal plus noise congurations. Go to the main menu. Select Item (1) and set the following parameters: (8)511 (9)48 (0)Returns to main menu Select Item (2) and set the following parameters: (8)511 (9)48 (0)Returns to main menu Select Item (3) and set the following parameters: (8)511 (9)48 (0)Returns to main menu Select Item (4) and set the following parameters: (1)500,000Hz (2)501,000Hz (3)QASK (4)Filters/bypass (8)16384 (9)3 (0)Returns to main menu Select main menu (7) to compute the register values. Select main menu (8) to congure the board. Select submenu item (5) to congure all channels. Select submenu item (3) to load both the modulator and Pattern RAM. When the submenu reappears, the download is complete. The output is a Gaussian Noise signal, sampled at 351kHz and modulated to 500kHz IF. On a spectrum analyzer the outline of the shaping lter is depicted. On the scope, a noisy signal that is 0.4Vpp is displayed. Now lets add back in a modulated signal. The length of the I/Q vector in the stimulus le is modied by the gain of the shaping lter and the gain of the programmable attenuator in the HSP50215. The standard deviation of the noise vector is likewise modied by the gains of the lter and the attenuator. After obtaining C/N, conversion to Eb/No is done by normalizing for the data rate, NBW of the noise lter, and the modulation type as follows: Eb/No=C/N-ModFactor-10LOG(symbol rate)+10LOG(NBW). where NBW is the double sided noise bandwidth of the noise lter. Go to the main menu. Select Item (1) and set the following parameters: (9)3 (0)Returns to main menu Select main menu (7) to compute the register values. Select main menu (8) to congure the board. Select submenu item (1) to congure channel 1. Select submenu item (1) to load the modulator. When the submenu reappears, the download is complete. The output is AWGN summed with modulated signal. The nal step is to determine how to set a particular Signal to Noise Ratio (SNR). In order to determine a C/N or Eb/No the following system information must be known: 1)The vector length of the I/Q data vector. (This is the magnitude of the input vector). 2)The standard deviation of the I and Q components of the noise pattern vector. 3)The DC gains of the data and noise lters. 4)The input sample rates for the data and noise modulators (it is assumed that the noise sample rate is higher than the data sample rate). 5) The noise bandwidth of the noise lters. 6) The multiplier settings for the gain in the modulators. Items 1 through 5 are listed in the headers of the le or in the control software menus. Item 6 can be obtained from the computed register values found in the .1, .2, .3 and .4 les.
Background on Eb/No and SNR Calculations
The signal to noise ratio (C/N) is equal to: C/NdB = 10LOG(A2/22) where is the standard deviation of the I and Q noise vectors (they are equal), and A is the average length of the I/Q vector.
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Adding the log of the noise bandwidth converts from C/N to C/No. Subtracting the log of the symbol rate converts from C/No to Es/No. The modulation factor converts from Es/No to Eb/No using the equation: MF = 10LOG[bits/symbol] This yields MF = 0dB for BPSK, MF = 3.01dB for QPSK, and MF = 4.77dB for 8 PSK.
Exercise #7: PRBS Data
This exercise will congure the board to bypass the lter and not upconvert, so that the user PRBS data is output. This conguration is useful for verifying stimulus les that are short data sequences. Go to the main menu. Select item (I) and set the following parameters: (9)48 (0)Returns to the main menu This turns channel 1 off. Select main menu, item (4) and set the following parameters: (1)0 (7)Stimulus/bpskpn (8)15 (9)3 (0)Returns to the main menu This sets the channel 4 stimulus le to be a 15 bit PRBS. The lter was already set to bypass. The IF is set to 0Hz. Select main menu item (7) to compute the register values. Select main menu item (8) to congure the board. Select submenu item (5) to congure all 4 channels. Select sumenu item (3) to load both the modulator and pattern RAM. When the submenu reappears, the download is complete. The output waveform should be the input PRBS data pattern. You should note that this configuration can be used to verify the maximum input rate by changing the input sample rate of channel 4 to be < fOSC/16. Varying the input sample rate will illustrate that with too high of an input sample rate, the filter does not have sufficient time to complete an output calculation, and no PRBS pattern is output. By lowering the input sample rate again, until the PRBS pattern reappears, the maximum input sample rate can be determined for your evaluation board/oscillator combination. that Note a similar process can be used to determine the maximum input rate of each of the example filter files, taking care to enter the proper DS and IP values for each filter as noted in Appendix G - Descriptive File List.
An Example Eb/No Calculation
Data File: QPSKPN, A = 1.0, FSAMP = 128ksym/sec Noise File: GN16K, std dev. = 0.25, FSAMP = 400ksamp/sec Data lter: IS136B, DC gain = 0.658, NBW = 1.004 x FSAMP Noise lter: RRC35A4xDC gain = 0.5, NBW = 0.989xFSAMP Signal Atten: 20 dB, 26 / 256 = 0.1016 Noise Atten: 14.6 dB, 48 / 256 = 0.1875 Begin by calculating C/NdB: C/NdB= 10LOG((1.0x0.658x0.1016)2/2(0.25x0.5x0.1875)2) = 10LOG((4.4693x103)/(1.0986x103)) = 6.094dB Continue by calculating Eb/No: Eb/No= 6.094-3.01-10LOG(128,000)+10LOG(0.989x400000) = 3.084 - 51.072 + 55.973 = 7.98dB Note that the values for A, standard deviation, DC gains, and noise bandwidths are found in the le headers of the example lter and stimulus les provided. When main menu item (7) is executed, four conguration les are generated, for the various channels. These les list the hex values for all of the control registers of the HSP50215. The channel (1, 2, 3, or 4) is indicated by the le sufx. The value of the multiplier for the attenuators is found in Register 17. This value, converted to decimal and divided by 256, yields the linear attenuation multiplier value. Note that there is an error introduced due to the 8-bit quantization of the gain control value. The error is small for attenuations close to 0dB but can be on the order of a tenth of a dB for attenuations greater than 15dB and as much as 1dB at the bottom of the range.
Generating User Congurations
Now that you understand the basics of controlling this modulator evaluation board, you should be able to edit the example conguration and stimulus les to obtain the test guration you desire. Remember that it is best to begin with the les that most closely match the desired conguration. Appendix G - Descriptive File List has a description of these les.
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The reader should reference the detailed schematics, found in Appendix E - Detailed Schematics, while reading the detailed circuit description. the digital upconverter for channel two. The gain control can be used to provide sufficient back off. The output of the digital upconverter for modulation channel 3, U2, is routed to the cascade input of modulation channel 2 (sheet 3 - U3).
Signal Path
Modulation Channel 4
Baseband in-phase and quadrature (I and Q) data enters the HSP50215EVAL via the host computer ISA interface (sheet 6), and is routed to an ACTEL FPGA (U6 - U9) on one of the four upconverter channels (sheets 1-4). Data enters the HSP50215 Digital UpConverter (U1, U2, U3, or U4) from the associated ACTEL FPGA via busses C(15:0) and DUA(9:0), and the WR control line. The Digital Upconverter provides the primary DSP processing for each channel. The control software allows Modulation Channel 4 selection of the modulation type (QASK, bandlimited FM and shaped FM), Resampler frequency, IF frequency, gain control, as well as shaping and interpolation filter configuration. The output of the digital upconverter for modulation channel 4, U1, is routed to the cascade input of modulation channel 3 (sheet 2 - U2). Modulation Channel 4 also allows for external digital cascade input, via connector J1. This input can be used for cascading several evaluation boards together, or for inclusion of any digitized IF signal, with the digital IF output of the modulation channel 4 upconverter, U1. The sync and clock signals are supplied to the connector from the clock and sync selection circuitry found on sheet 4 of the schematic. JP1 and RZ1 provide control and selection for the channel 4 ACTEL FPGA and associated Digital UpConverter. U13 and 14 provide the memory storage for data being processed by the ACTEL FPGA. Four modulation channels are provided, so that HSP50215 evaluation can include processing a signal of interest in the presence of two adjacent channel signals and an interferer signal.
Modulation Channel 2
Sheet 3 of the schematic details the control and access circuitry for Modulation Channel 2. U3 is the Digital upconverter and U8 is the associated ACTEL FPGA. The control software allows Modulation channel 2 selection of the modulation type (QASK, bandlimited FM and shaped FM), Resampler frequency, IF frequency, gain control, as well as shaping and interpolation lter conguration. JP3 and RZ3 provide control and selection for the channel 2 ACTEL FPGA and associated Digital UpConverter. U17 and 18 provide the memory storage for data being processed by the ACTEL FPGA. Care must be taken to ensure that the cascade input summed with the modulation output of channels 4 and 3 do not limit inside the digital upconverter for channel 2. The Gain control can be used to provide sufcient back off. The output of the digital upconverter for modulation channel 2, U3, is routed to the cascade input of modulation channel 1 (sheet 4 - U4).
Modulation Channel 1
Sheet 4 of the schematic details the control and access circuitry for modulation channel 1. U4 is the Digital upconverter and U9 is the associated ACTEL FPGA. The control software allows Modulation Channel 1 selection of the modulation type (QASK, bandlimited FM and shaped FM), Resampler frequency, IF frequency, gain control, as well as shaping and interpolation lter conguration. JP4 and RZ6 provide control and selection for the channel 1 ACTEL FPGA and associated Digital Upconverter. U19 and 20 provide the memory storage for data being processed by the ACTEL FPGA. Care must be taken to ensure that the cascade input summed with the modulation output of channels 4 through 2 do not limit inside the digital upconverter for channel 1. The Gain control can be used to provide sufcient back off. The output of the digital upconverter for modulation channel 1, U4, is routed to an output connector, J2, and to an DAC, U5, found on sheet 5. J2 is the digital output that is the cascaded IF outputs of channels 4 through 1. The DAC output is routed to J5 and provides 50 output at 0.5Vpp. Modulation Channel 1 also has an input connector, J3, which allows for direct control of one HSP50215 modulation channel on the HSP50215EVAL. Input Connector J4 provides access to the control bus of the ACTEL FPGA for channel four. All other channels are expected to be not used, to prevent bus contention during the control of the channel 1 upconverter, via the channel 1 ACTEL FPGA.
Modulation Channel 3
Sheet 2 of the schematic details the control and access circuitry for modulation channel 3. U2 is the Digital upconverter and U7 is the associated ACTEL FPGA.The control software allows Modulation Channel 2 selection of the modulation type (QASK, bandlimited FM and shaped FM), Resampler frequency, IF frequency, gain control, as well as shaping and interpolation lter conguration. JP2 and RZ2 provide control and selection for the channel 3 ACTEL FPGA and associated Digital UpConverter. U15 and 16 provide the memory storage for data being processed by the ACTEL FPGA. Care must be taken to ensure that the cascade input summed with the modulation output of channel two do not limit inside
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ACTEL is a registered trademark of Actel Corporation.
HSP50215EVAL PC/Controller Interface Section
ISA Interface
The normal installation conguration of the HSP50215EVAL Card is in a PC, using a standard ISA slot. J10 on sheet 6 of the schematic details the card connector interface to the computer ISA bus. JP6 is used to set the card address location in the PC. The default card address shown on the schematic is 110000, and should be used unless that address has already been allocated in your PC conguration. U21 and RZ7 perform the card decode from the ISA interface and combine with U22 and U23 to generate the Read, Write and Address handling necessary for proper ISA interaction with the HSP50215EVAL. Jumper JP9 allows for ISA control interface or an 8-bit parallel port interface via connector J9. Set the jumper conguration as shown in the schematic for ISA interface operation. U24 provides the ISA bus interface to the HSP50215EVAL 8-bit bus interface which downloads control data to the ACTEL FPGAs on each of the four modulator channels. Jumper JP5 sets the source for the sync signal. Installing jumpers J5 7-8 and 9-10 route the SYNCOUT from Channel 1 to the CASSYNC2 location on J1 and to the SYNCIN of U1-4. Installing JP5 5-6 routes this sync signal to the output connector. JP5 also allows jumpering of additional digital IF output resolution to the output connector, J2. Installing JP5 1-2 and 34 provides 2 bits of additional resolution on the output connector.
Power Supply Connections
The +5V and -12V are supplied via the ISA interface when the card is installed in a PC. When the card is used outside the PC, +5V is input via J8 and -12V is input via J7. The +5V can be supplied from any generic +5VDC/2A AC/DC power adapter. The evaluation board draws approximately 1.5A at 52MHz on the 5VDC input. The -12V is supplied from the ISA connector, J10 and is regulated to -5V with U12, shown on sheet 5 of the schematic. If the ISA bus interface is used, then jumper J11 must be installed. If an external -5VDC supply is used, then jumper J11 must not be installed. Any generic 5VDC/200mA AC/DC power adapter can be used for the J7 VEE input. The evaluation board draws approximately 100mA at 52MHz on the -5VDC input.
Parallel Interface Conguration
To congure the HSP50215EVAL to operate from a parallel port interface, remove jumpers JP6 17-18, and remove jumpers 1-2 and 5-6 from JP9. Install jumpers 3-4 and 7-8 on JP9. (Connects the external data bus, write signal and the address signals to the appropriate labelled pins on the J9 connector). Depending on the length of the cable connected to J9, installation of R13 and 14 as well as C3 and 4 may be desirable to improve the signal quality of the WR and address signals.
Advanced Evaluation Congurations
Non ISA (PC installed) Operation
The HSP50215EVAL can be operated external to a PC for laboratory applications with other evaluation boards. The ISA interface is disabled by configuring jumpers on the board. Remove jumpers JP9 1-2 and 5-6. Install jumpers JP9 3-4 and 7-8. Remove jumper JP6 17-18 and 19-20. Remove jumper JP-11 and provide external power supply voltages -5.0VDC at J7 and +5.0VDC at J8. The gure at the end of Appendix B - Initial Jumper Settings is a visual reference jumper conguration for this conguration. The control processor must then be connected to the parallel interface on J9. PDC(7-0) is the data bus, PARWR is the Write signal and PARA is the Address signal. The installation of R13 and R14 as well as C3 and C4 may help reduce signal distortion for long cable interfaces. Once the parallel port connection is made, and the jumpers set, the board is ready for operation and control from the parallel interface rather than the ISAbus interface. As in the ISAbus conguration stimulus, and lter les are used to operate the board.
Clocking
Jumpered Options
Sheet 4 of the schematic contains the jumpers for several clocking configurations. JP8 determines the source for the CONNINCLK, MASTERCLK, and DACCLK clock drivers, U11, on the board. When JP8 1-2 and 3-4 are installed, then the clock source will be either an external source or the on-board crystal oscillator and the connector clock is driven by the card. These jumpers also route the clock to the output connector, J2. When JP8-2-3 is installed, the output connector is the source of the clock. The configuration shown on the schematic is for internal crystal clock source. JP7 determines if the clock source is external or internal. The default conguration shown in the schematic is for operation from the internal crystal clock source, U10. Termination of the external clock with 50 is done by installing the JP10 jumper.
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HSP50215EVAL
Direct Modulator Control
The HSP50215EVAL Board provides a conguration that allows a user direct access to the HSP50215 control busses as well as to the ACTEL FPGA bus interface. This mode is intended for single channel only operation, as bus contention will result if other channels are attempted to be controlled via the parallel or ISA bus while the local control is active. Modulation channel 1 is the channel that has connectors for the local control of the DUC and ACTEL. J4 provides the HSP50215 interface and J3 provides the ACTEL interface. The user must design a cable to match the appropriate data and control signals for these parts, if local control is to be effective. Disable the ACTEL by removing JP4 9-10 J2
Appendix A - Circuit Board Layout
U10
JP11
Using SERINADE Designed Filters
SERINADE, a lter design tool can be used to synthesize a lter for the HSP50215 shaping lters. This procedure assumes that the SERINADE .imp les are available for import. Version 1.1 or higher is recommended. File format is consistent with a SERINADE .imp le or SIGLAB le.
U4
U9
JP6 JP9
JP5
JP4
J3
JP3
U3
U1
JP2
U2
JP1
J1
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SERINADE is a trademark of Harris Corporation. SIGLAB a trademark of The Athena Group, Inc.
U6
U7
U8
J4
JP8
JP10 JP7
J6
HSP50215EVAL Appendix B - Initial Jumper Settings
INITIAL JUMPER SETTINGS LOCATION J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 SETTING 3-4 5-6 7-8 9-10 11-12 13-14 15-16 17-18 23-24 25-26 27-28 29-30 31-32 33-34 35-36 37-38 INITIAL JUMPER SETTINGS (CONTINUED) LOCATION JP4 JP4 JP4 SETTING 9-10 11-12 13-14
The JP4 jumpers set the control signals, such as chip enables, output enables, and chip select controls for the ACTEL and HSP50215 for Channel 1 JP5 JP5 JP5 JP5 1-2 3-4 7-8 9-10
The JP5 jumpers set the SYNC controls, bringing SYNCOUT to the output connector and routing the SYNCOUT of channel 1 HSP50215 to the SYNCIN on all channels (HSP50215s) on the board. The remaining jumpers add additional output signal resolution to the output connector, J2. JP6 JP6 JP6 JP6 JP6 JP6 9-10 11-12 13-14 15-16 17-18 19-20
The J1 jumpers are installed to terminate the Channel 4 cascade input, which is unused in the standard conguration JP1 JP1 JP1 JP1 5-6 9-10 11-12 13-14
The JP6 jumpers set the card address to 110000 and connecting the card decode to the board circuitry. JP7 2-3
The JP1 jumpers set the control signals, such as chip enables, output enables, and chip select controls for the ACTEL and HSP50215 for Channel 4 JP2 JP2 JP2 JP2 JP2 1-2 5-6 9-10 11-12 13-14
JP7 sets the clocking conguration to be from the on board crystal oscillator. JP8 JP8 1-2 3-4
The JP8 jumpers connect the selected clock to the on board clock drivers and connect one driver output to the output connector, J2. JP9 JP9 1-2 5-6
The JP2 jumpers set the control signals, such as chip enables, output enables, and chip select controls for the ACTEL and HSP50215 for Channel 3 JP3 JP3 JP3 JP3 JP3 3-4 5-6 9-10 11-12 13-14
The JP9 jumpers set the control to be from the ISAbus rather than from the parallel port interface JP10 1-2
The JP10 jumper terminates an external clock input in 50. While this jumper is set, no external clock is used in the standard conguration (see jumper JP7) JP11 1-2
The JP3 jumpers set the control signals, such as chip enables, output enables, and chip select controls for the ACTEL and HSP50215 for Channel 2 JP4 JP4 JP4 1-2 3-4 5-6
The JP11 jumper connects the 12V from the ISAbus interface, which is regulated down to the -5V required for the -VEE onboard, to the board -VEE runs.
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HSP50215EVAL
Evaluation Board Layout Showing Jumper Conguration for ISAbus Conguration. Evaluation Board Layout Showing Jumper Conguration for Parallel Bus Conguration.
JP11
U10
JP6 JP9
U10
JP11
J2
U9
J2
U4
J4
U4
U9
JP6 JP9
JP5
JP5
JP4
JP4
J3
U8
J3
U3
JP3
U2
U7
JP3
U3
JP2
U1
U6
U1
JP2
U2
JP1
J1
JP1
J1
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U6
U7
U8
J4
JP8
JP10 JP7
JP8
JP10 JP7
J6
J6
HSP50215EVAL Appendix C - Connector Pin Assignments
J1 CONNECTOR PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SIGNAL N/C GND CAS15 GND CAS14 GND CAS13 GND CAS12 GND CAS11 GND CAS10 GND CAS9 GND CAS8 GND CONNINCLK GND PIN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SIGNAL NC GND CAS7 GND CAS6 GND CAS5 GND CAS4 GND CAS3 GND CAS2 GND CAS1 GND CAS0 GND CASSYNC2 GND PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J3 CONNECTOR PIN ASSIGNMENTS SIGNAL GND A3_0 FIFOTP_4 CEPULLUP_4 SYMBLCLK_4 WR215_4 OE215_4 RESET4 GND DU4A9 DU4A8 DU4A7 DU4A6 DU4A5 DU4A4 DU4A3 DU4A2 DU4A1 DU4A0 GND PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SIGNAL GND OERAM4 C4_15 C4_14 C4_13 C4_12 C4_11 C4_10 GND C4_9 C4_8 C4_7 C4_6 C4_5 C4_4 C4_3 C4_2 C4_1 C4_0 GND
J2 CONNECTOR PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SIGNAL N/C GND OUT4_15 GND OUT4_14 GND OUT4_13 GND OUT4_12 GND OUT4_11 GND OUT4_10 GND OUT4_9 GND OUT4_8 GND MASTERCLK GND PIN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SIGNAL NC GND OUT4_7 GND OUT4_6 GND OUT4_5 GND OUT4_4 GND OUT4_3 GND OUT4_2 GND OUT4_1 GND OUT4_0 GND OPCASSYNC GND
J4 CONNECTOR PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SIGNAL GND A4_16 A4_15 A4_14 A4_13 A4_12 A4_11 A4_10 GND A4_9 A4_8 A4_7 A4_6 A4_5 A4_4 A4_3 A4_2 A4_1 A4_0 GND
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HSP50215EVAL
J5 CONNECTOR PIN ASSIGNMENTS PIN 1 2 SIGNAL ANALOG IF GND J6 CONNECTOR PIN ASSIGNMENTS PIN 1 2 SIGNAL SMACLK GND J7 CONNECTOR PIN ASSIGNMENTS PIN 1 2 SIGNAL -5VEE GND J8 CONNECTOR PIN ASSIGNMENTS PIN 1 2 SIGNAL SVCC GND J9 CONNECTOR PIN ASSIGNMENTS 18 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 SIGNAL N/C PCD0 PCD1 PCD2 PCD3 PCD4 PCD5 PCD6 PCD7 NC STAT N/C N/C PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 SIGNAL 19 N/C 20 N/C 21 PARWR 22 PARA 23 GND 24 GND 25 GND 26 GND 27 GND 28 GND 29 GND 30 GND 31 GND A0 62 GND A1 61 14.3MHz A2 60 +5V A3 59 ALE A4 58 TC A5 57 -DACK2 A6 56 IRQ3 A7 55 IRQ4 A8 54 IRQ5 A9 53 IRQ6 A10 52 IRQ7 A11 51 SYSCLK A12 50 -REFSH A13 49 DREQ1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 J10 CONNECTOR PIN ASSIGNMENTS SIGNAL -IOCHK D7 D6 D5 D4 D3 D2 D1 D0 IOCHRDY AEN A19 A18 A17 A16 A15 A14 PIN 32 33 34 35 36 37 38 39 40 41 42 43 55 45 46 47 48 SIGNAL GND RESDRV +5V IRQ9 -5V DREQ2 -12V -0WS +12V GND -SMEMW -SMEMR -IOW -IOR -DACK3 DREQ3 -DACK1
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HSP50215EVAL Appendix D - Test Header Pin Assignments
JP1 TEST HEADER PIN ASSIGNMENTS PIN 1 3 5 7 9 11 13 15 SIGNAL GND GND GND GND GND GND GND GND Ground Ground Ground Ground Ground Ground Ground Ground DESCRIPTION PIN 2 4 6 8 10 12 14 16 SIGNAL CSEL0_1 CSEL1_1 CSEL2_1 Unused ACTELEN_1 OEPULLUP_1 CEPULLUP_1 FIFOTP_1 CSEL0_1 CSEL1_1 CSEL2_1 Unused ACTEL ENABLE FOR U6 OUTPUT ENABLE PULLUP U1 CHIP ENABLE U1 PULLUP_1 FIFO TEST POINT U1 DESCRIPTION
JP2 TEST HEADER PIN ASSIGNMENTS PIN 1 3 5 7 9 11 13 15 SIGNAL GND GND GND GND GND GND GND GND Ground Ground Ground Ground Ground Ground Ground Ground DESCRIPTION PIN 2 4 6 8 10 12 14 16 SIGNAL CSEL0_2 CSEL1_2 CSEL2_2 Unused ACTELEN_2 OEPULLUP_2 CEPULLUP_2 FIFOTP_2 CSEL0_2 CSEL1_2 CSEL2_2 Unused ACTEL ENABLE FOR U7 OUTPUT ENABLE PULLUP U2 CHIP ENABLE U2 PULLUP_1 FIFO TEST POINT U2 DESCRIPTION
JP3 TEST HEADER PIN ASSIGNMENTS PIN 1 3 5 7 9 11 13 15 SIGNAL GND GND GND GND GND GND GND GND Ground Ground Ground Ground Ground Ground Ground Ground DESCRIPTION PIN 2 4 6 8 10 12 14 16 SIGNAL CSEL0_3 CSEL1_3 CSEL2_3 Unused ACTELEN_3 OEPULLUP_3 CEPULLUP_3 FIFOTP_3 CSEL0_3 CSEL1_3 CSEL2_3 Unused ACTEL ENABLE FOR U8 OUTPUT ENABLE PULLUP U3 CHIP ENABLE U3 PULLUP_1 FIFO TEST POINT U3 DESCRIPTION
JP4 TEST HEADER PIN ASSIGNMENTS PIN 1 3 5 7 9 11 13 15 SIGNAL GND GND GND GND GND GND GND GND Ground Ground Ground Ground Ground Ground Ground Ground DESCRIPTION PIN 2 4 6 8 10 12 14 16 SIGNAL CSEL0_4 CSEL1_4 CSEL2_4 Unused ACTELEN_4 OEPULLUP_4 CEPULLUP_4 FIFOTP_4 CSEL0_4 CSEL1_4 CSEL2_4 Unused ACTEL ENABLE FOR U9 OUTPUT ENABLE PULLUP U4 CHIP ENABLE U4 PULLUP_1 FIFO TEST POINT U4 DESCRIPTION
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HSP50215EVAL
JP5 TEST HEADER PIN ASSIGNMENTS PIN 1 3 5 SIGNAL OUT4_1 OUT4_0 CASSYNC DESCRIPTION 2ND TO LSB OF OUTPUT OF CHANNEL 1 OUTPUT LSB OF OUTPUT OF CHANNEL Q OUTPUT OFF BOARD (J1) SYNC DRIVER INPUT AND SYNCIN/SYNCOUT JUMPER POINTS HSP50215 SYNCIN INPUT FOR CHANNELS 1, 2, 3, AND 4 SYNCOUT OUTPUT FROM CHANNEL 1 HSP50215 AS SOURCE FOR SYNC SIGNAL PIN 2 4 6 SIGNAL OPOUT1 OPOUT0 OPCASSYNC DESCRIPTION OUTPUT LSB+1 OUTPUT LSB CASCADE SYNC OUTPUT ON OUTPUT CONNECTOR J2 OFF BOARD (J1) SYNC DRIVER INPUT AND SYNCIN/SYNCOUT JUMPER POINTS OFF BOARD (J1) SYNC DRIVER INPUT AND SYNCIN/SYNCOUT JUMPER POINTS
7
SYNCIN
8
U11-11 AND JP5-8, 10 U11-2, 4, 6, 8
9
SYNCOUT
10
JP6 TEST HEADER PIN ASSIGNMENTS PIN 1 3 5 7 9 11 13 15 17 19 SIGNAL GND GND GND GND GND GND GND GND GND GND DESCRIPTION CHIPSELECT UNUSED PULLUP AND ISA CARD ADDRESS DECODE BIT 9 (MSB) PULLUP AND ISA CARD ADDRESS DECODE BIT 8 PULLUP AND ISA CARD ADDRESS DECODE BIT 7 PULLUP AND ISA CARD ADDRESS DECODE BIT 6 PULLUP AND ISA CARD ADDRESSDECODE BIT 5 PULLUP AND ISA CARD ADDRESS DECODE BIT 4 PULLUP AND ISA CARD ADDRESS DECODE ENABLE BIT ISA CARD DECODE PIN 2 4 6 8 10 12 14 16 18 20 SIGNAL GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND U23- 4, 5, 9 AND 12 DESCRIPTION CHIPSELECT HARDWIRE ZERO UNUSED CARD ADDRESS HARDWIRE ZERO CARD ADDRESS HARDWIRE ZERO CARD ADDRESS HARDWIRE ZERO CARD ADDRESS HARDWIRE ZERO CARD ADDRESS HARDWIRE ZERO CARD ADDRESS HARDWIRE ZERO CARD ADDRESS HARDWIRE ZERO ENABLE FOR ISABUS READ, WRITE AND DATA BUS
JP7 TEST HEADER PIN ASSIGNMENTS PIN 1 2 3 SIGNAL SMACLK OSCLCK CRYSTALCLK DESCRIPTION J3 SMA CLOCK INPUT CLOCK SELECTION, OUTPUT CRYSTAL CLOCK OUTPUT PIN 1 2 3 4
JP8 TEST HEADER PIN ASSIGNMENTS SIGNAL OSCLCK DU3A9 J2-17 MASTERCLK DESCRIPTION SELECTED CLOCK SOURCE CLOCK DRIVER INPUT OUTPUT CONNECTOR PIN 17 MASTER CLOCK OUTPUT
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HSP50215EVAL
JP9 TEST HEADER PIN ASSIGNMENTS PIN 1 3 5 7 SIGNAL GND PARA LIOW PARWR DESCRIPTION ISA INPUT ADDRESS PARALLEL INPUT ADDRESS ISA INPUT WRITE PARALLEL INPUT WRITE PIN 2 4 6 8 A A WR WR SIGNAL DESCRIPTION ADDRESS ADDRESS WRITE WRITE
JP10 TEST HEADER PIN ASSIGNMENTS PIN 1 2 SIGNAL SMACLK 50 - GND DESCRIPTION J3 SMA CLOCK INPUT TERMINATION RESISTOR
JP11 TEST HEADER PIN ASSIGNMENTS PIN 1 SIGNAL REGULATED -5.2V DESCRIPTION REGULATED -5.2V SOURCED FROM ISA BUS INTERFACE PIN 2 SIGNAL CARD -VEE -VEE DESCRIPTION
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Appendix E - Detailed Schematics
3-464
HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
3-465
HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
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HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
3-467
HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
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HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
3-469
HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
3-470
HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
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HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
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HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
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HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
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HSP50215EVAL
Appendix E - Detailed Schematics (Continued)
3-475
HSP50215EVAL
HSP50215EVAL Appendix F - Parts List
HARRIS SEMICONDUCTOR LINE ITEM
1 2 3 4
HSP50215EVAL REV B
REV. B 3/23/98 MANUFACTURERS PART #
HSP50215VC IDT71024S15TY A1225XL-PL84C
QTY PER PCB
4 8 4 4
REFERENCE DESIGNATOR
U1-U4 U13 - U20 U6 - U9 REF U6-U9
DESCRIPTION
DIGITAL UPCONVERTER 1 MBIT STATIC RAM FPGA Label to read on FPGA: HSP50215 FPGA REV A 14-BIT D/A HEADER 2 x 8 HEADER 2 x 13, SHROUDED HEADER 2 x 10 HEADER 2 x 4 HEADER 1 x 2 HEADER 1 x 3 HEADER 1 x 4 HEADER 1 x 20 HEADER 2 x 5 HEADER 2 X 20 22K RPACK TO PIN SM SIP 14 PIN SOCKET XTAL OSC 50MHz IC IC IC IC VOLT, REGULATOR -5.2V CAPACITOR, SM 0.1F CAPACITOR, 10F CAPACITOR, SM, 0.01F RESISTOR, SM, 62 RESISTOR, SM 910 RESISTOR, SM 20 RESISTOR, SM 50 ANGLE PCB MOUNT SHORTING JUMPERS
PKG
100 MQFP 32 SOJ 84 PLCC
MANUFACTURER
HARRIS IDT ACTEL
5 6 6A 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
1 3 1 2 1 2 1 1 1 1 3 10 1 1 1 1 1 2 1 1 8 58 2 1 6 2 2 50 2 2 15 1 1
U5 JP1 - JP3 J9 JP4, 6 JP9 JP10, 11 JP7 JP8 J4 JP5 J1, J2, J3 RZ - RZ10 XU10 U10 U21 U23 U24 U11, U22 U12 C6 C5, 61 - 66, 69 C1, 2, 7-60, 67, 68 R6, 7 R8 R1 - 5, 11 RA1, R31 J5, 6
28 SOIC 2x8 2 x 13 2 x 10 2x4 1x2 1x3 1x4 1 x 20 2x5 2 x 20 10 PIN SIP SOCKET 14 DIP 20 SOIC 14 SOIC 20 SOIC 20 SOIC TO220 1210 RADIAL 1206 1210 1210 1210 1210
HARRIS QPL/SULLINS CIRCUIT ASSEMBLY CORP QPL/SULLINS QPL/SULLINS QPL/SULLINS QPL/SULLINS QPL/SULLINS QPL/SULLINS QPL/SULLINS QPL/SULLINS PANASONIC QPL/AUGAT QPL/CTS NATIONAL HARRIS HARRIS HARRIS NATIONAL SEMI QPL/PANASONIC QPL/MALLORY QPL/PANASONIC QPL/PANASONIC QPL/PANASONIC QPL/PANASONIC QPL/PANASONIC AMPHONEL/DIGIKEY QPL/SULLINS QPL/LZR QPL/LZR
HI5741BIB PTC8DAAN CA-28HL-1C PTC10DAAN PTC4DAAN PTC2SAAN PTC35SAAN PTC4SAAN PTC20SAAN PTC5DAAN PTC20DAAN EXB-H110223J 814-AG11D MX-45T-50,000 74ACT520SC 74ACT32M 74ACT245M 74ACT244M LM29905-5.2 ECH-U1C104JB5 TDC106M025NSF ECH-U1C103JB5 ERJ-14YJ62 ERJ-14YJ910 ERJ-14YJ20 ERJ-14YJ50 ARF1232-ND STC02SYAN RL30B DC10B ERJ-8GEYJ200 M1AXA-2636R-ND 8225-6000
J7, 8
DJ0058 POWER PLUG CABLE, DC10B
R15-28, 30
RESISTOR, SM, 200 RIBBON CABLE W/CONN CONNECTOR, 25D, IDC
1206
QPL/PANASONIC DIGLKEY QPL/3M
C3, C4, C100, R9, R10, R12 - 14, R29, R100 1 1 1 TBD TBD TBD
OPTIONAL PARTS FOR PARALLEL CONTROL BOLT WASHER NUT PWB DISKETTE MANUAL STATIC BAG BOX
38 39
41 42 43 40 44
1 1 1 1 1
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HSP50215EVAL Appendix G - Descriptive File List
PC PROGRAM FILE HSP50215.EXE DESCRIPTION HSP50215EVAL CONTROL SOFTWARE PROGRAM
File Name: EX02GMSK
Description: This is an example of GMSK using the FM with pre-lter. The BT product is 0.3 (GSM). The input sample rate is 270.833kHz. The data is a 511 sample PN. The PN codes for channels 2 and 4 are pre-coded to give the proper data when demodulated as OQPSK at 135.417 kbaud. When using this conguration with bursts for GSM, it does not support guard times of less than full data bit periods due to that input sample rate. To generate guard times with quarter bit resolution, the input sample rate must be increased to 4x270833. The channel spacing is 800kHz with one unoccupied channel. With the supplied 50MHz oscillator, the maximum input sample rate supported by this conguration is 625,000Hz.
EX02GMSK EXAMPLE CONFIGURATION FILE Channel 1 Filter file: IP / DS: Center Frequency: Input Sample Rate: Stimulus File: GS5T16X 16 / 5 3200000 Channel 2 GS5T16X 16 / 5 4000000 Channel 3 GS5T16X 16 / 5 4800000 Channel 4 GS5T16X 16 / 5 6400000
MISCELLANEOUS FILE EXxxname.CFG DESCRIPTION EXAMPLE CONFIGURATION FILES REFERENCE EXAMPLE FILTER FILES REFERENCE EXAMPLE STIMULUS FILES
filename.IMP filename.IMP
Example Conguration Files
The example conguration les are located in the EXAMPLES subdirectory. Load the desired example conguration le using menu item 5 in the main menu. The naming convention for the example conguration les is:.
EX
xx
NAME
FILE NAME
270833.333 270833.333 270833.333 270833.333
EXAMPLE NUMBER
GMSKPN
EXAMPLE CONFIGURATION FILE
GMSKPNPC
GMSKPN
GMSKPNPC
File Name: EX03QPSK File Name: EX01QPSK
Description: This example illustrates high dynamic range QPSK modulation. It is similar to IS136, but with a continuous 511 sample long PN sequence and QPSK modulation instead of Pi/4DQPSK modulated in bursts. The lter is a square root of raised cosine with a = 0.35. The channel spacing is 120kHz with one unoccupied channel. With the supplied 50MHz oscillator, the maximum input sample rate supported by this conguration is 195,312.5Hz.
EX01QPSK EXAMPLE CONFIGURATION FILE Channel 1 Filter file: IP / DS: Center Frequency: Input Sample Rate: Stimulus File: IS136B 16 / 16 4000000 24300 Channel 2 IS136B 16 / 16 4120000 24300 Channel 3 IS136B 16 / 16 4240000 24300 Channel 4 IS136B 16 / 16 4480000 24300
Description: This is a lower dynamic range QPSK example. This lter is a slightly modied version of the IS95 coefcient set. The stimulus is a 511 PN sequence on I and Q. The channel spacing is 1.25 times the symbol rate. With the supplied 50MHz oscillator, the maximum input sample rate supported by this conguration is 1.041667MHz.
EX03QPSK EXAMPLE CONFIGURATION FILE Channel 1 Filter file: IP / DS: Center Frequency: Input Sample Rate: Stimulus File: IS95MOD 4 / 12 4000000 614400 Channel 2 IS95MOD 4 / 12 4768000 614400 Channel 3 IS95MOD 4 / 12 5536000 614400 Channel 4 IS95MOD 4 / 12 6304000 614400
QPSKPN
QPSKPN
QPSKPN
QPSKPN
QPSKPN
QPSKPN
QPSKPN
QPSKPN
3-477
HSP50215EVAL
File Name: EX04QAM
Description: This le demonstrates 16QAM modulation. The lter is a square root of raised cosine response (a = 0.2). The stimulus le is 511 PN codes on each data bit. The channel spacing is 1.5 times the symbol rate. With the supplied 50MHz oscillator, the maximum input sample rate supported by this conguration is 1.041667MHz.
EX04QAM EXAMPLE CONFIGURATION FILE Channel 1 Filter file: IP / DS: Center Frequency: Input Sample Rate: Stimulus File: RRC2A4X 4 / 12 4000000 512000 Channel 2 RRC2A4X 4 / 12 4768000 512000 Channel 3 RRC2A4X 4 / 12 5536000 512000 Channel 4 RRC2A4X 4 / 12 6304000 512000 Filter file: IP / DS: Center Frequency: Input Sample Rate: Stimulus File:
File Name: EX06QPSK
Description: This example is similar to EX01QPSK, but used for cochannel and adjacent channel testing. The desired signal is in channel 2. Channels 1 and 3 are at 1.4 times the symbol rate offsets and +10dB higher than the desired signal. Channel 4 is in the same channel as the desired signal and 10dB lower. The data rates are offset slightly to randomize the phasing of the channels.
EX06QPSK EXAMPLE CONFIGURATION FILE Channel 1 IS136B 16 / 16 4000000 24300.2 Channel 2 IS136B 16 / 16 4034000 24300 Channel 3 IS136B 16 / 16 4068000 24300.3 Channel 4 IS136B 16 / 16 4034000 24300.1
16QAMPN
16QAMPN
16QAMPN
16QAMPN
QPSKPN
QPSKPN
QPSKPN
QPSKPN
File Name: EX05QPSK
Description: This ...