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28 Pages

Lec04_II_Dyn_Tomasulo

Course: ECE 690, Fall 2009
School: NJIT
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Word Count: 5525

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Computer ECE690 Systems Architecture Spring 2005 Lecture 04-II: Instruction-Level Parallelism and Dynamic Exploitation Jie Hu http://web.njit.edu/~jhu/ece690 [Adapted from Computer Architecture: A Quantitative Approach, J. L. Hennessy and D. A. Patterson, 3rd Edition, Morgan Kaufmann. Copyright 2001 UCB. ] Todays Lecture Data dependences and data hazards Control dependences Dynamic scheduling to overcome data...

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Computer ECE690 Systems Architecture Spring 2005 Lecture 04-II: Instruction-Level Parallelism and Dynamic Exploitation Jie Hu http://web.njit.edu/~jhu/ece690 [Adapted from Computer Architecture: A Quantitative Approach, J. L. Hennessy and D. A. Patterson, 3rd Edition, Morgan Kaufmann. Copyright 2001 UCB. ] Todays Lecture Data dependences and data hazards Control dependences Dynamic scheduling to overcome data hazards Scoreboard dynamic scheduling algorithm Tomasulo dynamic scheduling algorithm Hu, NJIT, Spring 2005 ECE690 Lec04_II.2 1 Tomasulos Algorithm For IBM 360/91 (before caches!) Goal: High Performance without special compilers Small number of floating point registers (4 in 360) prevented interesting compiler scheduling of operations This led Tomasulo to try to figure out how to get more effective registers renaming in hardware! Why Study 1966 Computer? The descendants of this have flourished! Alpha 21264, HP 8000, MIPS 10000, Pentium III, PowerPC 604, Hu, NJIT, Spring 2005 ECE690 Lec04_II.3 Tomasulos Algorithm Control & buffers distributed with Function Units (FU) FU buffers called reservation stations; have pending operands Registers in instructions replaced by values or pointers to reservation stations(RS); called register renaming ; avoids WAR, WAW hazards More reservation stations than registers, so can do optimizations compilers cant Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs Load and Stores treated as FUs with RSs as well Integer instructions can go past branches, allowing FP ops beyond basic block in FP queue Hu, NJIT, Spring 2005 ECE690 Lec04_II.4 2 Tomasulo Organization From inst. unit Load-store op Store Address unit Address unit Buffers Load Buffers Load1 Load2 Load3 Load4 Load5 Add1 Add2 Add3 Mult1 Mult2 FP Registers FP Op Queue data address FP adders FP adders Memory unit Memory unit Reservation Stations FP multipliers FP multipliers Common Data Bus (CDB) Hu, NJIT, Spring 2005 ECE690 Lec04_II.5 Tomaulo Algorithm Implementation Reservation station has seven fields Op: Operation to perform in the unit (e.g., + or ) Vj, Vk: Value of Source operands Store buffers has V field, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) Note: Qj,Qk=0 => ready Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Register status Qi: number of reservation station whose operation will write this register. Blank when no active instructions that will write that register. Hu, NJIT, Spring 2005 ECE690 Lec04_II.6 3 Three Stages of Tomasulo Algorithm 1. Issueget instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Executeoperate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write resultfinish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available Common data bus: data + source (come from bus) 64 bits of data + 4 bits of Reservation Station source address Write if matches expected Reservation Station (produces result) Does the broadcast Example speed: 3 clocks for Fl .pt. +,-; 10 for * ; 40 clks for / Hu, NJIT, Spring 2005 ECE690 Lec04_II.7 Instruction stream Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 Time j 34+ 45+ F2 F6 F0 F8 Tomasulo Example k R2 R3 F4 F2 F6 F2 Issue Exec Write Comp Result Load1 Load2 Load3 Busy No No No Address 3 Load/Buffers Op S1 Vj S2 Vk RS Qj RS Qk Reservation Stations: FU count down Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No 3 FP Adder R.S. 2 FP Mult R.S. Register result status: Clock 0 Qi F0 F2 F4 F6 F8 F10 F12 ... F30 Clock cycle counter Hu, NJIT, Spring 2005 ECE690 Lec04_II.8 4 Tomasulo Example Cycle 1 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 Time j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Issue 1 Exec Write Comp Result Load1 Load2 Load3 Busy Yes No No Address 34+R2 Reservation Stations: Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No Op S1 Vj S2 Vk RS Qj RS Qk Register result status: Clock 1 Qi F0 F2 F4 F6 Load1 F8 F10 F12 ... F30 Hu, NJIT, Spring 2005 ECE690 Lec04_II.9 Tomasulo Example Cycle 2 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 Time j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Issue 1 2 Exec Write Comp Result Load1 Load2 Load3 Busy Yes Yes No Address 34+R2 45+R3 Reservation Stations: Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No Op S1 Vj S2 Vk RS Qj RS Qk Register result status: Clock 2 Qi F0 F2 Load2 F4 F6 Load1 F8 F10 F12 ... F30 Note: Can have multiple loads outstanding Hu, NJIT, Spring 2005 ECE690 Lec04_II.10 5 Tomasulo Example Cycle 3 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 Time j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Issue 1 2 3 Exec Write Comp Result 3 Load1 Load2 Load3 Busy Yes Yes No Address 34+R2 45+R3 Reservation Stations: Op Name Busy Add1 No Add2 No Add3 No Mult1 Yes MULTD Mult2 No S1 Vj S2 Vk RS Qj RS Qk R(F4) Load2 Register result status: Clock 3 Qi F0 Mult1 F2 Load2 F4 F6 Load1 F8 F10 F12 ... F30 Note: registers names removed (renamed) in RS; MULT issued Load1 completing; what is waiting for Load1? Hu, NJIT, Spring 2005 ECE690 Lec04_II.11 Tomasulo Example Cycle 4 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 Time j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Issue 1 2 3 4 Exec Write Comp Result 3 4 4 Load1 Load2 Load3 Busy No Yes No Address 45+R3 Reservation Stations: S1 Op Vj Name Busy Add1 Yes SUBD M(A1) Add2 No Add3 No Mult1 Yes MULTD Mult2 No S2 Vk RS Qj RS Qk Load2 R(F4) Load2 Register result status: Clock 4 Qi F0 Mult1 F2 Load2 F4 F6 M(A1) F8 Add1 F10 F12 ... F30 Load2 completing; what is waiting for Load2? Hu, NJIT, Spring 2005 ECE690 Lec04_II.12 6 Tomasulo Example Cycle 5 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 Time j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Issue 1 2 3 4 5 Exec Write Comp Result 3 4 4 5 Load1 Load2 Load3 Busy No No No Address Reservation Stations: S1 S2 Op Vj Vk Name Busy 2 Add1 Yes SUBD M(A1) M(A2) Add2 No Add3 No 10 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) RS Qj RS Qk Mult1 Register result status: Clock 5 Qi F0 Mult1 F2 M(A2) F4 F6 M(A1) F8 Add1 F10 Mult2 F12 ... F30 Hu, NJIT, Spring 2005 ECE690 Lec04_II.13 Tomasulo Example Cycle 6 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 Time j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Issue 1 2 3 4 5 6 Exec Write Comp Result 3 4 4 5 Load1 Load2 Load3 Busy No No No Address Reservation Stations: S1 S2 Op Vj Vk Name Busy 1 Add1 Yes SUBD M(A1) M(A2) Add2 Yes ADDD M(A2) Add3 No 9 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) RS Qj Add1 RS Qk Mult1 Register result status: Clock 6 Qi F0 Mult1 F2 M(A2) F4 F6 Add2 F8 Add1 F10 Mult2 F12 ... F30 Hu, NJIT, Spring 2005 ECE690 Lec04_II.14 7 Tomasulo Example Cycle 7 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 Time j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Issue 1 2 3 4 5 6 Exec Write Comp Result 3 4 7 4 5 Load1 Load2 Load3 Busy No No No Address Reservation Stations: S1 S2 Op Vj Vk Name Busy 0 Add1 Yes SUBD M(A1) M(A2) Add2 Yes ADDD M(A2) Add3 No 8 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) RS Qj Add1 RS Qk Mult1 Register result status: Clock 7 Qi F0 Mult1 F2 M(A2) F4 F6 Add2 F8 Add1 F10 Mult2 F12 ... F30 ! " Hu, NJIT, Spring 2005 #$ # ECE690 Lec04_II.15 Tomasulo Example Cycle 8 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 7 4 5 8 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 RS Vj Vk Qj Time Name Busy Op Add1 No 2 Add2 Yes ADDD (M-M) M(A2) Add3 No 7 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 RS Qk Register result status: Clock 8 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 Mult1 M(A2) Add2 (M-M) Mult2 Hu, NJIT, Spring 2005 ECE690 Lec04_II.16 8 Tomasulo Example Cycle 9 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 7 4 5 8 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 RS Vj Vk Qj Time Name Busy Op Add1 No 1 Add2 Yes ADDD (M-M) M(A2) Add3 No 6 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 RS Qk Register result status: Clock 9 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 Mult1 M(A2) Add2 (M-M) Mult2 Hu, NJIT, Spring 2005 ECE690 Lec04_II.17 Tomasulo Example Cycle 10 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 7 10 4 5 8 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 RS Vj Vk Qj Time Name Busy Op Add1 No 0 Add2 Yes ADDD (M-M) M(A2) Add3 No 5 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 RS Qk Register result status: Clock 10 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 Mult1 M(A2) Add2 (M-M) Mult2 Add2 (ADDD) completing; what is waiting for it? Hu, NJIT, Spring 2005 ECE690 Lec04_II.18 9 Tomasulo Example Cycle 11 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 7 10 4 5 8 11 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 RS Vj Vk Qj Time Name Busy Op Add1 No Add2 No Add3 No 4 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 RS Qk Register result status: Clock 11 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 Mult1 M(A2) (M-M+M)M-M) Mult2 ( Write result of ADDD here? All quick instructions complete in this cycle! Hu, NJIT, Spring 2005 ECE690 Lec04_II.19 Tomasulo Example Cycle 12 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 7 10 4 5 8 11 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 RS Vj Vk Qj Time Name Busy Op Add1 No Add2 No Add3 No 3 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 RS Qk Register result status: Clock 12 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 Mult1 M(A2) (M-M+M)M-M) Mult2 ( Hu, NJIT, Spring 2005 ECE690 Lec04_II.20 10 Tomasulo Example Cycle 13 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 7 10 4 5 8 11 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 RS Vj Vk Qj Time Name Busy Op Add1 No Add2 No Add3 No 2 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 RS Qk Register result status: Clock 13 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 Mult1 M(A2) (M-M+M)M-M) Mult2 ( Hu, NJIT, Spring 2005 ECE690 Lec04_II.21 Tomasulo Example Cycle 14 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 7 10 4 5 8 11 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 RS Vj Vk Qj Time Name Busy Op Add1 No Add2 No Add3 No 1 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 RS Qk Register result status: Clock 14 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 Mult1 M(A2) (M-M+M)M-M) Mult2 ( Hu, NJIT, Spring 2005 ECE690 Lec04_II.22 11 Tomasulo Example Cycle 15 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 15 7 10 4 5 8 11 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 RS Vj Vk Qj Time Name Busy Op Add1 No Add2 No Add3 No 0 Mult1 Yes MULTD M(A2) R(F4) Mult2 Yes DIVD M(A1) Mult1 RS Qk Register result status: Clock 15 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 Mult1 M(A2) (M-M+M)M-M) Mult2 ( Mult1 (MULTD) completing; what is waiting for it? Hu, NJIT, Spring 2005 ECE690 Lec04_II.23 Tomasulo Example Cycle 16 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 15 7 10 4 5 16 8 11 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 Vj Vk Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No 40 Mult2 Yes DIVD M*F4 M(A1) RS Qj RS Qk Register result status: Clock 16 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 M*F4 M(A2) (M-M+M)M-M) Mult2 ( Just waiting for Mult2 (DIVD) to complete Hu, NJIT, Spring 2005 ECE690 Lec04_II.24 12 Skip a couple of cycles Hu, NJIT, Spring 2005 ECE690 Lec04_II.25 Tomasulo Example Cycle 55 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 15 7 10 4 5 16 8 11 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 Vj Vk Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No 1 Mult2 Yes DIVD M*F4 M(A1) RS Qj RS Qk Register result status: Clock 55 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 M*F4 M(A2) (M-M+M)M-M) Mult2 ( Hu, NJIT, Spring 2005 ECE690 Lec04_II.26 13 Tomasulo Example Cycle 56 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 15 7 56 10 4 5 16 8 11 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 Vj Vk Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No 0 Mult2 Yes DIVD M*F4 M(A1) RS Qj RS Qk Register result status: Clock 56 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 M*F4 M(A2) (M-M+M)M-M) Mult2 ( Mult2 (DIVD) is completing; what is waiting for it? Hu, NJIT, Spring 2005 ECE690 Lec04_II.27 Tomasulo Example Cycle 57 Instruction status: Instruction LD F6 LD F2 MULTD F0 SUBD F8 DIVD F10 ADDD F6 j 34+ 45+ F2 F6 F0 F8 k R2 R3 F4 F2 F6 F2 Exec Write Issue Comp Result 1 2 3 4 5 6 3 4 15 7 56 10 4 5 16 8 57 11 Load1 Load2 Load3 Busy Address No No No Reservation Stations: S1 S2 Vj Vk Time Name Busy Op Add1 No Add2 No Add3 No Mult1 No Mult2 Yes DIVD M*F4 M(A1) RS Qj RS Qk Register result status: Clock 56 FU Qi F0 F2 F4 F6 F8 F10 F12 ... F30 M*F4 M(A2) (M-M+M)M-M) Result ( Once again: In-order issue, out-of-order execution and out-of-order completion. Hu, NJIT, Spring 2005 ECE690 Lec04_II.28 14 Tomasulo Loop Example Loop: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 This time assume Multiply takes 4 clocks Assume 1st load takes 8 clocks (L1 cache miss), 2nd load takes 1 clock (hit) To be clear, will show clocks for SUBI, BNEZ Reality: integer instructions ahead of Fl. Pt. Instructions Show 2 iterations Hu, NJIT, Spring 2005 ECE690 Lec04_II.29 Instruction status: ITER Instruction 1 1 1 Iter2 ation 2 Count 2 Time LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 Loop Example j 0 F0 0 0 F0 0 Op k R1 F2 R1 R1 F2 R1 Vj Exec Write Issue CompResult Load1 Load2 Load3 Store1 Store2 Store3 S1 Vk S2 Qj RS Qk Code: LD MULTD SD SUBI BNEZ Busy Addr No No No No No No Fu Reservation Stations: Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No R1 80 Qi Fu Added Store F4 Buffers F0 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Instruction Loop Clock 0 F0 F2 F4 F6 F8 F10 F12 ... F30 Value of Register used for address, iteration control Hu, NJIT, Spring 2005 ECE690 Lec04_II.30 15 Instruction status: ITER Instruction 1 LD F0 Loop Example Cycle 1 j 0 k R1 Exec Write Issue CompResult 1 Load1 Load2 Load3 Store1 Store2 Store3 S2 Qj RS Qk Code: LD MULTD SD SUBI BNEZ Busy Addr Yes No No No No No 80 Fu Reservation Stations: Time Name Busy Add1 No Add2 No Add3 No Mult1 No Mult2 No R1 80 Op Vj S1 Vk F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 1 F0 Qi Fu Load1 F2 F4 F6 F8 F10 F12 ... F30 Hu, NJIT, Spring 2005 ECE690 Lec04_II.31 Instruction status: ITER Instruction 1 1 LD MULTD F0 F4 Loop Example Cycle 2 j 0 F0 k R1 F2 Exec Write Issue CompResult 1 2 Load1 Load2 Load3 Store1 Store2 Store3 S2 Qj RS Qk Code: LD MULTD SD SUBI BNEZ Busy Addr Yes No No No No No 80 Fu Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No R1 80 Vj S1 Vk R(F2) Load1 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 2 F0 Qi Fu Load1 F2 F4 Mult1 F6 F8 F10 F12 ... F30 Hu, NJIT, Spring 2005 ECE690 Lec04_II.32 16 Instruction status: ITER Instruction 1 1 1 LD MULTD SD F0 F4 F4 Loop Example Cycle 3 j 0 F0 0 k R1 F2 R1 Exec Write Issue CompResult 1 2 3 Load1 Load2 Load3 Store1 Store2 Store3 S2 Qj RS Qk Code: LD MULTD SD SUBI BNEZ Busy Addr Yes No No Yes No No 80 Fu 80 Mult1 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No R1 80 Vj S1 Vk R(F2) Load1 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 3 F0 Qi Fu Load1 F2 F4 Mult1 F6 F8 F10 F12 ... F30 Implicit renaming sets up data flow graph Hu, NJIT, Spring 2005 ECE690 Lec04_II.33 Instruction status: ITER Instruction 1 1 1 LD MULTD SD F0 F4 F4 Loop Example Cycle 4 j 0 F0 0 k R1 F2 R1 Exec Write Issue CompResult 1 2 3 Load1 Load2 Load3 Store1 Store2 Store3 S2 Qj RS Qk Code: LD MULTD SD SUBI BNEZ Busy Addr Yes No No Yes No No 80 Fu 80 Mult1 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No R1 80 Vj S1 Vk R(F2) Load1 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 4 F0 Qi Fu Load1 F2 F4 Mult1 F6 F8 F10 F12 ... F30 Dispatching SUBI Instruction (not in FP queue) Hu, NJIT, Spring 2005 ECE690 Lec04_II.34 17 Instruction status: ITER Instruction 1 1 1 LD MULTD SD F0 F4 F4 Loop Example Cycle 5 j 0 F0 0 k R1 F2 R1 Exec Write Issue CompResult 1 2 3 Load1 Load2 Load3 Store1 Store2 Store3 S2 Qj RS Qk Code: LD MULTD SD SUBI BNEZ Busy Addr Yes No No Yes No No 80 Fu 80 Mult1 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No R1 72 Vj S1 Vk R(F2) Load1 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 5 F0 Qi Fu Load1 F2 F4 Mult1 F6 F8 F10 F12 ... F30 And, BNEZ instruction (not in FP queue) Hu, NJIT, Spring 2005 ECE690 Lec04_II.35 Instruction status: ITER Instruction 1 1 1 2 LD MULTD SD LD F0 F4 F4 F0 Loop Example Cycle 6 j 0 F0 0 0 k R1 F2 R1 R1 Exec Write Issue CompResult 1 2 3 6 Load1 Load2 Load3 Store1 Store2 Store3 S2 Qj RS Qk Code: LD MULTD SD SUBI BNEZ Busy Addr Yes Yes No Yes No No 80 72 80 Fu Mult1 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 No R1 72 Vj S1 Vk R(F2) Load1 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 6 F0 Qi Fu Load2 F2 F4 Mult1 F6 F8 F10 F12 ... F30 Notice that F0 never sees Load from location 80 Hu, NJIT, Spring 2005 ECE690 Lec04_II.36 18 Instruction status: ITER Instruction 1 1 1 2 2 LD MULTD SD LD MULTD F0 F4 F4 F0 F4 Loop Example Cycle 7 j 0 F0 0 0 F0 k R1 F2 R1 R1 F2 Exec Write Issue CompResult 1 2 3 6 7 S1 Vk S2 Qj RS Qk Load1 Load2 Load3 Store1 Store2 Store3 Code: LD MULTD SD SUBI BNEZ Busy Addr Yes Yes No Yes No No 80 72 80 Fu Mult1 Reservation Stations: Time Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 Yes Multd R1 72 Vj R(F2) Load1 R(F2) Load2 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 7 F0 Qi Fu Load2 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Register file completely detached from computation First and Second iteration completely overlapped Hu, NJIT, Spring 2005 ECE690 Lec04_II.37 Instruction status: ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 Loop Example Cycle 8 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Vj Exec Write Issue CompResult 1 2 3 6 7 8 S1 Vk S2 Qj RS Qk Load1 Load2 Load3 Store1 Store2 Store3 Code: LD MULTD SD SUBI BNEZ Busy Addr Yes Yes No Yes Yes No 80 72 80 72 Fu Mult1 Mult2 Reservation Stations: Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 Yes Multd R1 72 R(F2) Load1 R(F2) Load2 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 8 F0 Qi Fu Load2 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Hu, NJIT, Spring 2005 ECE690 Lec04_II.38 19 Instruction status: ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD F0 F4 F4 F0 F4 F4 Loop Example Cycle 9 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Vj Exec Write Issue CompResult 1 2 3 6 7 8 S1 Vk 9 Load1 Load2 Load3 Store1 Store2 Store3 RS Qk Code: LD MULTD SD SUBI BNEZ Busy Addr Yes Yes No Yes Yes No 80 72 80 72 Fu Mult1 Mult2 Reservation Stations: Name Busy Op Add1 No Add2 No Add3 No Mult1 Yes Multd Mult2 Yes Multd R1 72 S2 Qj R(F2) Load1 R(F2) Load2 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 9 F0 Qi Fu Load2 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Load1 completing: who is waiting? Note: Dispatching SUBI Hu, NJIT, Spring 2005 ECE690 Lec04_II.39 Instruction status: ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Loop Example Cycle 10 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue CompResult 1 2 3 6 7 8 9 10 Load1 Load2 Load3 Store1 Store2 Store3 Code: LD MULTD SD SUBI BNEZ Busy Addr No Yes No Yes Yes No 72 80 72 Fu F0 F4 F4 F0 F4 F4 10 Mult1 Mult2 Reservation Stations: 4 S1 S2 RS Name Busy Op Vj Vk Qj Qk Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd R(F2) Load2 R1 64 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 10 F0 Qi Fu Load2 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Load2 completing: who is waiting? Note: Dispatching BNEZ Hu, NJIT, Spring 2005 ECE690 Lec04_II.40 20 Instruction status: ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Loop Example Cycle 11 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue CompResult 1 2 3 6 7 8 9 10 Load1 Load2 Load3 Store1 Store2 Store3 Code: LD MULTD SD SUBI BNEZ Busy Addr No No Yes Yes Yes No 64 80 72 Fu F0 F4 F4 F0 F4 F4 10 11 Mult1 Mult2 Reservation Stations: 3 4 S1 Name Busy Op Vj Vk Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd M[72] R(F2) R1 64 S2 Qj RS Qk F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 11 F0 Qi Fu Load3 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Next load in sequence Hu, NJIT, Spring 2005 ECE690 Lec04_II.41 Instruction status: ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Loop Example Cycle 12 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue CompResult 1 2 3 6 7 8 9 10 Load1 Load2 Load3 Store1 Store2 Store3 Code: LD MULTD SD SUBI BNEZ Busy Addr No No Yes Yes Yes No 64 80 72 Fu F0 F4 F4 F0 F4 F4 10 11 Mult1 Mult2 Reservation Stations: 2 3 S1 Name Busy Op Vj Vk Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd M[72] R(F2) R1 64 S2 Qj RS Qk F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 12 F0 Qi Fu Load3 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Why not issue third multiply? Hu, NJIT, Spring 2005 ECE690 Lec04_II.42 21 Instruction status: ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Loop Example Cycle 13 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue CompResult 1 2 3 6 7 8 9 10 Load1 Load2 Load3 Store1 Store2 Store3 Code: LD MULTD SD SUBI BNEZ Busy Addr No No Yes Yes Yes No 64 80 72 Fu F0 F4 F4 F0 F4 F4 10 11 Mult1 Mult2 Reservation Stations: 1 2 S1 Name Busy Op Vj Vk Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd M[72] R(F2) R1 64 S2 Qj RS Qk F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 13 F0 Qi Fu Load3 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Why not issue third store? Hu, NJIT, Spring 2005 ECE690 Lec04_II.43 Instruction status: ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Loop Example Cycle 14 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue CompResult 1 2 3 6 7 8 9 14 10 10 Load1 Load2 Load3 Store1 Store2 Store3 Code: LD MULTD SD SUBI BNEZ Busy Addr No No Yes Yes Yes No 64 80 72 Fu F0 F4 F4 F0 F4 F4 11 Mult1 Mult2 Reservation Stations: 0 1 S1 Name Busy Op Vj Vk Add1 No Add2 No Add3 No Mult1 Yes Multd M[80] R(F2) Mult2 Yes Multd M[72] R(F2) R1 64 S2 Qj RS Qk F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Clock 14 F0 Qi Fu Load3 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Mult1 completing. Who is waiting? Hu, NJIT, Spring 2005 ECE690 Lec04_II.44 22 Instruction status: ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Loop Ex...

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NJIT - CIS - 392
Well, I?ve decided I can bear the guilt no longer. After savoring the most exciting vacation of my life so far for four months, I?m finally giving back to the online cruise community by writing a review. Pretty bold statement considering this is ju
Acton School of Business - BIOE - 301
BIOE301LectureEighteenReviewofLastTimeHowdowetreatcoronaryarterydisease? CABG PTCA Stent PreventionPreventionvs.TreatmentRiskFactorsforHeartDisease Tobaccouse HighbloodpressureOver70%notundercontrol Over80%notundercontrolHig
Acton School of Business - ECON - 446
Econ 446 MT # 1 February 27, 2008 R. Sickles Answer all of the following questions. You have 50 minutes. You may use a calculator and an 8 1/2 x 11 sheet of paper with notes, etc. on both sides. Questions 1-6 are worth 5 points each, question 7 is wo
Acton School of Business - ECON - 446
Econ 446 Lab Mar. 28 2008 spring Topic: Dummy Variables Online Resources: http:/www.bus.lsu.edu/economics/faculty/chill/personal/undergraduate_econometrics.htm 9.6 (d)(iv) construct t-statistic: t = (b6-b5)/se(b6-b5). 9.7 (a), (b) straightforward (c)
Acton School of Business - COMP - 210
COMP 210, FALL 2000 Lecture 11: Moving Beyond ListsStart of the second third of COMP 210 - the first lecture for the second exam.Reminders: Homework assignment next Friday 9/30/00 Exam will be 9/27/2000, in classclosed-notes, closed-book Revie
Acton School of Business - PHYS - 102
Acton School of Business - PHYS - 102
PHYS102 - Gausss Law.Dr. Suess January 31, 2007PRS Questions 2 Question #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Answer to Ques
Stanford - CAL - 070907
Acton School of Business - MECH - 403
-Complete COSMOSWorks Static Analysis of a Assembly (CW Tutorial #2) Assigned 9/15/05-Adam Parsons Tue, 13 Sep 2005 19:37:07Ali Hamshari Thu, 8 Sep 2005 14:19:19Ashley Edison Tue, 13 Sep 2005 14:02:53Brad Tonnesen Thu, 15 Sep
Acton School of Business - HIST - 327
Acton School of Business - SOCI - 445
Acton School of Business - BIOS - 352
Name: Answers Page Score 1 _ 2 _ 3 _ 4 _ 5 _ 6 _ 7 _ 8 _ Total _ Pledge:Examination I Bios. 352 - Physical Chemistry for the Biosciences February 2, 2007 (closed book, in class)A. (35 points) Ethanol has been used as an intoxicant by Homo sapiens
Siena - CSIS - 114
Security, Privacy, and Ethical Issues in Information Systems and the InternetChapter 14Social Issues in Information Systems Computer Waste Cyber Crime Privacy Issues Ethical Issues Health Concerns Patent & CopyrightIssuesComputer Waste
St. John Fisher - KEEP - 03446
Living Environment Period 8 Mr. Whalen Dissolved Oxygen Lab Purpose The Purpose of the Dissolved Oxygen Lab is to show students the affects poor water quality has on the plant and animal life of underwater ecosystems. Students will be able to perform
St. John Fisher - KEEP - 03972
Tim Patchett CSCI150-02 Tkp03972@sjfc.edu Assignment #8 St. John Fisher Spring Athletics Slide 1 Introduction Slide 2 Spring Sports: Lacrosse, Golf, Baseball, and Tennis Slide 3 Lacrosse, overview and season outlook. Slide 4 Beginning of 07 seaso
St. John Fisher - PTE - 07977
Web Pages Used http:/beginnersinvest.about.com/gi/dynamic/offsite.htm? zi=1/XJ/Ya&sdn=beginnersinvest&cdn=money&tm=3&f=00&tt=14&bt=1&bts=0&zu=http %3A/www.dailycelebrations.com/112599.htm http:/www.youtube.com/watch?v=h_kMkQCZV8o http:/l
St. John Fisher - SUN - 231
Fall 2002 CSCI 162 Laboratory 12 The Joy of Sets Objectives Implement heterogeneous sets - the Set struct Work with a struct of ordered lists 12.1 Getting startedThe files that you will use are set12.h (containing the definition of the struct Se
Wagner - CS - 400
GRAPHIC DESIGNA thesis written at WAGNER COLLEGE in partial fulfillment of the requirements for the degree ofBACHELOR OF SCIENCE IN COMPUTER SCIENCEby Tara Ferraiuolo December 20032Abstract Since the 1940's, the computer has dramatically ch
Wagner - FILESTORE - 416
Wagner - FILESTORE - 419
NJ City - EDTC - 617
EDTC617: Website CritiqueBy Julio A. Velasco, December 14, 20031Educational Technology Department School of Education, New Jersey City University Dr. Beva Eastman, ProfessorWebsite: JavaPowered.com! URL4http:/www.javapowered.com I visited this
NJ City - CS - 209
Chapter 3Array-Based ListsDr. Liu1Chapter Objectives Learn about lists Explore how various operations, such as search, insert, and remove, on lists are implemented Learn how to design and implement a generic class to process various types o
Scranton - MATH - 345
Tarskis AxiomsUndefined terms: between and congruent Notation: ab cd is an abbreviation for congruent(a,b,c,d) a. b. c is an abbreviation for between(a,b,c) Note: We can think of all variables as representing points, ab cd as saying the distance
Texas Tech - ETD - 10232007
Writing an Original Score for the Oxford Street Players of Lesley Universitys Production of The Merry Wives of Windsor, Texas: shore know how to git a man down by Terry Michael Chance, B.A., M.A. A DISSERTATION IN FINE ARTS Submitted to the Graduate
Texas Tech - ETD - 08272008
CYBERSPACIAL EDUCATED INTELLIGENT COMPUTER AIDED ARCHITECTURAL DESIGN SYSTEM (C.E.I.C.A.A.D.S.) by JAMES C. GOODLETT, B.ARCH. A THESIS IN ARCHITECTURE Submitted to the Graduate Faculty of Texas Tech University in Partial FulfiHment of the Requirement
Texas Tech - ETD - 07312008
BEHAVIORAL AND ENVIRONMENTAL MANAGEMENT OF FEEDLOT CATTLE by FRANK MICHAEL MITLOHNER, M.S. A DISSERTATION IN ANIMAL SCIENCE Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of DOCTOR
Texas Tech - ENGLISH - 5377
Marketing Your Service:On Becoming VisibleBY RICH MAGGIANI, Associate Fellow, Vermont Chapteryour careerou check into a hotel. How do you know your room is clean? You visit a lawyer. How do you know she is competent? You stop at a tailor's shop
Texas Tech - ENGLISH - 5377
Kevin Burnett Mentoring Assignment Introduction My primary goals and decisions over the next couple of years are related to location and vocational field. The locations are Japan and the United States. The vocational fields are teaching English as a
Texas Tech - ETD - 10272008
RELEVANCE AND MOTIVATION: STUDENT REPORTS OF EFFECTIVE TEACHER STRATEGIESbyJAMIE LYNNE WALTERS, B.A.A THESIS IN COMMUNICATION STUDIES Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the D
Stanford - LINGUIST - 238
LING 138/238 SYMBSYS 138 Intro to Computer Speech and Language ProcessingLecture 6: Part of Speech Tagging (II): October 14, 2004 Neal SniderThanks to Dan Jurafsky, Jim Martin, Dekang Lin, and Bonnie Dorr for some of the examples and details in th
Santa Clara - COEN - 178
Schedule Today:xSecurity, Object-Relational Systems. x Read Section 8.7. Nextx Indexing. x ReadSection 6.6.5 And Thenx Queryoptimization. x No Readings in TextSCU Holliday 121Terminology A Vulnerability is a weakness in the system t
Santa Clara - COEN - 120
vti_encoding:SR|utf8-nl vti_timelastmodified:TR|07 Jan 2001 22:44:00 -0000 vti_extenderversion:SR|4.0.2.4426 vti_filesize:IR|241152 vti_title:SR|Introduction vti_assignedto:SR| vti_approvallevel:SR| vti_backlinkinfo:VX| vti_nexttolasttimemodified:TR|
Santa Clara - COEN - 288
PowerPoint Slides to AccompanyA Gift of Fire: Social, Legal, and Ethical Issues for Computers and the Internet(2nd Edition)by Sara BaaseSan Diego State UniversityPowerPoint slides created by Sherry Clark Copyright 2003 Prentice HallA Gift o
Santa Clara - ENGR - 300
Databases and Product MarketingPage 1 of 2Databases and Product MarketingTechnologyThe technology and workings of relational databases are somewhat unknown to the general public, however their impact on society is considerable. A basic database
Santa Clara - COEN - 120
= MICROSOFT FOUNDATION CLASS LIBRARY : DishWasherGUI=AppWizard has created this DishWasherGUI application for you. This applicationnot only demonstrates the basics of using the Microsoft Foundation classesbut is also a starting point fo
Santa Clara - ENGR - 019
Stem Cell ResearchWhat are Stem Cells?Self RegenerationDifferentiationWhat types of stem cells are there?EmbryonicAdult1Why bother?Alzheimer's Parkinsons Diabetes Muscular Dystrophy ALS Arthritis Heart Disease Multiple Sclerosis Vario
Santa Clara - COEN - 194
Santa Clara UniversityDEPARTMENT of COMPUTER ENGINEERINGDate: May 14, 2004I HEREBY RECOMMEND THAT THE THESIS PREPARED UNDER MY SUPERVISION BYMozhdeh Rastegarpanah and Joelle StringerENTITLEDProactive Java Application for Telemetry Data Anal
Santa Clara - COEN - 194
Santa Clara UniversityDEPARTMENT of COMPUTER ENGINEERINGDate: June 4, 2004I HEREBY RECOMMEND THAT THE THESIS PREPARED UNDER MY SUPERVISION BYMozhdeh Rastegarpanah and Joelle StringerENTITLEDProactive Java Application for Telemetry Data Anal
Santa Clara - COEN - 120
SpyPlaneReport on Configuration DefaultConfigPACKAGESDefault GLOBALS: ACTORS:actor_0Relations: itsTest Association with Test, Multiplicity of 1, Bi-directionalPilotRelations: itsSet Target Coordinates Association with Set Target Coordinates,
Santa Clara - COEN - 120
MyDHCPReport on Configuration DefaultConfigPACKAGESDefault USE CASE DIAGRAMS:DHCP_UseCaseDHCP ProtocolAllocate IP AddressAllocate Specific IP Address<include><include>Renew IP Address <include> DHCP Client <include>Check DHCP Reposi
Santa Clara - COEN - 120
MyDHCPReport on Configuration DefaultConfigPACKAGESDefault USE CASE DIAGRAMS:DHCP_UseCaseDHCP ProtocolAllocate IP AddressAllocate Specific IP Address<include><include>Renew IP AddressCheck DHCP Repository <include>DHCP Client <inc
Santa Clara - COEN - 120
Todd King Sonia BuiGroup 6 project proposalWireless text messaging deviceOur group has decided to create a wireless text messaging device similar to Motorolas Two-Way Personal Communicators. These devices are basically cell phones with text messa
Santa Clara - GROUP - 120
Todd King Sonia BuiGroup 6 project proposalWireless text messaging deviceOur group has decided to create a wireless text messaging device similar to Motorolas Two-Way Personal Communicators. These devices are basically cell phones with text messa
Santa Clara - COEN - 120
GroupProjectReport on Configuration DefaultConfigPACKAGESDefault GLOBALS: ACTORS:UserThe user pushes buttons to request an elevator. The user pushes appropriate button for desired floor destination. Relations: itsFloor_Car_Interface Uses Associ
Santa Clara - GROUP - 120
GroupProjectReport on Configuration DefaultConfigPACKAGESDefault GLOBALS: ACTORS:UserThe user pushes buttons to request an elevator. The user pushes appropriate button for desired floor destination. Relations: itsFloor_Car_Interface Uses Associ
Santa Clara - ENGR - 019
Air and Water PollutionBy: Kalie Bass Chris Lamm E. David RodriguezEthical AnalysisAir and water pollution are OKREASON 1: Humans have been polluting the world for centuries. REASON 2: By the time any serious environmental effects take place wel
Santa Clara - ENGR - 019
ENGR019/301 Wednesday, December 03, 2003Final ExamFall 2003This exam should take you approximately 2 hours to complete. Do not make it your weeks work. Do not stress over it. Relax, grab a soda and something to eat, sit down, spend 2 hours and
Santa Clara - ENGR - 019
The Ethics of Gas GuzzlersGiovanni MinelliI will discuss the difficulties and benefits that gas guzzler automobiles have on our society as a whole. Gas guzzler automobiles are not only the popular SUVs and large vans but many of the worst listing
Purdue - CHEM - 513
Chemistry 513 / Problem Set #5 Febru a ry 12, 2009 / Due: Febru a ry 19, 2009SciFinder Scholar: Please use SciFinder forall questions. Also, besides the answer, please indicate to me your search path so Ican understand how you approached the ques
Santa Clara - COEN - 288
The Freedom of InformationThe Freedom of InformationBy: Rosa TantaleanIntroduction Global Information Infrastructure Freedom of Information Which countries really need the new technology? The ethical analysis ConclusionIntroductionThere are
Texas Tech - ETD - 07092007
Effects of Integrated Marketing Communication (IMC) on Visitors Heritage Destination Selectionby Yu-Ju Wang, B.A. A Thesis In NUTRITION HOSPITALITY & RETAILING Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the
Texas Tech - ETD - 03162008
Tax Incentives and Domestic Investment: An Empirical Analysis of the Repatriation Decisions of U.S. Multinational Corporations Following the Implementation of the Homeland Investment Act of 2004by Michaele L. Morrow, MPA A Dissertation In BUSINESS
Texas Tech - ETD - 06262008
THE TRANSFORMATIVE POWER OF ART: A SELF-STUDY by ELIZABETH GONZALEZ LEAL, B.A., M.F.A. A DISSERTATION IN FINE ARTS Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILO
Texas Tech - ETD - 01292009
AN ACTRESS' APPROACH TO THE ROLE OF HESTHER SALOMON IN PETER SHAFFER'S EQUUS by HEATHER BRYSON, B.A.A THESIS IN THEATRE ARTS Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of MAS
Texas Tech - ETD - 10272008
^v<*-METAMORPHOSIS AND THE EMERGENCE OF THE FEMININE: A MOTIF OF "DIFFERENCE" IN RECENT FEMINIST QUEST FICTIONbyPAULA J. SMITH ALLEN, B.A., M.A. A DISSERTATION IN ENGLISH Submitted to the Graduate Faculty of Texas Tech University in Partial Fulf
Texas Tech - ETD - 06272008
GENETICS OF COMMITMENT TO CELL DIVISION IN S. CEREVISIAE by JIAN ZHANG, B.S. A DISSERTATION IN CELL & MOLECULAR BIOLOGY Submitted to the Graduate Faculty of Texas Tech University Health Sciences Center in Partial Fulfillment of the Requirements for t
Texas Tech - RHIM - 5200
INDIVIDUAL SCORE SHEETRecord your answers to each question in the corresponding box1. Total your A's in each horizontal rowA B C D E F G H1 9 17 25 33 41 49 572 10 18 26 34 42 50 583 11 19 27 35 43 51 594 12 20 28 36 44 52 605 13 21 29
Texas Tech - ENGLISH - 5387
Instant Information from a Single SourceUsing XML for Cross-Media Publishing and Syndication 2001, Arbortext, Inc. All rights reserved. Specifications are subject to change without notice. Epic and Intermarket are trademarks of Arbortext, Inc. All
Texas Tech - ENGLISH - 5371
MOO Appetizers for 10/23/06 CW Ch. 29, Sauer (R), Grabill & Simmons (R) As we move from the Central Works book to Sauer's book on The Rhetoric of Risk, I'd like you to think about how you can use your MOO appetizer to help us review the central ideas
Texas Tech - M - 3354
Supplemental Laplace Transform Problems Find the Laplace transform of the functions: 1. e5t sin(2t) 2. t2 e5t 3. t3 + e2t cos(3t) 4. u(t 1)e2t 5. u(t 1)t 6. u(t ) sin(t) 7. u(t 2)t2 8. u(t 2)(2t 1) 9. u(t 1)e2t t 2 2 s2 + 10 s + 29 2
Texas Tech - FIN - 6331
FIN6331 Foundations of Finance Summer(2) 2008 Course and contact information: Professor: Jack Cooney Email: jack.cooney@.ttu.edu Web: http:/jcooney.ba.ttu.edu/fin6331.html Classroom: BA360 Teaching assistants Maggie Foley caoxiaomei@yahoo.com Office: