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ECTE432_Lecture6_tomasulo2_2008

Course: ECTE 432, Fall 2009
School: Allan Hancock College
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Word Count: 2300

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status: 1 T2-1 T2-2 Instruction LD Loop Example Cycle 1 ITER Instruction F0 j 0 k R1 Exec Write Issue Comp Result 1 Instruction status: Busy Load1 Yes Load2 No Load3 No Store1 No Store2 No Store3 No Loop Example Cycle 2 ITER Instruction 1 1 LD MULTD F0 F4 Addr 80 Fu j 0 F0 k R1 F2 Exec Write Issue Comp Result 1 2 Busy Load1 Yes Load2 No Load3 No Store1 No Store2 No Store3 No Addr 80 Fu Reservation...

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status: 1 T2-1 T2-2 Instruction LD Loop Example Cycle 1 ITER Instruction F0 j 0 k R1 Exec Write Issue Comp Result 1 Instruction status: Busy Load1 Yes Load2 No Load3 No Store1 No Store2 No Store3 No Loop Example Cycle 2 ITER Instruction 1 1 LD MULTD F0 F4 Addr 80 Fu j 0 F0 k R1 F2 Exec Write Issue Comp Result 1 2 Busy Load1 Yes Load2 No Load3 No Store1 No Store2 No Store3 No Addr 80 Fu Reservation Stations: Time Name Add1 Add2 Add3 Mult1 Mult2 R1 80 Busy No No No No No Op Vj S1 Vk S2 Qj RS Qk Reservation Stations: Code: LD MULTD SD SUBI BNEZ Time F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Name Add1 Add2 Add3 Mult1 Mult2 R1 80 Busy Op No No No Yes Multd No Vj S1 Vk S2 Qj RS Qk R(F2) Load1 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Register result status Clock 1 F0 Fu Load1 F2 F4 F6 F8 F10 F12 ... F30 Clock 2 F0 Fu Load1 F2 F4 Mult1 F6 F8 F10 F12 ... F30 T2-3 T2-4 Instruction status: 1 1 1 LD MULTD SD Loop Example Cycle 3 ITER Instruction F0 F4 F4 j 0 F0 0 k R1 F2 R1 Exec Write Issue Comp Result 1 2 3 Instruction status: Busy Load1 Yes Load2 No Load3 No Store1 Yes Store2 No Store3 No Loop Example Cycle 4 ITER Instruction 1 1 1 LD MULTD SD F0 F4 F4 Addr 80 Fu j 0 F0 0 k R1 F2 R1 Exec Write Issue Comp Result 1 2 3 Busy Load1 Yes Load2 No Load3 No Store1 Yes Store2 No Store3 No Addr 80 Fu 80 Mult1 80 Mult1 Reservation Stations: Time Name Add1 Add2 Add3 Mult1 Mult2 R1 80 Busy Op No No No Yes Multd No Vj S1 Vk S2 Qj RS Qk Reservation Stations: Code: LD MULTD SD SUBI BNEZ Time F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Name Add1 Add2 Add3 Mult1 Mult2 R1 80 Busy Op No No No Yes Multd No Vj S1 Vk S2 Qj RS Qk R(F2) Load1 R(F2) Load1 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Register result status Clock 3 F0 Fu Load1 F2 F4 Mult1 F6 F8 F10 F12 ... F30 Clock 4 F0 Fu Load1 F2 F4 Mult1 F6 F8 F10 F12 ... F30 Implicit renaming sets up data flow graph Dispatching SUBI Instruction (not in FP queue) T2-5 T2-6 Instruction status: 1 1 1 LD MULTD SD Loop Example Cycle 5 ITER Instruction F0 F4 F4 j 0 F0 0 k R1 F2 R1 Exec Write Issue Comp Result 1 2 3 Instruction status: Busy Load1 Yes Load2 No Load3 No Store1 Yes Store2 No Store3 No Loop Example Cycle 6 ITER Instruction 1 1 1 2 LD MULTD SD LD F0 F4 F4 F0 Addr 80 Fu j 0 F0 0 0 k R1 F2 R1 R1 Exec Write Issue Comp Result 1 2 3 6 Busy Load1 Yes Load2 Yes Load3 No Store1 Yes Store2 No Store3 No Addr 80 72 80 Fu 80 Mult1 Mult1 Reservation Stations: Time Name Add1 Add2 Add3 Mult1 Mult2 R1 72 Busy Op No No No Yes Multd No Vj S1 Vk S2 Qj RS Qk Reservation Stations: Code: LD MULTD SD SUBI BNEZ Time F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Name Add1 Add2 Add3 Mult1 Mult2 R1 72 Busy Op No No No Yes Multd No Vj S1 Vk S2 Qj RS Qk R(F2) Load1 R(F2) Load1 Code: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Register result status Clock 5 F0 Fu Load1 F2 F4 Mult1 F6 F8 F10 F12 ... F30 Clock 6 F0 Fu Load2 F2 F4 Mult1 F6 F8 F10 F12 ... F30 And, BNEZ instruction (not in FP queue) Notice that F0 never sees Load from location 80 T2-7 T2-8 Instruction status: 1 1 1 2 2 LD MULTD SD LD MULTD Loop Example Cycle 7 ITER Instruction F0 F4 F4 F0 F4 j 0 F0 0 0 F0 k R1 F2 R1 R1 F2 Exec Write Issue Comp Result 1 2 3 6 7 S1 Vk S2 Qj RS Qk Instruction status: Busy Load1 Yes Load2 Yes Load3 No Store1 Yes Store2 No Store3 No Code: LD MULTD SD SUBI BNEZ Loop Example Cycle 8 ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 Mult1 Mult2 R1 72 F0 F4 F4 F0 F4 F4 Addr 80 72 80 Fu j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Vj Exec Write Issue Comp Result 1 2 3 6 7 8 S1 Vk S2 Qj RS Qk Load1 Load2 Load3 Store1 Store2 Store3 Code: LD MULTD SD SUBI BNEZ Busy Yes Yes No Yes Yes No Addr 80 72 80 72 Fu Mult1 Mult1 Mult2 Reservation Stations: Time Name Add1 Add2 Add3 Mult1 Mult2 R1 72 Busy Op No No No Yes Multd Yes Multd Vj Reservation Stations: F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Busy Op No No No Yes Multd Yes Multd R(F2) Load1 R(F2) Load2 R(F2) Load1 R(F2) Load2 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Register result status Clock 7 F0 Fu Load2 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Clock 8 F0 Fu Load2 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Register file is completely detached from computation First and Second iteration completely overlapped T2-9 T2-10 Instruction status: 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 Mult1 Mult2 R1 72 Loop Example Cycle 9 ITER Instruction F0 F4 F4 F0 F4 F4 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Vj Exec Write Issue Comp Result 1 2 3 6 7 8 S1 Vk 9 Load1 Load2 Load3 Store1 Store2 Store3 RS Qk Code: LD MULTD SD SUBI BNEZ Instruction status: Busy Yes Yes No Yes Yes No Loop Example Cycle 10 ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 Mult1 Mult2 R1 64 F0 F4 F4 F0 F4 F4 Addr 80 72 80 72 Fu j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue Comp Result 1 2 3 6 7 8 9 10 Busy Load1 No Load2 Yes Load3 No Store1 Yes Store2 Yes Store3 No Code: LD MULTD SD SUBI BNEZ Addr 72 80 72 Fu Mult1 Mult2 10 Mult1 Mult2 Reservation Stations: Busy Op No No No Yes Multd Yes Multd S2 Qj Reservation Stations: F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 R(F2) Load1 R(F2) Load2 4 S1 S2 RS Busy Op Vj Vk Qj Qk No No No Yes Multd M[80] R(F2) Yes Multd R(F2) Load2 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Register result status Clock 9 F0 Fu Load2 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Clock 10 F0 Fu Load2 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Load1 completing: who is waiting? Note: Dispatching SUBI Load2 completing: who is waiting? Note: Dispatching BNEZ T2-11 T2-12 Instruction status: 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 Mult1 Mult2 R1 64 Loop Example Cycle 11 ITER Instruction F0 F4 F4 F0 F4 F4 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue Comp Result 1 2 3 6 7 8 9 10 Instruction status: Busy Example Addr Loop Cycle 12 ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 Mult1 Mult2 R1 64 F0 F4 F4 F0 F4 F4 Fu j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue Comp Result 1 2 3 6 7 8 9 10 Busy Load1 No Load2 No Load3 Yes Store1 Yes Store2 Yes Store3 No Code: LD MULTD SD SUBI BNEZ Addr Fu 10 11 Load1 No Load2 No Load3 Yes Store1 Yes Store2 Yes Store3 No Code: LD MULTD SD SUBI BNEZ 64 80 72 Mult1 Mult2 10 11 64 80 72 Mult1 Mult2 Reservation Stations: 3 4 S1 Busy Op Vj Vk No No No Yes Multd M[80] R(F2) Yes Multd M[72] R(F2) S2 Qj RS Qk Reservation Stations: F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 2 3 S1 Busy Op Vj Vk No No No Yes Multd M[80] R(F2) Yes Multd M[72] R(F2) S2 Qj RS Qk F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Register result status Clock 11 F0 Fu Load3 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Clock 12 F0 Fu Load3 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Next load in sequence Why not issue third multiply? T2-13 T2-14 Instruction status: 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 Mult1 Mult2 R1 64 Loop Example Cycle 13 ITER Instruction F0 F4 F4 F0 F4 F4 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue Comp Result 1 2 3 6 7 8 9 10 Instruction status: Busy Addr Loop Example Cycle 14 ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 Mult1 Mult2 R1 64 F0 F4 F4 F0 F4 F4 Fu j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue Comp Result 1 2 3 6 7 8 9 14 10 10 Busy Load1 No Load2 No Load3 Yes Store1 Yes Store2 Yes Store3 No Code: LD MULTD SD SUBI BNEZ Addr Fu 10 11 Load1 No Load2 No Load3 Yes Store1 Yes Store2 Yes Store3 No Code: LD MULTD SD SUBI BNEZ 64 80 72 Mult1 Mult2 11 64 80 72 Mult1 Mult2 Reservation Stations: 1 2 S1 Busy Op Vj Vk No No No Yes Multd M[80] R(F2) Yes Multd M[72] R(F2) S2 Qj RS Qk Reservation Stations: F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 0 1 S1 Busy Op Vj Vk No No No Yes Multd M[80] R(F2) Yes Multd M[72] R(F2) S2 Qj RS Qk F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Register result status Clock 13 F0 Fu Load3 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Clock 14 F0 Fu Load3 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Why not issue third store? Mult1 completing. Who is waiting? T2-15 T2-16 Instruction status: 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 Mult1 Mult2 R1 64 Loop Example Cycle 15 ITER Instruction F0 F4 F4 F0 F4 F4 j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Exec Write Issue Comp Result 1 2 3 6 7 8 9 14 10 15 S2 Qj 10 15 11 Instruction status: Busy Addr Loop Example Cycle 16 ITER Instruction 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 Mult1 Mult2 R1 64 F0 F4 F4 F0 F4 F4 Fu j 0 F0 0 0 F0 0 k R1 F2 R1 R1 F2 R1 Vj Exec Write Issue Comp Result 1 2 3 6 7 8 S1 Vk 9 14 10 15 S2 Qj 10 15 11 16 RS Qk Busy Load1 No Load2 No Load3 Yes Store1 Yes Store2 Yes Store3 No Code: LD MULTD SD SUBI BNEZ Addr Fu Load1 No Load2 No Load3 Yes Store1 Yes Store2 Yes Store3 No Code: LD MULTD SD SUBI BNEZ 64 80 72 [80]*R2 Mult2 64 80 72 [80]*R2 [72]*R2 Reservation Stations: 0 S1 Busy Op Vj Vk No No No No Yes Multd M[72] R(F2) RS Qk Reservation Stations: F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Busy Op No No No Yes Multd No 4 R(F2) Load3 F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8 Register result status Register result status Clock 15 F0 Fu Load3 F2 F4 Mult2 F6 F8 F10 F12 ... F30 Clock 16 F0 Fu Load3 F2 F4 Mult1 F6 F8 F10 F12 ... F30 Mult2 completing. Who is waiting? T2-17 T2-18 Instruction status: 1 1 1 2 2 2 Time LD MULTD SD LD MULTD SD Name Add1 Add2 Add3 M...

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Passed by both HousesNew South WalesFilming Approval Bill 2004ContentsPagePart 1Preliminary1 2 3 Name of Act Commencement Definitions 2 2 2Part 2Filming approvals4 5 6 7 8 Filming approvals for designated areas Application of Environ
Purdue - MA - 222
MA 222Assignment SheetSpring 2008Text: Technical Calculus with Analytic Geometery by Peter Kuhttig, Fourth Edition, Brooks/Cole, 2005. A one-line, scientic calculator with logarithm and exponential functions is required. Graphing calculators or
Allan Hancock College - GBRMPTGBRF - 2006946
2004-2005-2006 The Parliament of the Commonwealth of Australia HOUSE OF REPRESENTATIVESPresented and read a first timeGreat Barrier Reef Marine Park (Protecting the Great Barrier Reef from Oil Drilling and Exploration) Amendment Bill 2006(Mr Alb
Allan Hancock College - ELEC - 4400
Chapter 2: Overview of Power Semiconductor DevicesCopyright 2003 by John Wiley & Sons, Inc.Chapter 2 Power Semiconductor Switches: An Overview2-1Bipolar Junction Transistors (BJT) Used commonly in the past Mostly replaced by MOSFETs an
Allan Hancock College - HIT - 3315
Environment-Passing InterpretersOverview The The The The TheGLoo Perspective F-Calculus Language of Java Services Language of Classes Language of Namespaces and TraitsReferencesMarkus Lumpe, A Lambda Calculus with Forms, SC05, LNC
Allan Hancock College - NPAWCPRP - 2006762
Published in Gazette 29.6.2006 p 2119South AustraliaNational Parks and Wildlife (Yumbarra Conservation ParkMining Rights) Proclamation 2006under section 43 of the National Parks and Wildlife Act 1972Preamble1 The Crown land described in Sched
Allan Hancock College - TSAB - 2007224
2004-2005-2006-2007 The Parliament of the Commonwealth of Australia HOUSE OF REPRESENTATIVESPresented and read a first timeTradex Scheme Amendment Bill 2007 No. , 2007(Industry, Tourism and Resources)A Bill for an Act to amend the Tradex Sche
Allan Hancock College - COMS - 7902
Learning objectivesTo understand:Ethernet LANsLecture 5Copyright 2004 Prentice-Hall Pankos Business Data Networks and Telecommunications, 5th ed. Modified by Jadwiga IndulskaEthernet communication and wiring standards Switches and hubs Etherne
Allan Hancock College - PBLACB - 2002200840
2002 The Parliament of the Commonwealth of Australia THE SENATEPresented and read a first timePlastic Bag Levy (Assessment and Collection) Bill 2002 No. , 2002(Senator Brown)A Bill for an Act to provide for the assessment and collection of a