Modern CS577 Language Processors
Spring 2008 Lecture 6
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R EGISTER A LLOCATION
Task: Manage scarce resources (registers) in environment with imperfect information (static program text) about dynamic program behavior. General aim is to keep frequently-used values in registers as much as possible, to lower memory trafc. Can have a large effect on program performance. Variety of approaches are possible, differing in sophistication and in scope of analysis used. Allocator may be unable to keep every live variable in registers; must then spill variables to memory. Spilling adds new instructions, which often affects the allocation analysis, requiring a new iteration.
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L IVENESS
To determine how long to keep a given variable (or temporary) in a register, need to know the range of instructions for which the variable is live. A variable or temporary is live immediately following an instruction if its current value will be needed in the future (i.e., it will be used again, and it wont be changed before that use). mov 3, %t2 mov %t2, %t3 add %t3, 4, %t4 add %t2, %t4, %t4 st %t4, [a] ! ! ! | | | live after instruction: %t2 %t2 %t3 %t2 %t4 %t4 (nothing)
Its easy to calculate liveness for a consecutive series of instructions without branches, just by working backwards.
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L IVENESS (2)
But if a value can stay in a register over a jump, things get harder. 1 mov 0, %t1 2 L1: add %t1, 1, %t2 3 add %t3, %t2, %t3 4 mul %t2, 2, %t1 5 cmp %t1, 1000 6 bl L1 7 return %t3 ! ! ! ! ! ! ! ! live after instruction: %t1 %t3 %t2 %t3 %t2 %t3 %t1 %t3 %t1 %t3 %t1 %t3 (nothing)
To calculate liveness in this case requires iterative ow analysis and the result is only conservative approximation to true liveness (more later). The live range of a variable is the set of instructions which leave it live. E.g. in 2nd example, live range of %t1 is {1, 4, 5, 6}. Basic idea: If two variables have disjoint live ranges, they can occupy the same physical register. So in both examples, 2 physical registers sufce to allocate all vars.
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L INEAR S CAN A LLOCATION
Using live ranges turns out to be computationally expensive (more later). A simple alternative is to approximate each live range by a live interval. This is the consecutive interval of instructions between the rst and last use of each variable. 1 mov 0, %t1 2 L1: add %t1, 1, %t2 3 add %t3, %t2, %t3 4 mul %t2, 2, %t1 5 cmp %t1, 1000 6 bl L1 7 return %t3 ! ! ! ! ! ! ! ! live after instruction: %t1 %t3 %t2 %t3 %t2 %t3 %t1 %t3 %t1 %t3 %t1 %t3 (nothing)
Live ranges: %t1: 1,4,5,6 %t2:2,3 %t3:1,2,3,4,5,6 Live intervals: %t1: [1,6] %t2: [2,3] %t3: [1,6] (Revised) Basic idea: if two temporaries have non-overlapping live intervals, they can occupy the same physical register.
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L INEAR S CAN A LLOCATION A LGORITHM D ETAILS
1. Compute startpoint[i] and endpoint[i] of live interval i for each variable. Store the intervals in a list in order of increasing start point. 2. Initialize set active := and pool of free registers = all usable registers. 3. For each live interval i in order of increasing start point: (a) For each interval j in active, in order of increasing end point If endpoint[j] startpoint[i] break to step (b). Remove j from active. Add register[j] to pool of free registers. (b) Set register[i] := next register from pool of free registers, and remove it from pool. (If pool is already empty, need to spill.) (c) Add i to active, sorted by increasing end point. A more complicated form of linear scan does take advantage of knowing precise live ranges (expressed as holes in live intervals).
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C OMPUTING L IVENESS
Liveness is another property that is computed using dataow analysis. Classic algorithm is dened on standard CFG (not necessarily in SSA). gen[n] = set of variables used by node n kill[n] = set of variables defined by node n s t <t <M[a] if a t <gen[s] {b,c} {b} {a,b} {a,b} {a1,...an} kill[s] {t} {t} {} {} {t}
b bop c M[b] <- b relop b then L f(a1,...an)
Note that ow equations for this problem are backwards, i.e., data ows in reverse direction from control ow. in[n] = gen[n] (out[n] - kill[n]) out[n] = s succ[n] in[s] In this case we want the xed point solution having the smallest sets.
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L IVENESS E XAMPLE
1 2 3 4 5 6 L: a <b <c <a <if f(c) a 0 a c b < + + * N 1 b 2 goto L
Assume that a,b,c are local variables not used after the termination of this code fragment. We can extract the problem parameters: n 6 5 4 3 2 1 succ[n] 2,6 5 4 3 2 gen[n] c a b b,c a kill[n] a c b a
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S OLVING E XAMPLE
Heres a solution. The control ow equations are solved as usual, but it is more efcient (takes fewer iterations) to ll them in in (roughly) reverse execution order, computing out[] before in[]. Thats because liveness is a backwards ow problem.
iteration 0 out[n] in[n] iteration 1 out[n] in[n] c c a,c a,c b,c b,c b,c b,c a,c a,c c iteration 2 out[n] in[n] c a,c a,c a,c b,c b,c b,c b,c a,c a,c c iteration 3 out[n] in[n] c a,c a,c a,c b,c b,c b,c b,c a,c a,c c
n 6 5 4 3 2 1
Note that this in example, no more than two of {a,b,c} are ever simultaneously live, so two registers will sufce to hold these variables at all times.
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V ISUALIZING R ESULTS
Live ranges a c b c b c a c a c Live Intervals a c a b c a b c a c a c
1 2 3 4 5 6
L:
a <b <c <a <if a f(c)
0 a c b <
+ + * N
1 b 2 goto L
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S TATIC VS . DYNAMIC L IVENESS E XAMPLE
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| | 1 V |---------| | a = b*b | |---------| | | | 2 V |---------| | c = a+b | |---------| | | 3 V |-----------| | c >= b ? | |-----------| / \ / \ 4 V 5 V |-----------| |----------| | return a | | return c | |-----------| |----------|
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S TATIC L IVENESS (2)
Is a live-out at node 2? It depends on whether control ow ever reaches node 4. A smart compiler could answer no. A smarter compiler could answer similar questions about more complicated programs. But no compiler can ever always answer such questions correctly. This is a consequence of the uncomputability of the Halting Problem. So we must be content with static liveness, which talks about paths of control-ow edges, and is just a conservative approximation of dynamic liveness, which talks about actual execution paths.
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Coloring Register Interference Graphs
More general mechanism for doing register allocation is by translation to graph coloring. Build a register interference graph, which has - a node for each logical register. - an edge between two nodes if the corresponding registers are simultaneously live. Attempt to color the nodes of the graph so that no two nodes connected by an edge have the same color. (Like coloring a map, where nodes=countries and edges connect countries with a common bord...