465, ECE Spring 2009, Instructor: Prof. Shantanu Dutt
Project 1 : Due Tue, March 31
1 Goal
In this project you will solve a non-trivial design problem explicitly using the divide-and-conquer (D&C) approach. The main reason for using the D&C approach is the ease of the design process and cleanness of the resulting design. A typical by-product is a design that also uses less hardware and may be faster. Furthermore, the actual design will be implemented and simulated with Quartus II's schematic capture tool using a hierarchical approach--design and simulate smaller components, use them to design and simulate larger components and so forth until the entire design is completed and simulated.
2 Design Problem
You need to design a 32-bit combinational circuit that is a multiple-of-5 (MO5) detector. The output of this circuit should be 1 if the 32-bit input number is a multiple of 5, and should be 0 otherwise. Assume that the input number is an unsigned (non-negative) number. Hints: (1) Whether a number checking if : the formulation:
is a multiple of , can be determined by obtaining the remainder and implies that is a multiple of , otherwise it is not. The remainder is defined in
where is some integer and . In other words, is the remainer of the division of by , though you should not be obtaining the remainder by performing a division first, as division is a complex process. (2) In order to perform the D&C breakup of the design, as well as determine the "stitch-up" unit, you can use the following properties of the remainder function:
(3) You need not go down to a 1-bit MO5 detector in your D&C tree, just because we went down to a 1-bit comparator for the comparator's D&C design (D&C lecture notes). In fact, a 1-bit MO5 detector is an useless circuit to have, since its ouput will always be 0 (no 1-bit number can be a multiple of 5). Thus the # of bits you need to process at the leaf of your D&C tree for a particular design has to make sense for that design. You need to determine what is for the MO5 detector.
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Explicitly show the following in your design process: 1. The D&C breakup of the problem. 2. The "stitch-up" logic required at each level of the D&C tree. 3. The design of the basic/smallest unit(s) (sometimes you can have more than one type of basic unit as, in the comparator design--D&C notes, and sometimes only one type of basic unit, as in the ripplecarry addern--D&C notes) resulting from the D&C breakup. This design process should include the following for each type of basic unit: TT, QM-based (use multi-function QM if a basic unit has more than one output bit and they are functions of the same set of input variables) final logic expressions for each output bit, and the gate-level design (with gate sharing, if any) using AND/OR/NOT gates. 4. The design of the entire 32-bit MO5 detector using basic units as components (similar to the design of the 8-bit comparator in the D&C lecture notes in which two types of basic units were used, a 1-bit comparator and a 2:1 Mux). We define a basic unit as follows: Each type of component at the leaves (bottom part) of the D&C tree is a basic unit (the comparator had only one type of component, a 1-bit comparator, at the leaves), and each type of component at the stitch-up units in the tree is a basic unit (the comparator had only one type of component, a 2:1 Mux, as the stitch-up unit). 5. Assuming a -input gate has a delay of units, determine the delay of your 32-bit MO5 circuit, showing clearly the critical path (max delay path) of your circuit. Specify each delay component in the critical path for (see example the critical path delay calculation for the 8-bit tree comparator in the D&C lecture notes). Writing down the final delay number is not enough; we need to know clearly how you arrived at your answer.
6. Determine the number of units of each basic type, used in the 32-bit MO5 circuit and from there, obtain the total number of basic units used (across all types). Extend the above calculations for your MO5 circuit to corresponding expressions for an -bit MO5 circuit, where assume is a power of 2. For example, the -bit tree comparator circuit discussed in class has two basic components: 1-bit comparator and 2:1 Mux. It has 1-bit comparators and 2:1 Mux'es, for a total of basic components. 1400 points
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Extend the above delay calculation to a delay expression for an -bit MO5 circuit, where assume a power of 2.
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3 Implementation and Simulation using Quartus II
You are required to implement and simulate your gate-based design obtained above using the Quartus CAD software as specified below: 800 points 1. The project is to be done in groups of 2; you need to report your teams to the TA by Thurs, 03/12/09. 2. Choose the schematic capture tool in Quartus to specify your design. 3. Device family to be used for the project is Cyclone which is selected by default in Quartus. 4. Design the basic unit(s) using gates, simulate it/them for correctness (generate your own inputs for this simulation; test exhaustively, i.e., using all possible input combinations), save it/them. 5. Using the above saved design(s) and other in-built library components (if any needed) like gates and Mux'es, design the 32-bit MO5 detector. 6. Perform simulations of the 32-bit MO5 circuit based on the input file or VHDL test bench provided by the TA. 7. Perform timing analysis of a 4-bit, 8-bit, 16-bit and the final 32-bit MO5 circuit, and plot this delay (Y axis) versus the number of input bits (X axis). Include this plot in your report and comment on what this empirical data says about the delay of a general -bit MO5 circuit, for a power of 2. Also comment on whether this plot is consistent, in terms of order notation, with the analytical delay expression you obtained earlier for an -bit MO5. 8. Count the number of total gate inputs (with...