Memory Virtual and Demand Paging
Virtual Memory Illustrated
executable file
header text idata data wdata symbol table, etc. program sections
virtual memory (big)
text data BSS user stack args/env
kernel
physical memory (small)
backing storage
pageout/eviction
page fetch
process segments
physical page frames
virtual-to-physical translations
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Virtual Address Translation
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virtual address VPN
Example: typical 32-bit architecture with 8KB pages. Virtual address translation maps a virtual page number (VPN) to a physical page frame number (PFN): the rest is easy.
Deliver exception to OS if translation is not valid and accessible in requested mode. physical address
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0
00
offset
address translation
{
PFN
+
offset
Role of MMU Hardware and OS
VM address translation must be very cheap (on average).
Every instruction includes one or two memory references.
(including the reference to the instruction itself)
VM translation is supported in hardware by a Memory Management Unit or MMU.
The addressing model is defined by the CPU architecture. The MMU itself is an integral part of the CPU.
The role of the OS is to install the virtual-physical mapping and intervene if the MMU reports that it cannot complete the translation.
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The Translation Lookaside Buffer (TLB)
An on-chip hardware translation buffer (TB or TLB) caches recently used virtual-physical translations (ptes).
Alpha 21164: 48-entry fully associative TLB.
A CPU pipeline stage probes the TLB to complete over 99% of address translations in a single cycle. Like other memory system caches, replacement of TLB entries is simple and controlled by hardware.
e.g., Not Last Used
If a translation misses in the TLB, the entry must be fetched by accessing the page table(s) in memory.
cost: 10-200 cycles
A View of the MMU and the TLB
CPU
TLB
Control MMU
Memory
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Completing a VM Reference
start here
probe page table load TLB
MMU
access physical memory
probe TLB
access valid?
raise exception
load TLB
zero-fill
OS
allocate frame page fault? signal process
fetch from disk
page on disk?
The OS Directs the MMU
The OS controls the operation of the MMU to select:
(1) the subset of possible virtual addresses that are valid for each process (the process virtual address space); (2) the physical translations for those virtual addresses; (3) the modes of permissible access to those virtual addresses;
read/write/execute
(4) the specific set of translations in effect at any instant.
need rapid context switch from one address space to another
MMU completes a reference only if the OS says its OK.
MMU raises an exception if the reference is not OK.
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Alpha Page Tables (Forward Mapped)
21 seg 0/1 base + + + L1 10 L2 10 L3 PO 10 13
sparse 64-bit address space (43 bits in 21064 and 21164)
offset at each level is determined by specific bits in VA
PFN
three-level page table (forward-mapped)
A Page Table Entry (PTE)
This is (roughly) what a MIPS/Nachos page table entry (pte) looks like.
valid bit: OS uses this bit to tell the MMU if the translation is valid. write-enable: OS touches this to enable or disable write access for this mapping.
PFN
dirty bit: MMU sets this when a store is completed to the page (page is modified).
reference bit: MMU sets this when a reference is made through the mapping.
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Paged Virtual Memory
Like the file system, the paging system manages physical memory as a page cache over a larger virtual store.
Pages not resident in memory can be zero-filled or found somewhere on secondary storage. MMU and TLB handle references to resident pages. A reference to a non-resident page causes the MMU to raise a page fault exception to the OS kernel.
Page fault handler validates access and services the fault. Returns by restarting the faulting instruction.
Page faults are (mostly) transparent to the interrupted code.
Care and Feeding of TLBs
The OS kernel carries out its memory management functions by issuing privileged operations on the MMU. Choice 1: OS maintains page tables examined by the MMU.
MMU loads TLB autonomously on each TLB miss page table format is defined by the architecture OS loads page table bases and lengths into privileged memory management registers on each context switch.
Choice 2: OS controls the TLB directly.
MMU raises exception if the needed pte is not in the TLB. Exception handler loads the missing pte by reading data structures in memory (software-loaded TLB).
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Where Pages Come From
file volume with executable programs
text data BSS user stack args/env
Modified (dirty) pages are pushed to backing store (swap) on eviction.
Fetches for clean text or data are typically fill-from-file.
kernel
Paged-out pages are fetched from backing store when needed.
Initial references to user stack and BSS are satisfied by zero-fill on demand.
Demand Paging and Page Faults
OS may leave some virtual-physical translations unspecified.
mark the pte for a virtual page as invalid
If an unmapped page is referenced, the machine passes control to the kernel exception handler (page fault).
passes faulting virtual address and attempted access mode
Handler initializes a page frame, updates pte, restarts.
If and a disk access is required, the OS may switch to another process after initiating the I/O. Page faults are delivered at IPL 0, just like a system call trap. Fault handler executes in context of faulted process, blocks on a semaphore or condition variable awaiting I/O completion.
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Issues for Paged Memory Management
The OS tries to minimize page fault costs incurred by all processes, balancing fairness, system throughput, etc.
(1) fetch policy: When are pages brought into memory?
prepaging: reduce page faults by bring pages in before needed clustering: reduce seeks on backing storage
(2) replacement policy: How and when does the system select victim pages to be evicted/discarded from memory? (3) backing storage policy:
Where does the system store evicted pages? When is the backing storage allocated? When does the system write modified pages to backing store?
Where Pages Come From
file volume with executable programs
text data BSS user stack args/env
Modified (dirty) pages are pushed to backing store (swap) on eviction.
Fetches for clean text or data are typically fill-from-file.
kernel
Paged-out pages are fetched from backing store when needed.
Initial references to user stack and BSS are satisfied by zero-fill on demand.
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Questions for Paged Virtual Memory
1. How do we prevent users from accessing protected data? 2. If a page is in memory, how do we find it?
Address translation must be fast.
3. If a page is not in memory, how do we find it? 4. When is a page brought into memory? 5. If a page is brought into memory, where do we put it? 6. If a page is evicted from memory, where do we put it? 7. How do we decide which pages to evict from memory?
Page replacement policy should minimize overall I/O.
VM Internals: Mach/BSD Example
address space (task)
start, len, prot start, len, prot start, len, prot start, len, prot
vm_map lookup enter
memory objects
putpage getpage
pmap pmap_enter() pmap_remove() One pmap (physical map) per virtual address space.
pmap_page_protect pmap_clear_modify pmap_is_modified pmap_is_referenced pmap_clear_reference
page cells (vm_page_t) array indexed by PFN
page table
system-wide phys-virtual map
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Mapped Files
With appropriate support, virtual memory is a useful basis for accessing file storage (vnodes).
bind file to a region of virtual memory with mmap syscall.
e.g., start address x virtual address x+n maps to offset n of the file
several advantages over stream file access
uniform access for files and memory (just use pointers) performance: zero-copy reads and writes for low-overhead I/O but: program has less control over data movement style does not generalize to pipes, sockets, terminal I/O, etc.
Using File Mapping to Build a VAS
executable image header text idata data wdata
symbol table relocation records
Memory-mapped files are used internally for demand-paged text and initialized static data.
text data text data segments
sections
header text idata data wdata
symbol table relocation records
loader
BSS user stack args/env
kernel u-area
library (DLL)
BSS and user stack are anonymou...