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If 1. the following scheme is used to represent real numbers: computer A: computer B: 1 bit sign, 7 bits mantissa, 4 bits exponent 1 bit sign, 8 bits mantissa, 3 bits exponent
Then computer A can represent real numbers with __less___ precision and __more___ range than computer B. 2. This gate is equivalent to ___AND__ gate. 3. If A XOR B = C, then: a) A XOR C = B b) B XOR C = A c) A XOR B XOR C = 0
d) All of the above YES e) None of the above
4. How many Boolean functions can be made out of 3 variables? We can make 2^3 3-input, one AND gate functions. So, then we can combine this number to make 2 ^ (2^3) Boolean functions of 3 variables. i.e.: out of variables a,b and c, we can make a'b'c', a'b'c, a'bc', ..., abc (so this 2^3 pieces). Then, out of those 2^3 pieces, we can make functions: F1 = a'b'c' + a'bc' F2 = a'b'c' + a'bc' + a'bc' ... F256 = a'b'c' + a'bc' + ... + a b c etc, there are 2 ^ (2^3) functions total. 5. Remove all hazards from xy + zx'. Add term: xy + zx' + yz 6. Convert x'yz' + x'y'z + x(y+z) into a product of sums. Many ways to go about this. A simple, fast way: work with 0's from the truth table, or circle 0's in K map. xyz O 000 0 001 1 010 1 011 0 100 0 101 1 110 1 111 1 O = (x + y + z)(x+y'+z')(x'+y + z) Check: O = (y+z)(x+x')(x+y'+z') = (y+z)(x+y'+z')
7. Four 256 x 8 PROM chips are used to produce a total capacity of 1024 x 8. How many address bus lines are required?
Since there are 4 chips, we need 2 bits to represent the "area code" i.e. which chip it is. Then each chip must use 8 bit-address in order to be able to access all 256 locations on the chip. So, the total of number bits is 10. 8. If 2 lines go into an X address decoder and 2 lines go into a Y address decoder, than this 2dimensional addressing scheme can access at most __4*4 = 16____ values. X can address 2^2 addresses, and Y can address 2^2 addresses. If the final address is XY, then we can access 16 addresses. 9. Consider the following set of micro-operations: a) MAR = PC b) IR = MDR, PC ++ c) Decoder = IR d) ABUS = R1, BBUS = R2 e) ALU = R1+R2 f) CBUS = ALU g) R1 = CBUS
The operations that make up the entire fetch phase of the instruction cycle include: a, b and c. Unfortunately, the GRE test does not provide the acronyms. The term "decoder" is used for the circuitry in CPU which has to recognize which instruction is referred to by the binary instruction code that was fetched from the memory. (This is true but is a play on words, because we are not using a "decoder chip" but are performing a deciphering, i.e. decoding, function. Our book uses this terminology it on p.54.) How to figure it out without knowing what it really means: From our book we have that: IP is put onto address register going into memory Memory has to put out the contents of that address (which contains the instruction code) onto the data bus IP ++ CPU has to figure out which instruction it is, and then the execute cycle may start, because CPU might have to go back into the memory to get the data. So, a, b and c seem like good choices. e,f and g are definitely related to the execution cycle and ALU. d can be eliminated because it also cannot be a part of fetch cycle to put something out on the bus again.

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