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lecture9_Virtex_devices_3
Course: ECE 297, Fall 2009School: George Mason
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to Introduction Xilinx Virtex FPGA devices ECE 297 - Reconfigurable Architectures for Computer Security Outline Introduction Features of Xilinx Virtex FPGAs Architecture overview CLB Routing IOB Block SelectRAM Additional components ECE 297 - Reconfigurable Architectures for Computer Security 2 Outline Introduction Features of Xilinx Virtex FPGAs Architecture overview CLB Routing IOB Block...
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to Introduction Xilinx Virtex FPGA devices
ECE 297 - Reconfigurable Architectures for Computer Security
Outline
Introduction Features of Xilinx Virtex FPGAs Architecture overview CLB Routing IOB Block SelectRAM Additional components
ECE 297 - Reconfigurable Architectures for Computer Security 2
Outline
Introduction Features of Xilinx Virtex FPGAs Architecture overview CLB Routing IOB Block SelectRAM Additional components
ECE 297 - Reconfigurable Architectures for Computer Security 3
1
World of ASICs
ASIC
(Application Specific Integrated Circuit)
Full-Custom
(ordered by users)
Semi-Custom
(designed by users)
User Programmable
PLD
FPGA
PAL
PLA
MAX
TLU
(Table Look-Up)
MUX
Gates
4
ECE 297 - Reconfigurable Architectures for Computer Security
Which Way to Go?
Custom ASICs FPGAs
Off-the-shelf High performance Low development costs Low power Short time to the market Low cost (but only in high volumes) Reconfigurability
ECE 297 - Reconfigurable Architectures for Computer Security
5
Other FPGA Advantages
Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower
Mistakes not detected at design time have large impact on development time and cost FPGAs are perfect for rapid prototyping of digital circuits
Easy upgrades like in case of software Unique applications
reconfigurable computing
ECE 297 - Reconfigurable Architectures for Computer Security 6
2
What is FPGA?
FPGA Field Programmable Gate Array
Originally a large array of gates with programmable interconnections
Now much more complex arrays of various components
ECE 297 - Reconfigurable Architectures for Computer Security
7
Outline
Introduction Features of Xilinx Virtex FPGAs Architecture overview CLB Routing IOB Block SelectRAM Additional components
ECE 297 - Reconfigurable Architectures for Computer Security 8
Xilinx Virtex 2.5V (1)
Densities from 50k to 1M gates System performance up to 200MHz including I/O 66MHz PCI compliant Support 16 highperformance interface standards Built-in clock management circuitry Hierarchical memory system Flexible architecture
fast carry chain multiplier support cascade chain for wideinput functions abundant registers/latches internal 3-state bussing IEEE 1149.1 boundaryscan
SRAM-based in-system configuration 0.22m 5-layer metal process
9
ECE 297 - Reconfigurable Architectures for Computer Security
3
Xilinx Virtex 2.5V (2)
Device CLB Array Logic cells LUT 16x24 20x30 24x36 28x42 32x48 40x60 48x72 56x84 64x96 1,728 2,700 3,888 5,292 6,912 10,800 15,552 21,168 27,684 Maximum Available I/O 180 180 260 284 316 404 512 512 512 BlockRAM Distributed (4kb each) RAM bits 8 10 12 14 16 20 24 28 32 24,576 38,400 55,296 75,264 98,304 153,600 221,184 301,056 393,216
XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
ECE 297 - Reconfigurable Architectures for Computer Security
10
Outline
Introduction Features of Xilinx Virtex FPGAs Architecture overview CLB Routing IOB Block SelectRAM Additional components
ECE 297 - Reconfigurable Architectures for Computer Security 11
Virtex 2.5V Architecture (1)
DLL
Block RAMs
ECE 297 - Reconfigurable Architectures for Computer Security
Block RAMs
I/O Block Configurable Logic Block
12
4
Virtex 2.5V Architecture (2)
CLBs provide the functional elements for constructing logic IOBs provide interface between the package pins and the CLBs Block RAMs dedicated dual-port memories of 4096 bits DLLs for clock-distribution delay compensation
ECE 297 - Reconfigurable Architectures for Computer Security 13
Outline
Introduction Features of Xilinx Virtex FPGAs Architecture overview CLB Routing IOB Block SelectRAM Additional components
ECE 297 - Reconfigurable Architectures for Computer Security 14
COUT
CLB Slice
G4 G3 G2 G1 A4 A3 A2 A1 WS DI LUT ROM RAM D
G1 1 0
YB
1 G 0 1
F6 GXOR G
Y
D CE CK
FF LATCH Q YQ
INIT
PROD
REV XB
0 1 1 0
BY
nBY BY 1 0 BY BX DG DF
A5 WE CLK
WSG 1 WSF G 0 1
F5
F5in
BX F5 GXOR G
CIN F4 F3 F2 F1 A4 A3 A2 A1 LUT ROM RAM WS DI D
CIN
X
D CE CK
FF LATCH Q XQ
INIT
PROD F1 1 0 nBX BX 1 0
REV
BX
CE
nCE CE 1 0
CLK
SR
nSR SR 1 0
ECE 297 - Reconfigurable Architectures for Computer Security
15
5
LUT Functionality
x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 y 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 x1 x2 x3 x4
LUT
y
x1 x2 x3 x4
x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
x3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
x4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
y 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0
x1 x2 y
Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs Capacity limited by number of inputs, not complexity Can be configured as LUT, ROM or RAM
y
ECE 297 - Reconfigurable Architectures for Computer Security
16
5-Input Functions on LUTs
One CLB Slice can implement any function of 5 inputs Logic function is partitioned between two LUTs F5 multiplexer selects LUT
A4 A3 A2 A1 WS DI
0
LUT ROM RAM
D
F5
F5 GXOR G
F4 F3 F2 F1 BX
A4 A3 A2 A1
WS
DI D
1
X
LUT ROM RAM
nBX BX 1 0
ECE 297 - Reconfigurable Architectures for Computer Security
17
6-Input Functions on LUTs
A4 A3 A2 A1 WS DI
0
LUT ROM RAM
D
F5 F5
A4 A3 A2 A1
WS
DI D
1
LUT ROM RAM
nBX BX 1 0
A4 A3 A2 A1
LUT ROM RAM
D
WS
DI
0
F5 F6
1 0 F6 GXOR G
One CLB (two adjacent Slices) can implement any 6-input function Logic function is partitioned among four LUTs Dedicated multiplexers F5 and F6 select LUT
Y
F4 F3 F2 F1 BX
A4 A3 A2 A1
WS
DI D
1
LUT ROM RAM
nBX BX 1 0
F5in BY
nBX BX 1 0
ECE 297 - Reconfigurable Architectures for Computer Security
18
6
RAM 16x2 on LUT
G4 G3 G2 G1 A4 A3 A2 A1
RAM 16x1
WS
D
F6 GXOR G
Y
DI
BY
nBY BY 1 0
BY BX
DG DF
A5 WE CLK
WSG WSF F5 GXOR G
X
Each LUT can implement a 16x1 RAM Inputs to RAMs are through BY and BX Both RAMs share CLK and WE
F4 F3 F2 F1 BX
nBX BX 1 0
A4 A3 A2 A1
WS
DI D
RAM 16x1
CLK
SR
nSR SR 1 0
ECE 297 - Reconfigurable Architectures for Computer Security
19
RAM 32x1 on LUTs
G4 G3 G2 G1 A4 A3 A2 A1
RAM 16x1
WS
D
DI
0 1
BY
nBY BY 1 0 BY BX DG DF
A5 WE CLK
WSG WSF F5 GXOR G
Both LUTs share inputs Input BX acts as A5 Input BY is an input to the RAM
X
A4 A3 A2 A1 BX
nBX BX 1 0
WS
DI D
RAM 16x1
CLK
SR
nSR SR 1 0
ECE 297 - Reconfigurable Architectures for Computer Security
20
RAMD 16x1 (Dual-Port)
G4 G3 G2 G1 A4 A3 A2 A1 WS DI
RAMD
D
F6 GXOR G
Y
BY
nBY BY 1 0 BY BX DG DF
One port used for writing and reading, other only for reading Writing to both memories simultaneously
X
A5 WE CLK
WSG WSF F5 GXOR G
F4 F3 F2 F1 CLK
A4 A3 A2 A1
WS
DI D
RAMD
SR
nSR SR 1 0
ECE 297 - Reconfigurable Architectures for Computer Security
21
7
COUT
Carry Chain
G4 G3 G2 G1 A4 A3 A2 A1 WS DI LUT ROM RAM D
YB
1 G 0 1
F6 GXOR G
Y
PROD G1 1 0
1 G 0 1
BX
F5 GXOR G
X
CIN F4 F3 F2 F1 A4 A3 A2 A1 LUT ROM RAM WS DI D
CIN
PROD F1 1
BX
0 nBX BX 1 0
Carry chain connects CLB Slices in the same column Chain is unidirectional Can connect only as many CLB Slices as there are rows in the device (64 in XCV1000) Very useful for implementing arithmetic logic
ECE 297 - Reconfigurable Architectures for Computer Security
22
Ripple-Carry Adder
Full adder implemented using propagate/generate idea Carry is propagated from the previous stage to the next stage only when it is necessary i.e. A and B have different values. Function p decides if carry needs to be propagated Function g generates carry when carry does not get propagated.
Cout
0
1
S A B A2 A1 D p
XOR
g Cin
ECE 297 - Reconfigurable Architectures for Computer Security
23
Ripple-Carry Adder on CLB Slice
COUT YB
1 G 0 1 F6 GXOR G
Y
A4 A3 G2 G1 A2 A1 D
XOR
WS DI
PROD G1 1 0
1 G 0 1
BX
F5 GXOR G
X
CIN A4 A3 F2 F1 A2 A1 WS DI D
CIN
XOR
PROD F1 1
BX
0 nBX BX 1 0
ECE 297 - Reconfigurable Architectures for Computer Security
24
8
Array Multiplier
Implementation of array multiplier requires addition of multiple products Can be implemented on full adders with inputs from AND gates computing products
Cout
0
1
A0 B1 A1 B0
S1 D p
XOR
g Cin
ECE 297 - Reconfigurable Architectures for Computer Security
25
Array Multiplier on CLB Slice
COUT YB
1 G 0 1 F6 GXOR G
Y
G4 G3 G2 G1
A4 A3 A2 A1 WS DI D
PROD G1 1 0
1 G 0 1
BX
CIN F4 F3 F2 F1 A4 A3 A2 A1 WS DI D
CIN
F5 GXOR G
X
PROD F1 1
BX
0 nBX BX 1 0
ECE 297 - Reconfigurable Architectures for Computer Security
26
Outline
Features Introduction of Xilinx Virtex FPGAs Architecture overview CLB Routing IOB Block SelectRAM Additional components
ECE 297 - Reconfigurable Architectures for Computer Security 27
9
Routing Between CLBs (1)
TBUF OE Global SR CE CLK
Global CLK nets 4 TBUF lines 4 Connect any four adjacent CLBs 12 4 4 4 4 4 4 6 6 1 6 6 4 4 4 4 4 4
Universal vertical lines connecting three big switching matrices in a distance of three.
8
Universal vertical lines connecting three big switching matrices in a distance of three.
Long vertical lines across the chip connecting switching matrices in a distance of six.
Y YQ YB X XQ XB Y YQ YB X XQ XB
2
F5 cout cin
CLB Slice
G BY F 4 BX CLK CE SR
F5
CLB Slice
G 4 BY F 4 BX CLK CE SR
cout cin
4
4
2
2
4 2 6 6 6 6 2
24 2
~100
8
24
24
3 3
24 12 12 12 12 12 12
2
Universal horizontal lines connecting three big switching matrices in a distance of three. Long horizontal lines across the chip connecting switching matrices in a distance of six.
12
ECE 297 - Reconfigurable Architectures for Computer Security
28
Routing Between CLBs (2)
Routing resources organized into a hierarchy of nets
carry chain directly connects adjacent CLB Slices in the same column 2 dedicated nets connect adjacent CLB Slices in the same row 24 nets in each direction connect adjacent routing matrices 48 vertical nets and 72 horizontal nets connect every 3rd routing matrix 12 vertical and 12 horizontal lines connect every 6th routing matrix across the entire chip
Dedicated CLK, RST, CE and 3-state nets
ECE 297 - Reconfigurable Architectures for Computer Security 29
Routing Between CLBs (3)
TBUF O E TBUF O E G loba l SR G loba l SR CE CL K
Glob al CLK nets 4 T BUF lines 4 Conne ct any f our adjacen t CLBs
CE
CL K
Glob al CLK nets 4 T BUF li es n 4 Conne ct any f our a djacen t CLBs
12
4 4
4 4
4 4
6
6 1
6
6
4 4
4 4
4 4
12
4 4
4 4
4 4
6
6 1
6
6
4 4
4 4
4 4
Un ive rsa l ve rt ical line s co nn ec ting th re e big sw itch ing matr ice s in a dis tan ce of th re e.
8
U nive rs al v er tica l line s c on ne ctin g t hr ee big s witch ing mat rice s in a d ista nce o f th re e.
Un ive rsa l ve rt ical li es n co nn ec ting th re e b ig sw itchin g ma tr ices in a dis tan ce of th re e.
8
U nive rs al v er tica l line s c on ne ctin g t hr ee big s witch ing matr ice s in a d ista nce o f th re e.
L on g ver tica l lin es a cr oss th e ch ip c on ne ctin g sw itch ing ma trice s in a d ista nc e o f s ix.
Y YQ YB X XQ XB Y YQ YB X XQ XB
2
L on g v er tica l line s a cr oss the ch ip c on nec ting sw itch ing mat rice s in a d ista nce o f six .
Y YQ YB X XQ XB Y YQ YB X XQ XB
2
F5 cou t cin
F5
CLB Slice
G BY F BX CLK CE SR
F5
CLB Slice
G BY F BX CLK CE SR
co ut cin
c ou t c in
CLB Slice
G BY F BX CLK CE SR
F5
CLB Slice
G BY F BX CLK CE SR
co ut cin
4
4
4
4
4 2 2
4
4
4
4
4 2
2
4 2 6 6 6 6 2 2 6 6
4 2 6 6
24 2
~10 0
8
24 2
~10 0
8
24
24
24
24
3 3
3 3
24 12 12 12 12 12 12
2
24 12 12 12 12 12 12
2
U nive rs al h or izon ta l line s c on nec ting th re e big s witch ing matr ice s in a d istan ce of th re e. L on g ho rizo nt al lin es a cr oss th e c hip c on ne ctin g s witch ing ma tric es in a d ista nc e o f s ix.
Un ive rsa l h or izon ta l line s co nn ec ting th re e big sw itch ing matr ice s in a dis tan ce of th re e. L on g h or izo nta l lin es a cr oss the ch ip c on nec ting sw itch ing mat rice s in a d ista nce o f six .
12
12
TBUF O E
TBUF O E
Glo ba l SR
Glo ba l SR
CE
CL K
Glob al CLK nets 4 T BUF lines 4 Conne ct any f our adjacen t CLBs
CE
CL K
Glob al CLK nets 4 T BUF li es n 4 Conne ct any f our a djacen t CLBs
12
4 4
4 4
4 4
6
6 1
6
6
4 4
4 4
4 4
12
4 4
4 4
4 4
6
6 1
6
6
4 4
4 4
4 4
Un ive rsa l ve rt ical line s co nn ec ting th re e big sw itch ing matr ice s in a dis tan ce of th re e.
8
U nive rs al v er tica l line s c on ne ctin g t hr ee big s witch ing mat rice s in a d ista nce o f th re e.
Un ive rsa l ve rt ical li es n co nn ec ting th re e b ig sw itchin g ma tr ices in a dis tan ce of th re e.
8
U nive rs al v er tica l line s c on ne ctin g t hr ee big s witch ing matr ice s in a d ista nce o f th re e.
L on g ver tica l lin es a cr oss th e ch ip c on ne ctin g sw itch ing ma trice s in a d ista nc e o f s ix.
Y YQ YB X XQ XB Y YQ YB X XQ XB
2
L on g v er tica l line s a cr oss the ch ip c on nec ting sw itch ing mat rice s in a d ista nce o f six .
Y YQ YB X XQ XB Y YQ YB X XQ XB
2
F5 cou t cin
F5
CLB Slice
G BY F BX CLK CE SR
F5
CLB Slice
G BY F BX CLK CE SR
co ut cin
c ou t c in
CLB Slice
G BY F BX CLK CE SR
F5
CLB Slice
G BY F BX CLK CE SR
co ut cin
4
4
4
4
4 2 2
4
4
4
4
4 2
2
4 2 6 6 6 6 2 2 6 6
4 2 6 6
24 2
~10 0
8
24 2
~10 0
8
24
24
24
24
3 3
3 3
24 12 12 12 12 12 12
2
24 12 12 12 12 12 12
2
U nive rs al h or izon ta l line s c on nec ting th re e big s witch ing matr ice s in a d istan ce of th re e. L on g ho rizo nt al lin es a cr oss th e c hip c on ne ctin g s witch ing ma tric es in a d ista nc e o f s ix.
Un ive rsa l h or izon ta l line s co nn e...
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Information about SMAM 314-Dr. Grubers Section Instructor: Dr. M. Gruber office 08-3250 Phone 475-2541 email mjgsma@rit.edu Web page http:/www.rit.edu/~mjgsma/smam314winter02/hw.html Textbook:Basic Engineering Data Data Collection and Analysis -Steph
RIT - SMAM - 351
SMAM 351 HW#6 Due 4/16/04 1.Consider the continuous function k ,x 2 x5 A. Find k so that f(x) is a probability density function. f ( x )=2k k k dx = lim - 4 = =1 5 A 4x x 64 2Ak = 64B. Find (1)P(X<4) 64 16 16 15 P(X < 4) = 2 5 dx = - 4
RIT - SMAM - 351
Exam 2d Solution1. 7.5k = 60 k=8 1 1 63 = 82 642. A. P(X 7) = 1 P(X 6) = 1 .4862 = .5138 B. P(X 2) = .2616 C. = 10(.65) = 6.5 = 6.5(.35) = 1.508 D. p=.05 P(X 1) = 1 P(X = 0) = 1 .599 = .4013. A. P(X 2) = .9595 =3 B. P(X = 6) = P(X 6) P(
RIT - SMAM - 351
SMAM 351Quiz 6 dName_1. The exponential probability density function below of random variable T represents the time until a machine part fails in years. .2e -.2t g(t) = 0 t>0 elsewhereA. What is the mean time before failure? (2 points) 1/.2 =
Cornell - CS - 172
CS/ENGRI 172, Fall 2003: Computation, Information, and Intelligence 10/3/03: Turing Machine Computability Turing Machine Universality Data/Program duality for Turing machines: Turing machine control tables can be written on a Turing machines tape as
Cornell - CS - 412
Variables vs. Registers/MemoryCS412/CS413 Introduction to Compilers Tim Teitelbaum Lecture 33: Register Allocation 18 Apr 07 Difference between IR and assembly code: IR (and abstract assembly) manipulate data in local and temporary variables Asse
Cornell - GEO - 326
326 - S TRUCTURAL G EOLOGY JOINTS "The study of geologic history of fractures is notoriously difficult." Four general categories of observations: 1) 2) 3) 4) the distribution and geometry of the fracture system the surface features of the fractures t
Virginia Tech - ETD - 03102001
Cornell - CS - 172
Computation, Information, and Intelligence (ENGRI/CS/INFO/COGST 172), Spring 2007 5/2/07: Lecture 41 aid A zero-knowledge protocol; a look back before the end Topics: a zero-knowledge protocol (really, this time I swear); course review in preparatio
Virginia Tech - CS - 1044
CS 1044 Program 3Fall 2003Putting the basics together:Billing for VT Long DistanceIt's finally time to write a complete program. This project will use many of the C+ features that were illustrated in the source code you were given for the fir
Cornell - M - 171
CLT Simulation NotesStart by realizing 500 trials from a uniform [0,1] distribution. (Mean=.5, Standard Deviation=.sqrt(1/12)=.289) Now square each value to get the simulation of a new distribution. (Mean=.333, Standard Deviation=.298) Co
Texas A&M - MEEN - 651
MEEN 364 Vijay 9/13/01Introduction to SimulinkSimulink is a software package for modeling, simulating, and analyzing dynamical systems. It supports linear and nonlinear systems, modeled in continuous time, sampled time, or a hybrid of the two. Sys
Maryland - PHIL - 100
Philosophy 100 Fall 2006 Discussion Section 0207 Jimemez 3203: 1:00pm-1:50pmTeaching Assistant: Contact Information:William Michael Kallfelz (301)405(301)405-5841 wkallfel@umd.edu1 http:/www.glue.umd.edu/~wkallfel/index.html1120C Skinner Buildi
Texas A&M - CVEN - 302
Chapter 2MATLAB FundamentalsMATLABMatrix LaboratoryProblem-Solving Methodologys s s s s s sState the problem clearly Describe the Input/Output (I/O) Work the problem by hand Algorithm - Numerical Method Develop a MATLAB Solution Debugging an
Texas A&M - PHYS - 205
Type B Teacher Quality Grant: Physics Participant Roster# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Last Name Bierman Brevard Caballero Cantrell Carandang Castillo Denny Dimaliwat Doffing Dudley-Scott Dwived
Texas A&M - PHYS - 205
Session 2 March 19, 2005Promoting Excellence in Physics TeachingTHECB Type B Teacher Quality Professional Development Spring Branch ISD Science Center Agenda8:00 AM 8:30 AM 8:45 AM 9:45 AM 10:30 AM 11:00 AM 11:15 AM 12:00 PM 12:30 PM 1:30 PM 2:15
Texas A&M - PHYS - 205
ACCELERATION OF FALLING OBJECTS: VIDEO ANALYSISIn this exercise, you will use the VideoPoint2.5 video analysis software program to investigate the motion of a falling object that has minimal air resistance (a small basketball) and the motion of anot
Texas A&M - PHYS - 205
Session 3 April 9, 2005Promoting Excellence in Physics TeachingTHECB Type B Teacher Quality Professional Development Spring Branch ISD Science Center Agenda8:00 AM 8:30 AM 8:45 AM 9:15 AM 10:30 AM 11:30 AM 12:00 PM 12:30 PM 1:30 PM 2:45 PM 3:00 P
Texas A&M - PHYS - 205
Session 15 June 17, 2005Promoting Excellence in Physics TeachingTHECB Type B Teacher Quality Professional Development Spring Branch ISD Science Center Agenda8:00 AM 8:30 AM 8:45 AM 10:00 AM 11:30 AM 12:00 PM 12:30 PM 3:45 PM 4:00 PM Welcome, Revi
Texas A&M - PHYS - 205
Session 9 June 9, 2005Promoting Excellence in Physics TeachingTHECB Type B Teacher Quality Professional Development Spring Branch ISD Science Center Agenda8:00 AM 8:30 AM 9:15 AM 10:00 AM 10:45 AM 11:30 AM 12:00 PM 12:30 PM 1:15 PM 2:00 PM 3:00 P
Texas A&M - PHYS - 205
Session 7 June 7, 2005Promoting Excellence in Physics TeachingTHECB Type B Teacher Quality Professional Development Spring Branch ISD Science Center Agenda8:00 AM 8:30 AM 8:45 AM 9:30 AM 10:00 AM 11:00 AM 12:00 PM 12:30 PM 2:00 PM 3:00 PM 3:45 PM
Texas A&M - PHYS - 205
Session 6 June 6, 2005Promoting Excellence in Physics TeachingTHECB Type B Teacher Quality Professional Development Spring Branch ISD Science Center Agenda8:00 AM 8:30 AM 8:45 AM 9:00 AM 10:30 AM 11:15 AM 12:00 PM 12:30 PM 2:00 PM 3:00 PM 3:45 PM
Texas A&M - PHYS - 205
Session 12 June 14, 2005Promoting Excellence in Physics TeachingTHECB Type B Teacher Quality Professional Development Spring Branch ISD Science Center Agenda8:00 AM 8:30 AM 8:45 AM 10:00 AM 11:00 AM 11:15 AM 12:00 PM 12:30 PM 2:30 PM 3:00 PM 3:45
Texas A&M - PHYS - 205
Session 1 Feb 26, 2005Promoting Excellence in Physics TeachingTHECB Type B Teacher Quality Professional Development Spring Branch ISD Science Center Agenda8:00 AM 8:45 AM 9:00 AM 10:00 AM 10:30 AM 10:45 AM 12:00 PM 12:30 PM 1:00 PM 1:30 PM 2:45 P
Texas A&M - FRSC - 461
1Homework Assignment # 3 This Homework Assignment is to be completed individually.Objectives: - Gain experience with more ArcGIS data types o Import a shapefile to a geodatabase o Work with geodatabases, shapefiles, and raster data o Create simple
Texas A&M - SSLSNAP - 461
1Homework Assignment # 3 This Homework Assignment is to be completed individually.Objectives: - Gain experience with more ArcGIS data types o Import a shapefile to a geodatabase o Work with geodatabases, shapefiles, and raster data o Create simple
Texas A&M - FRSC - 461
Attribute Data and Database Structure Input, Data Sources, and DigitizingLab 3: Raster vs. VectorRaster Cellular based data structure composed of rows and columns for storing images. Homogenous units are called cells or pixels. Vector
Texas A&M - SSLSNAP - 461
Attribute Data and Database Structure Input, Data Sources, and DigitizingLab 3: Raster vs. VectorRaster Cellular based data structure composed of rows and columns for storing images. Homogenous units are called cells or pixels. Vector