Organization Computer EECC 550
Week 1 Week 2 Week 3 Week 4 Week 5 Week 6 Week 7 Week 8 Week 9 Week 10 Week 11
Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Notation (RTN). [Chapters 1, 2] Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4] CPU Organization: Datapath & Control Unit Design. [Chapter 5] MIPS Single Cycle Datapath & Control Unit Design. MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
Microprogrammed Control Unit Design. [Chapter 5]
Microprogramming Project
Midterm Review and Midterm Exam CPU Pipelining. [Chapter 6] The Memory Hierarchy: Cache Design & Performance. [Chapter 7] The Memory Hierarchy: Main & Virtual Memory. [Chapter 7] Input/Output Organization & System Performance Evaluation. [Chapter 8] Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Final Exam.
EECC550 - Shaaban
#1 Lec # 1 Winter 2007 12-4-2007
Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals
Computing Element Choices:
Computing Element Programmability Spatial vs. Temporal Computing Main Processor Types/Applications
General Purpose Processor Generations The Von Neumann Computer Model CPU Organization (Design) Recent Trends in Computer Design/performance Hierarchy of Computer Architecture Hardware Description: Register Transfer Notation (RTN) Computer Architecture Vs. Computer Organization Instruction Set Architecture (ISA):
Definition and purpose ISA Specification Requirements Main General Types of Instructions ISA Types and characteristics Typical ISA Addressing Modes Instruction Set Encoding Instruction Set Architecture Tradeoffs Complex Instruction Set Computer (CISC) Reduced Instruction Set Computer (RISC) Evolution of Instruction Set Architectures
(Chapters 1, 2)
EECC550 - Shaaban
#2 Lec # 1 Winter 2007 12-4-2007
Computing Element Choices
General Purpose Processors (GPPs): Intended for general purpose computing (desktops, servers, clusters..) Application-Specific Processors (ASPs): Processors with ISAs and architectural features tailored towards specific application domains
E.g Digital Signal Processors (DSPs), Network Processors (NPs), Media Processors, Graphics Processing Units (GPUs), Vector Processors??? ...
Co-Processors: A hardware (hardwired) implementation of specific algorithms with limited programming interface (augment GPPs or ASPs) Configurable Hardware:
Field Programmable Gate Arrays (FPGAs) Configurable array of simple processing elements
Application Specific Integrated Circuits (ASICs): A custom VLSI hardware solution for a specific computational task The choice of one or more depends on a number of factors including: - Type and complexity of computational algorithm
(general purpose vs. Specialized)
-
Desired level of flexibility/ programmability Development cost/time Power requirements
- Performance requirements - System cost - Real-time constrains
The main goal of this course is the study of fundamental design techniques for General Purpose Processors
EECC550 - Shaaban
#3 Lec # 1 Winter 2007 12-4-2007
Computing Element Choices
Programmability / Flexibility
General Purpose Processors (GPPs):
The main goal of this course is the study of fundamental design techniques for General Purpose Processors
Processor : Programmable computing element that runs programs written using a pre-defined set of instructions
Application-Specific Processors (ASPs)
Configurable Hardware
Selection Factors:
- Type and complexity of computational algorithms (general purpose vs. Specialized) - Desired level of flexibility - Performance - Development cost - System cost - Power requirements - Real-time constrains
Co-Processors Application Specific Integrated Circuits (ASICs)
Specialization , Development cost/time Performance/Chip Area/Watt (Computational Efficiency)
Performance
EECC550 - Shaaban
#4 Lec # 1 Winter 2007 12-4-2007
Computing Element Choices:
Computing Element Programmability
(Hardware) (Processor)
Software
Fixed Function:
Computes one function (e.g. FP-multiply, divider, DCT) Function defined at fabrication time e.g hardware (ASICs)
Programmable:
Computes any computable function (e.g. Processors) Function defined after fabrication
Parameterizable Hardware: Performs limited set of functions
e.g. Co-Processors
Processor = Programmable computing element that runs programs written using pre-defined instructions
EECC550 - Shaaban
#5 Lec # 1 Winter 2007 12-4-2007
Computing Element Choices:
Spatial vs. Temporal Computing
Spatial
(using hardware)
Defined by fixed functionality and connectivity of hardware elements
Temporal
(using software/program running on a processor)
Hardware Block Diagram
Processor Instructions (Program)
Processor = Programmable computing element that runs programs written using a pre-defined set of instructions
EECC550 - Shaaban
#6 Lec # 1 Winter 2007 12-4-2007
Main Processor Types/Applications
The main goal of this course is the study of fundamental design techniques for General Purpose Processors General Purpose Computing & General Purpose Processors (GPPs) High performance: In general, faster is always better. RISC or CISC: Intel P4, IBM Power4, SPARC, PowerPC, MIPS ... Used for general purpose software End-user programmable Real-time performance may not be fully predictable (due to dynamic arch. features) Heavy weight, multi-tasking OS - Windows, UNIX Normally, low cost and power not a requirement (changing) Servers, Workstations, Desktops (PCs), Notebooks, Clusters Embedded Processing: Embedded processors and processor cores Cost, power code-size and real-time requirements and constraints Once real-time constraints are met, a faster processor may not be better e.g: Intel XScale, ARM, 486SX, Hitachi SH7000, NEC V800... Often require Digital signal processing (DSP) support or other application-specific support (e.g network, media processing) Single or few specialized programs known at system design time Not end-user programmable Real-time performance must be fully predictable (avoid dynamic arch. features) Lightweight, often realtime OS or no OS Examples: Cellular phones, consumer electronics .. Microcontrollers Extremely code size/cost/power sensitive Single program Processor = Programmable computing element Small word size - 8 bit common that runs programs written using pre-defined instructions Usually no OS Highest volume processors by far Examples: Control systems, Automobiles, industrial control, thermostats, ...
Increasing Cost/Complexity Increasing volume
Examples of Application-Specific Processors (ASPs)
EECC550 - Shaaban
#7 Lec # 1 Winter 2007 12-4-2007
The Processor Design Space
Application specific architectures for performance Embedded Real-time constraints processors
Specialized applications Low power/cost constraints
Microprocessors
GPPs
Performance
Performance is everything & Software rules
The main goal of this course is the study of fundamental design techniques for General Purpose Processors
Microcontrollers Cost is everything
Chip Area, Power complexity
Processor = Programmable computing element that runs programs written using a pre-defined set of instructions
Processor Cost
EECC550 - Shaaban
#8 Lec # 1 Winter 2007 12-4-2007
General Purpose Processor/Computer System Generations
Classified according to implementation technology:
The First Generation, 1946-59: Vacuum Tubes, Relays, Mercury Delay Lines:
ENIAC (Electronic Numerical Integrator and Computer): First electronic computer, 18000 vacuum tubes, 1500 relays, 5000 additions/sec (1944). First stored program computer: EDSAC (Electronic Delay Storage Automatic Calculator), 1949.
The Second Generation, 1959-64: Discrete Transistors.
e.g. IBM Main frames
The Third Generation, 1964-75: Small and Medium-Scale Integrated (MSI) Circuits.
e.g Main frames (IBM 360) , mini computers (DEC PDP-8, PDP-11).
The Fourth Generation, 1975-Present: The Microcomputer. VLSI-based Microprocessors (single-chip processor)
First microprocessor: Intels 4-bit 4004 (2300 transistors), 1970. Personal Computer (PCs), laptops, PDAs, servers, clusters Reduced Instruction Set Computer (RISC) 1984
Common factor among all generations: All target the The Von Neumann Computer Model or paradigm
EECC550 - Shaaban
#9 Lec # 1 Winter 2007 12-4-2007
Partitioning of the programmable computing engine into components:
Central Processing Unit (CPU): Control Unit (instruction decode , sequencing of operations), Datapath (registers, arithmetic and logic unit, connections, buses ). AKA Program Counter Memory: Instruction (program) and operand (data) storage. (PC) Based Architecture Input/Output (I/O) sub-system: I/O bus, interfaces, devices. The stored program concept: Instructions from an instruction set are fetched from a common memory and executed one at a time The Program Counter (PC) points to next instruction to be processed
The Von Neumann Computer Model
Control Memory (instructions, data)
Input
Datapath
registers ALU, buses
Output I/O Devices
Computer System
CPU
Major CPU Performance Limitation: The Von Neumann computing model implies sequential execution one instruction at a time Another Performance Limitation: Separation of CPU and memory (The Von Neumann memory bottleneck)
EECC550 - Shaaban
#10 Lec # 1 Winter 2007 12-4-2007
Generic CPU Machine Instruction Processing Steps
(Implied by The Von Neumann Computer Model) Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Obtain instruction from program storage
(memory)
The Program Counter (PC) points to next instruction to be processed
Determine required actions and instruction size
Locate and obtain operand data
Compute result value or status Deposit results in storage for later use
Determine successor or next instruction
(i.e Update PC to fetch next instruction to be processed)
Major CPU Performance Limitation: The Von Neumann computing model implies sequential execution one instruction at a time
EECC550 - Shaaban
#11 Lec # 1 Winter 2007 12-4-2007
Hardware Components of Computer Systems
Five classic components of all computers: 1. Control Unit; 2. Datapath; 3. Memory; 4. Input; 5. Output
Processor
Central Processing Unit (CPU)
I/O Keyboard, Mouse, etc.
Computer Processor (active) Control Unit Datapath Memory (passive) (where programs, data live when running) Devices Input
I/O
Output
Disk
Display, Printer, etc.
EECC550 - Shaaban
#12 Lec # 1 Winter 2007 12-4-2007
CPU Organization (Design)
Datapath Design:
Components & their connections needed by ISA instructions
Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic Units, ...) Components Ways in which these components are interconnected (buses connections, multiplexors, etc.). Connections How information flows between components.
Control Unit Design:
Control/sequencing of operations of datapath components to realize ISA instructions
Logic and means by which such information flow is controlled. Control and coordination of FUs operation to realize the targeted Instruction Set Architecture to be implemented (can either be implemented using a finite state machine or a microprogram).
Hardware description with a suitable language, possibly using Register Transfer Notation (RTN).
ISA = Instruction Set Architecture The ISA forms an abstraction layer that sets the requirements for both complier and CPU designers
EECC550 - Shaaban
#13 Lec # 1 Winter 2007 12-4-2007
Branch Control Data cache
Control Unit
A Typical Microprocessor Layout: The Intel Pentium Classic
Bus Integer datapath Floatingpoint datapath
Instruction cache
1993 - 1997 60MHz - 233 MHz Datapath
First Level of Memory (Cache)
EECC550 - Shaaban
#14 Lec # 1 Winter 2007 12-4-2007
Control Unit
A Typical Microprocessor Layout: The Intel Pentium Classic
1993 - 1997 60MHz - 233 MHz
Datapath
First Level of Memory (Cache)
EECC550 - Shaaban
#15 Lec # 1 Winter 2007 12-4-2007
Computer System Components
CPU Core Recently 1 or 2 or 4 processor cores per chip 1 GHz - 3.8 GHz 4-way Superscaler All Non-blocking caches RISC or RISC-core (x86): L1 16-128K 1-2 way set associative (on chip), separate or unified Deep Instruction Pipelines L2 256K- 2M 4-32 way set associative (on chip) unified L1 Dynamic scheduling L3 2-16M 8-32 way set associative (off or on chip) unified CPU Multiple FP, integer FUs Dynamic branch prediction L2 Hardware speculation Examples: Alpha, AMD K7: EV6, 200-400 MHz Intel PII, PIII: GTL+ 133 MHz L3 SDRAM Caches Intel P4 800 MHz
PC100/PC133 100-133MHZ 64-128 bits wide 2-way inteleaved ~ 900 MBYTES/SEC )64bit)
Front Side Bus (FSB)
Off or On-chip
Current Standard
Double Date Rate (DDR) SDRAM PC3200 200 MHZ DDR 64-128 bits wide 4-way interleaved ~3.2 GBYTES/SEC (one 64bit channel) ~6.4 GBYTES/SEC (two 64bit channels)
Memory Controller
adapters
I/O Buses NICs
Example: PCI, 33-66MHz 32-64 bits wide 133-528 MBYTES/SEC PCI-X 133MHz 64 bit 1024 MBYTES/SEC
Memory Bus
Controllers
Memory Disks Displays Keyboards I/O Devices:
North Bridge South Bridge
Networks
RAMbus DRAM (RDRAM) 400MHZ DDR 16 bits wide (32 banks) ~ 1.6 GBYTES/SEC
I/O Subsystem
EECC550 - Shaaban
#16 Lec # 1 Winter 2007 12-4-2007
Chipset
1200
1100
Performance Increase of Workstation-Class Microprocessors 1987-1997
DEC Alpha 21264/600
1000
900 800
Performance
700 600 500 400 300 200 100
Integer SPEC92 Performance
DEC Alpha 5/500
DEC Alpha 5/300 DEC Alpha 4/266 IBM POWER 100 DEC AXP/500 HP 9000/750 1991 1992 Year 1993 1994 1995 1996 1997
IBM SUN-4/ MIPS MIPS 260 M/120 M2000 RS6000 1988 1989 1990
0 1987
> 100x performance increase in one decade
EECC550 - Shaaban
#17 Lec # 1 Winter 2007 12-4-2007
Microprocessor Transistor Count Growth Rate
100000000
Currently > 1 Billion
Alpha 21264: 15 million Pentium Pro: 5.5 million PowerPC 620: 6.9 million Alpha 21164: 9.3 million Sparc Ultra: 5.2 million
10000000
Moores Law
1000000 i80386 100000 i80286
Pentium i80486
i8086 10000
Moores Law:
2X transistors/Chip Every 1.5 years
2300
1000 1970
i8080 i4004
1975
1980
1985 Year
1990
1995
2000
(circa 1970)
Still holds today
~ 500,000x transistor density increase in the last 36 years
EECC550 - Shaaban
#18 Lec # 1 Winter 2007 12-4-2007
Increase of Capacity of VLSI Dynamic RAM (DRAM) Chips
size 1000000000
1024 M bit = 1 G bit
100000000
16 M bit
10000000
1000000
1 M bit 256k bit
100000
64k bit
10000
year size(Megabit) 1980 0.0625 1983 0.25 1986 1 1989 4 1992 16 1996 64 1999 256 2000 1024 1.55X/yr, or doubling every 1.6 years
1000 1970 1975 1980 1985 Year 1990 1995 2000
~ 17,000x DRAM chip capacity increase in 20 years
(Also follows Moores Law)
EECC550 - Shaaban
#19 Lec # 1 Winter 2007 12-4-2007
Computer Technology Trends:
Evolutionary but Rapid Change
Processor:
1.5-1.6 performance improvement every year; Over 100X performance in last decade.
Memory:
DRAM capacity: > 2x every 1.5 years; 1000X size in last decade. Cost per bit: Improves about 25% or more per year. Only 15-25% performance improvement per year.
Disk:
Capacity: > 2X in size every 1.5 years. to CPU performance causes Cost per bit: Improves about 60% per year. system performance bottlenecks 200X size in last decade. Only 10% performance improvement per year, due to mechanical limitations.
Performance gap compared
Expected State-of-the-art PC by end of year 2007 :
Processor clock speed: ~ 3000 MegaHertz (3 Giga Hertz) With 2-4 processor cores Memory capacity: > 4000 MegaByte (4 Giga Bytes) on a single chip Disk capacity: > 1000 GigaBytes (1 Tera Bytes)
EECC550 - Shaaban
#20 Lec # 1 Winter 2007 12-4-2007
A Simplified View of The Software/Hardware Hierarchical Layers
ons softw icati l are pp A s softw tem a s
Sy
re
Hardware
EECC550 - Shaaban
#21 Lec # 1 Winter 2007 12-4-2007
Hierarchy of Computer Architecture
High-Level Language Programs Assembly Language Programs
Software
Machine Language Program
Application Operating System Compiler Firmware
e.g. BIOS (Basic Input/Output System)
Software/Hardware Boundary
Instr. Set Proc. I/O system Datapath & Control
Instruction Set Architecture (ISA)
The ISA forms an abstraction layer that sets the requirements for both complier and CPU designers
Hardware
Digital Design Circuit Design
Layout
Microprogram
Logic Diagrams Circuit Diagrams
VLSI placement & routing
Register Transfer Notation (RTN)
EECC550 - Shaaban
#22 Lec # 1 Winter 2007 12-4-2007
Levels of Program Representation
temp = v[k]; High Level Language Program Compiler Assembly Language Program v[k] = v[k+1]; v[k+1] = temp;
Software
Assembler Machine Language Program
0000 1010 1100 0101 1001 1111 0110 1000
lw $15, lw $16, sw$16, sw$15,
1100 0101 1010 0000 0110 1000 1111 1001
0($2) 4($2) 0($2) 4($2)
1010 0000 0101 1100 1111 1001 1000 0110
MIPS Assembly Code
0101 1100 0000 1010 1000 0110 1001 1111
ISA Hardware
Machine Interpretation Control Signal Specification
ALUOP[0:3] <= InstReg[9:11] & MASK
Register Transfer Notation (RTN)
Microprogram
ISA = Instruction Set Architecture. The ISA forms an abstraction layer that sets the requirements for both complier and CPU designers
EECC550 - Shaaban
#23 Lec # 1 Winter 2007 12-4-2007
A Hierarchy of Computer Design
Level
1 2 3
Name
Electronics Logic
Modules
Gates, FFs Registers, ALUs ... Processors, Memories
Primitives
Transistors, Resistors, etc. Gates, FFs . Registers, ALUs
Descriptive Media
Circuit Diagrams Logic Diagrams Register Transfer Notation (RTN)
Organization
Low Level - Hardware 4 Microprogramming Firmware 5 Assembly language programming OS Routines Assembly language Instructions OS Routines High-level Languages Procedural Constructs Assembly Language Programs High-level Language Programs Problem-Oriented Programs Assembly Language Microinstructions Microprogram
6 Procedural Programming 7 Application High Level - Software
Applications Drivers .. Systems
EECC550 - Shaaban
#24 Lec # 1 Winter 2007 12-4-2007
Hardware Description
Hardware visualization:
Block diagrams (spatial visualization): Two-dimensional representations of functional units and their interconnections. Timing charts (temporal visualization): Waveforms where events are displayed vs. time.
Register Transfer Notation (RTN):
A way to describe microoperations capable of being performed by the data flow (data registers, data buses, functional units) at the register transfer level of design (RT). Also describes conditional information in the system which cause operations to come about. A shorthand notation for microoperations.
Hardware Description Languages:
Examples: VHDL: VHSIC (Very High Speed Integrated Circuits) Hardware Description Language, Verilog.
EECC550 - Shaaban
#25 Lec # 1 Winter 2007 12-4-2007
Register Transfer Notation (RTN)
Independent RTN: No predefined data flow is assumed (i.e No datapath design yet) Describe actions on registers and memory locations without regard to nonexistence of direct paths or intermediate registers. Useful to describe functionality of instructions of a given ISA. Dependent RTN: When RTN is used after the data flow (datapath design) is assumed to be frozen. No data transfer can take place over a path that does not exist. No RTN statement implies a function the data flow hardware is incapable of performing. The general format of an RTN statement: Conditional information : Action1; Action2; The conditional statement is often an AND of literals (status and control signals) in the system (a p-term). The p-term is said to imply the action. Possible actions include transfer of data to/from registers/memory data shifting, functional unit operations etc.
EECC550 - Shaaban
#26 Lec # 1 Winter 2007 12-4-2007
RTN Statement Examples
AB or R[A] R[B] where R[X] mean the content of register X
A copy of the data in entity B (typically a register) is placed in Register A If the destination register has fewer bits than the source, the destination accepts only the lowest-order bits. If the destination has more bits than the source, the value of the source is sign extended to the left.
CTL T0: A = B
The contents of B are presented to the input of combinational circuit A This action to the right of : takes place when control signal CTL is active and signal T0 is active. EECC550 - Shaaban
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RTN Statement Examples
MD M[MA] or MD Mem[MA]
Means the memory data (MD) register receives the contents of the main memory (M or Mem) as addressed from the Memory Address (MA) register.
AC(0), AC(1), AC(2), AC(3)
Register fields are indicated by parenthesis. The concatenation operation is indicated by a comma. Bit AC(0) is bit 0 of the accumulator AC The above expression means AC bits 0, 1, 2, 3 More commonly represented by AC(0-3)
E T3: CLRWRITE
The control signal CLRWRITE is activated when the condition E T3 is active. EECC550 - Shaaban
#28 Lec # 1 Winter 2007 12-4-2007
Computer Architecture Vs. Computer Organization
The term Computer architecture is sometimes erroneously restricted to computer instruction set design, with other aspects of computer design called implementation. The ISA forms an abstraction layer that sets the requirements for both complier and CPU designers More accurate definitions: Instruction Set Architecture (ISA): The actual programmervisible instruction set and serves as the boundary or interface between the software and hardware. Implementation of a machine has two components: Organization: includes the high-level aspects of a computers CPU Microarchitecture design such as: The memory system, the bus structure, the (CPU design) internal CPU unit which includes implementations of arithmetic, logic, branching, and data transfer operations. Hardware: Refers to the specifics of the machine such as detailed logic design and packaging technology. Hardware design and implementation In general, Computer Architecture refers to the above three aspects: 1- Instruction set architecture 2- Organization. 3- Hardware.
EECC550 - Shaaban
#29 Lec # 1 Winter 2007 12-4-2007
Assembly Programmer Or Compiler
Instruction Set Architecture (ISA)
... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. an abstraction layer Amdahl, Blaaw, and Brooks, 1964. The ISA formsfor both complier andthat sets the requirements CPU designers
The instruction set architecture is concerned with:
Organization of programmable storage (memory & registers): Includes the amount addressable of memory and number of available registers. Data Types & Data Structures: Encodings & representations. Instruction Set: What operations are specified. Instruction formats and encoding. Modes of addressing and accessing data items and instructions Exceptional conditions.
EECC550 - Shaaban
#30 Lec # 1 Winter 2007 12-4-2007
Computer Instruction Sets
Regardless of computer type, CPU structure, or hardware organization, every machine instruction must specify the following:
Opcode: Which operation to perform. Example: add, load, and branch. Opcode = Operation Code Where to find the operand or operands, if any: Operands may be contained in CPU registers, main memory, or I/O ports. Where to put the result, if there is a result: May be explicitly mentioned or implicit in the opcode. Where to find the next instruction: Without any explicit branches, the instruction to execute is the next instruction in the sequence or a specified address in case of jump or branch instructions. EECC550 - Shaaban
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Instruction Set Architecture (ISA) Instruction Specification Requirements
Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction
Instruction Format or Encoding: How is it decoded? Location of operands and result (addressing modes): Where other than memory? How many explicit operands? How are memory operands located? Which can or cannot be in memory? Data type and Size. Operations What are supported Successor instruction: Jumps, conditions, branches. Fetch-decode-execute is implicit.
EECC550 - Shaaban
#32 Lec # 1 Winter 2007 12-4-2007
Main General Types of Instructions
1. Data Movement Instructions, possible variations: Memory-to-memory. Memory-to-CPU register. CPU-to-memory. Constant-to-CPU register. CPU-to-output. etc.
2. Arithmetic Logic Unit (ALU) Instructions: Logic instructions Integer Arithmetic Instructions Floating Point Arithmetic Instructions 3. Branch (Control) Instructions: Unconditional jumps. Conditional branches.
EECC550 - Shaaban
#33 Lec # 1 Winter 2007 12-4-2007
Examples of Data Movement Instructions
Instruction
MOV A,B lwz R3,A li $3,455 MOV AX,BX LEA.L (A0),A2
Meaning
Move 16-bit data from memory loc. A to loc. B Move 32-bit data from memory loc. A to register R3 Load the 32-bit integer 455 into register $3 Move 16-bit data from register BX into register AX Load the address pointed to by A0 into A2
Machine
VAX11 PPC601 MIPS R3000 Intel X86 MC68000
EECC550 - Shaaban
#34 Lec # 1 Winter 2007 12-4-2007
Examples of ALU Instructions
Instruction
MULF A,B,C
Meaning
Multiply the 32-bit floating point values at mem. locations A and B, and store result in loc. C Store the negative absolute value of register r1 in r2 Store the logical OR of register $1 with 255 into $2 Shift the 16-bit value in register AX left by 4 bits Add the 32-bit values in registers D0, D1 and store the result in register D0
Machine
VAX11
nabs r3,r1 ori $2,$1,255 SHL AX,4 ADD.L D0,D1
PPC601 MIPS R3000 Intel X86 MC68000
EECC550 - Shaaban
#35 Lec # 1 Winter 2007 12-4-2007
Examples of Branch Instructions
Instruction
BLBS A, Tgt
Meaning
Branch to address Tgt if the least significant bit at location A is set. Branch to location in r2 if the previous comparison signaled that one or more values was not a number. Branch to location PC+4+32 if contents of $1 and $2 are equal. Jump to Addr if contents of register CX = 0. Branch to next if overflow flag in CC is set.
Machine
VAX11
bun r2
PPC601
Beq $2,$1,32
MIPS R3000
JCXZ Addr BVS next
Intel X86 MC68000
EECC550 - Shaaban
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Operation Types in The Instruction Set
Operator Type
Arithmetic and logical Data transfer
1 2
Examples
Integer arithmetic and logical operations: add, or Loads-stores (move on machines with memory addressing) Branch, jump, procedure call, and return, traps. Operating system call/return, virtual memory management instructions ... Floating point operations: add, multiply .... Decimal add, decimal multiply, decimal to character conversion String move, string compare, string search The same operation performed on multiple data (e.g Intel MMX, SSE)
Control System
3
Floating point Decimal String Media
EECC550 - Shaaban
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Instruction Usage Example: Top 10 Intel X86 Instructions
Rank 1 2 3 4 5 6 7 8 9 10 instruction load conditional branch compare store add and sub move register-register call return Total Integer Average Percent total executed 22% 20% 16% 12% 8% 6% 5% 4% 1% 1% 96%
Observation: Simple instructions dominate instruction usage frequency.
CISC to RISC observation
EECC550 - Shaaban
#38 Lec # 1 Winter 2007 12-4-2007
Types of Instruction Set Architectures
According To Operand Addressing Fields
Memory-To-Memory Machines:
Operands obtained from memory and results stored back in memory by any instruction that requires operands. No local CPU registers are used in the CPU datapath. Include: The 4 Address Machine. Machine = ISA or CPU targeting a specific ISA type The 3-address Machine. The 2-address Machine.
The 1-address (Accumulator) Machine:
A single local CPU special-purpose register (accumulator) is used as the source of one operand and as the result destination.
The 0-address or Stack Machine:
A push-down stack is used in the CPU.
General Purpose Register (GPR) Machines:
The CPU datapath contains several local general-purpose registers which can be used as operand sources and as result destinations. A large number of possible addressing modes. Load-Store or Register-To-Register Machines: GPR machines where only data movement instructions (loads, stores) can obtain operands from memory and store results to memory.
CISC to RISC observation (load-store simplifies CPU design)
EECC550 - Shaaban
#39 Lec # 1 Winter 2007 12-4-2007
Types of Instruction Set Architectures
Memory-To-Memory Machines: The 4-Address Machine
No program counter (PC) or other CPU registers are used. Instruction encoding has four address fields to specify: Location of first operand. - Location of second operand. Place to store the result. - Location of next instruction. Instruction: Memory
CPU Op1Addr: Op1 Op2Addr: Op2 ResAddr: Res
add Res, Op1, Op2, Nexti Meaning: Res Op1 + Op2 or more precise RTN: M[ResAddr] M[Op1Addr] + M[Op2Addr]
Instruction Format (encoding)
+
: :
Bits:
8
24
24
24
24
NextiAddr: Nexti
add
Instruction Size: 13 bytes Opcode Which operation
ResAddr
Where to put result
Op1Addr
Op2Addr
NextiAddr
Where to find next instruction
Where to find operands
Can address
224
bytes = 16 MBytes
EECC550 - Shaaban
#40 Lec # 1 Winter 2007 12-4-2007
Types of Instruction Set Architectures
Memory-To-Memory Machines: The 3-Address Machine
A program counter (PC) is included within the CPU which points to the next instruction. No CPU storage (general-purpose registers).
Memory
CPU
Instruction: add Res, Op1, Op2 Meaning: Res Op1 + Op2 or more precise RTN: M[ResAddr] M[Op1Addr] + M[Op2Addr] PC PC + 10 Increment PC
Instruction Format (encoding)
Bits:
8 24 24 24
Instruction Size: 10 bytes
Op1Addr: Op1 Op2Addr: Op2 ResAddr: Res
+
: :
NextiAddr: Nexti
Where to find next instruction
Program 24 Counter (PC)
add
Opcode Which operation
ResAddr
Where to put result
Op1Addr
Op2Addr
Where to find operands
Can address 224 bytes = 16 MBytes
EECC550 - Shaaban
#41 Lec # 1 Winter 2007 12-4-2007
Types of Instruction Set Architectures
Memory-To-Memory Machines: The 2-Address Machine
The 2-address Machine: Result is stored in the memory address of one of the operands. Instruction:
Memory
CPU
add Op2, Op1 Meaning: Op2 Op1 + Op2 or more precise RTN: M[Op2Addr] M[Op1Addr] + M[Op2Addr] PC PC + 7 Increment PC
Instruction Format (encoding)
Bits:
8 24 24
Op1Addr: Op1
+
Op2Addr: Op2,Res
: :
NextiAddr: Nexti
Where to find next instruction
Program 24 Counter (PC)
add
Opcode Which operation
Op2Addr
Op1Addr
Where to find operands Instruction Size: 7 bytes
Can address 224 bytes = 16 MBytes
Where to put result
EECC550 - Shaaban
#42 Lec # 1 Winter 2007 12-4-2007
Types of Instruction Set Architectures
The 1-address (Accumulator) Machine
A single accumulator in the CPU is used as the source of one operand and result destination.
Instruction:
Memory
CPU
add Op1 Meaning: Acc Acc + Op1 or more precise RTN: Acc Acc + M[Op1Addr] PC PC + 4 Increment PC
Op1Addr: Op1
+
: :
NextiAddr: Nexti
Accumulator Where to find next instruction
Program 24 Counter (PC)
Where to find operand2, and where to put result
Instruction Format (encoding)
Bits:
8 24
add
Op1Addr
Opcode Where to find Which operand1 operation
Instruction Size: 4 bytes
Can address 224 bytes = 16 MBytes
EECC550 - Shaaban
#43 Lec # 1 Winter 2007 12-4-2007
Types of Instruction Set Architectures
The 0-address (Stack) Machine
Memory
push
A push-down stack is used in the CPU.
4 Bytes
CPU
Stack
Instruction Format 24 Bits: 8
Op1Addr: Op1 Op2Addr: Op2 ResAddr: Res
pop
TOS SOS etc. 8
Op2, Res Op1
add
Instruction: push push Op1 Opcode Meaning: TOS M[Op1Addr]
Op1Addr
Where to find operand
+
: :
NextiAddr: Nexti
Instruction: Instruction Format 1 Byte add Bits: 8 Meaning: add TOS TOS + SOS
Opcode
4 Bytes
Program 24 Counter (PC)
Instruction Format 24 Bits: 8
pop Instruction: pop Res Opcode Meaning: M[ResAddr] TOS
ResAddr
Memory Destination
TOS = Top Entry in Stack SOS = Second Entry in Stack
Can address
224
bytes = 16 MBytes
EECC550 - Shaaban
#44 Lec # 1 Winter 2007 12-4-2007
Types of Instruction Set Architectures
General Purpose Register (GPR) Machines
CPU contains several general-purpose registers which can be used as operand sources and result destination.
Eight general purpose Registers (GPRs) assumed here: R1-R8
Memory
CPU
Registers
load
add
Op1Addr: Op1
+
: :
NextiAddr: Nexti
store
R8 R7 R6 R5 R4 R3 R2 R1
Instruction Format Instruction: 3 24 Bits: 8 load R8, Op1 load R8 Op1Addr Meaning: R8 M[Op1Addr] Opcode Where to find operand1 PC PC + 5
Size = 4.375 bytes rounded up to 5 bytes
Instruction: add R2, R4, R6 Meaning: R2 R4 + R6 PC PC + 3
Instruction Format 3 3 3 Bits: 8
add
R2 R4 R6
Opcode Des Operands
Size = 2.125 bytes rounded up to 3 bytes
Program 24 Counter (PC)
Instruction Format Instruction: 3 24 Bits: 8 store R2, Op2 Meaning: store R2 ResAddr M[Op2Addr] R2 Opcode Destination PC PC + 5
Size = 4.375 bytes rounded up to 5 bytes
Here add instruction has three register specifier fields While load, store instructions have one register specifier field and one memory address specifier field
EECC550 - Shaaban
#45 Lec # 1 Winter 2007 12-4-2007
Expression Evaluation Example with 3-, 2-, 1-, 0-Address, And GPR Machines
For the expression A = (B + C) * D - E
3-Address 2-Address
1-Address Accumulator where A-E are in memory
GPR 0-Address Register-Memory Load-Store Stack
push B push C add push D mul push E sub pop A
8 instructions Code size: 23 bytes 5 memory accesses for data
add A, B, C load A, B mul A, A, D add A, C sub A, A, E mul A, D sub A, E
load B add C mul D sub E store A
load R1, B add R1, C mul R1, D sub R1, E store A, R1
load R1, B load R2, C add R3, R1, R2 load R1, D mul R3, R3, R1 load R1, E sub R3, R3, R1 store A, R3
8 instructions Code size: 34 bytes 5 memory accesses for data
3 instructions Code size: 30 bytes 9 memory accesses for data
4 instructions 5 instructions Code size: Code size:
28 bytes 11 memory accesses for data
20 bytes 5 memory accesses for data
5 instructions Code size: 25 bytes 5 memory accesses for data
EECC550 - Shaaban
#46 Lec # 1 Winter 2007 12-4-2007
Typical GPR ISA Memory Addressing Modes
Addressing Mode
Register Immediate Displacement Indirect Indexed Absolute Memory indirect Autoincrement
Sample Instruction
Add R4, R3 Add R4, #3 Add R4, 10 (R1) Add R4, (R1) Add R3, (R1 + R2) Add R1, (1001) Add R1, @ (R3) Add R1, (R2) +
Meaning
R4 R4 + R3 R4 R4 + 3 R4 R4 + Mem[10+ R1] R4 R4 + Mem[R1] R3 R3 +Mem[R1 + R2] R1 R1 + Mem[1001] R1 R1 + Mem[Mem[R3]] R1 R1 + Mem[R2] R2 R2 + d R2 R2 - d R1 R1 + Mem[R2] R1 R1+ Mem[100+ R2 + R3*d]
Autodecrement
Add R1, - (R2)
Scaled
Add R1, 100 (R2) [R3]
CISC to RISC observation (fewer addressing modes simplify CPU design)
EECC550 - Shaaban
#47 Lec # 1 Winter 2007 12-4-2007
Addressing Modes Usage Example
For 3 programs running on VAX ignoring direct register mode: Displacement Immediate: Register deferred (indirect): Scaled: Memory indirect: Misc: 42% avg, 32% to 55%
75%
33% avg, 17% to 43% 13% avg, 3% to 24% 7% avg, 0% to 16% 3% avg, 1% to 6% 2% avg, 0% to 3%
88%
75% displacement & immediate 88% displacement, immediate & register indirect. Observation: In addition Register direct, Displacement, Immediate, Register Indirect addressing modes are important.
CISC to RISC observation (fewer addressing modes simplify CPU design)
EECC550 - Shaaban
#48 Lec # 1 Winter 2007 12-4-2007
Displacement Address Size Example
Avg. of 5 SPECint92 programs v. avg. 5 SPECfp92 programs
Int. Avg. 30% 20% 10% 0% 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FP Avg.
Displacement Address Bits Needed
For displacement addressing mode
1% of addresses > 16-bits 12 - 16 bits of displacement needed
CISC to RISC observation
EECC550 - Shaaban
#49 Lec # 1 Winter 2007 12-4-2007
15
Instruction Set Encoding
Considerations affecting instruction set encoding:
The number of registers and addressing modes supported by ISA. The impact of of the size of the register and addressing mode fields on the average instruction size and on the average program. To encode instructions into lengths that will be easy to handle in the implementation. On a minimum to be a multiple of bytes. Instruction Encoding Classification:
1. Fixed length encoding: Faster and easiest to implement in hardware. e.g. Simplifies design of pipelined C...