Electronic ESE535: Design Automation
Day 15: March 18, 2009 Static Timing Analysis and Multi-Level Speedup
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Today
Topological Worst Case
not adequate (too conservative)
Sensitization Conditions Timed Calculus Delay-justified paths
Timed-PODEM
Speedup
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Topological Worst-Case Delay
Compute ASAP schedule
Take max of arrival times Apply node Delay
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Topological Worst-Case Delay
1 3 2 2 1 2
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Node Delays
1
Topological Worst-Case Delay
7 1 6 3 2 2 3 2 1 0 0 1 0 0 0 2 0
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Compute Delays
4 1 3 2
Conservative
Topological Worst-Case Delay can be conservative
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[Fig/Examples from Logic Synthesis 6 by Devadas, Gosh, Keutzer 1994]
Example
Assume each gate 1:
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6 delays in longest path 7 (5 if assume c0 latest arriving)
Example
Is this path possible?
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Out from mux 0 input and10 = 0 p0=0 or p1=0 p1=0 167 not matter p0=0 c0 not matter 8 This path not feasible
False Paths
Once consider logic for nodes
There are logical constraints on data values
There are paths which cannot logically occur
Call them false paths
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What can we do?
Need to assess what paths are real Brute force
for every pair of inputs compute delay in outputs from in1in2 input transition take worst case
Expensive:
22n delay traces
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Alternately
Look at single vector and determine what controls delay of circuit
I.e. look at values on path and determine path sensitized to change with input
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Controlled Inputs
Controlled input to a gate:
input whose value will determine gate output e.g.
0 on a AND gate 1 on a OR gate
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Static Sensitization
A path is statically sensitized
if all the side (non-path) inputs are noncontrolling I.e. this path value flips with the input
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Statically Sensitized Path
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Sufficiency
Static Sensitization is sufficient for a path to be a true path in circuit
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...but not necessary
Paths of length 3 not statically sensitizable.
But there is a true path of delay 3.
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Static Co-sensitization
Each output with a controlled value
has a controlling value as input on path (and vice-versa for non-controlled)
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17 May trace multiple edges
Necessary
Static Co-sensitization is a necessary condition for a path to be true
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...but not sufficient
Cosensitize path of length 6. Real delay is 5.
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Combining
Combine these ideas into a timedcalculus for computing delays for an input vector
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Computing Delays
AND Timing Calculus
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Rules
If gate output is at a controlling value, pick the minimum input and add gate delay If gate output is at a non-controlling value, pick the maximum input and add gate delay
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Example (1)
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Example (2)
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Now...
We know how to get the delay of a single input condition Could:
find critical path search for an input vector to sensitize if fail, find next path ...until find longest true path
May be O(2n)
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Better Approach
Ask if can justify a delay greater than T Search for satisfying vector
...or demonstration that none exists
Binary search to find tightest delay
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Delay Computation
Modification of a testing routine
used to justify an output value for a circuit similar to SAT
PODEM
backtracking search to find a suitable input vector associated with some target output Simply a branching search with implication pruning
Heuristic for smart variable ordering
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Search
Takes two lists
outputs to set; inputs already set
Propagate values and implications If all outputs satisfied succeed Pick next PI to set and set value
Search with this value set If inconsistent
If PI not implied Invert value of PI Search with this value set If inconsistent fail Else succeed Else fail
Else succeed
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Picking next variable to set
Follow back gates w/ unknown values
sometimes dictate output input must be
(AND needing 1 output; with one input already assigned 1)
sometimes have to guess what to follow
(OR with 1 output and no inputs set) Uses heuristics to decide what to follow
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Example
Try justify g=1
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Example
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For Timed Justification
Also want to compute delay
on incompletely specified values
Compute bounds on timing
upper bound, lower bound Again, use our timed calculus
expanded to unknowns
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Delay Calculation
AND rules
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Timed PODEM
Input: value to justify and delay T Goal: find input vector which produces value and exceeds delay T Algorithm
similar implications check timing as well as logic
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Example
Justify 1(3)
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Example
Fail to justify 1(3) Justify 0(3)
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Search
Less than 2n
pruning due to implications here saw a must be 0
no need to search 1xx subtree
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Questions
On static timing analysis?
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Speed Up
(sketch flavor)
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Speed Up
Start with area optimized network Know target arrival times
Know delay from static analysis
Want to reduce delay of node
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Basic Idea
Improve speed by:
Collapsing node(s) Refactoring collapsed subgraph to reduce height
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Speed Up
While (delay decreasing, timing not met)
Compute delay (slack)
Static timing analysis
Generate network close to critical path Weight nodes in network
w/in some delay , to some distance d Less weight = more potential to improve, prefer to cut
Compute mincut of nodes on weighted network For each node in cutset
Partial collapse
For each node in cutset
Timing redecompose
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MinCut of Nodes
Cut nodes not edges
Typically will need to transform to dual graph
All edges become nodes, nodes become edges
Then use maxflow/mincut
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MinCut of Nodes
What are possible cuts?
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MinCut of Nodes
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MinCut of Nodes
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Weighted Cut
W=Wt+Wa tuning parameter Want to minimize area expansion
Things in collapsed network may be duplicated E.g. Wa=literals in duplicated logic
Want to maximize likely benefit
Prefer nodes with varying input times to the "near critical path" network
Quantify: large variance in arrival times
Prefer nodes with critical path on longer paths
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