216 EEC Lecture #7: Low Power Interconnect
Rajeevan Amirtharajah University of California, Davis
Outline
Announcements Review: Sizing, Clocking, Latches & Flip-Flops Low Swing Buses and Level Converters Stepwise Charging Data Dependent Swings Bus Invert Coding Modulated Signaling
R. Amirtharajah, EEC216 Winter 2009
2
Outline
Announcements Review: Sizing, Clocking, Latches & Flip-Flops Low Swing Buses and Level Converters Stepwise Charging Data Dependent Swings Bus Invert Coding Modulated Signaling
R. Amirtharajah, EEC216 Winter 2009
3
Summary of Sizing for Minimum Energy
Device sizing combined with voltage reduction is very effective approach to reducing energy consumption For large fanouts, a factor of 10 reduction can be gained K = 1 case is exception; minimum-size device optimal Overly large sizing can result in large power penalty Typical of designs today, especially standard cells since cells designed for worst case load conditions to guarantee design meets timing Optimal sizing for minimum energy (at fixed delay) smaller than sizing for minimum delay Example: for fanout K = 20, kopt(energy) = 3.53 vs. kopt(delay) = 4.47 Further increasing sizes leads to minimal voltage reductions
R. Amirtharajah, EEC216 Winter 2009 4
Synchronous System With Global Clock
LOGIC
CLK Reference from PLL
LOGIC
Simple and convenient design style with minimal circuit overhead Challenge is creating and distributing clock with low skew and jitter (timing uncertainty) at high frequencies
R. Amirtharajah, EEC216 Winter 2009 5
Critical Path Replica Self-Timed System
LOGIC LOGIC
CRITICAL PATH REPLICA
Similar to synchronous styl...
lecture7