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Lab Queued A-D Conversion (eQADC)
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Queued Analog-to-Digital Conversion
Acquire analog input from the potentiometer and observe the result using the debugger Using an oscilloscope, measure the time required to complete one conversion by toggling GPIO Acquire a sine wave signal from the function generator and investigate aliasing
Generate a square wave signal from the input sine function and observe output signal frequency on the digital oscilloscope Use the software oscilloscope to output the acquired signal to the serial port for display on the monitor
Software Oscilloscope Display
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Queued Analog-to-Digital Conversion
Chapter 19 MPC5553-RM
Two12-bit ADC (ADC0/1) Single ended, 0-5v Double ended 2.5 2.5v 40 MUXed input channels
Command FIFO (CFIFO) triggers ADC Results FIFO (RFIFO) receives conversions DMA (Direct Memory Access) transfers
Commands from userdefined command queue to CFIFO Results from RFIFO to used-defined results queue
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Queued Analog-to-Digital Conversion
6 CFIFOs (EQADC_CFIFO[0-5]) 6 RFIFOs (EQADC_RFIFO[0-5]) Any CFIFO can command either ADC, and results can be sent to any RFIFO
We will configure EQADC_CFIFO0 and EQACD_CFIFO1 to use ADC0 and put the results in RFIFO0 and RFIFO1 respectively Write commands to CFIFO push registers and read results from RFIFO pop registers
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Queued Analog-to-Digital Conversion
Operating Modes
Single-scan mode
Command Queue is scanned one time Software involvement is needed to re-arm queue after queue is scanned
Continuous-scan mode
Command Queue is scanned multiple times Software involvement is not needed to re-arm queue
All modes may be software-triggered, edgetriggered or level-triggered
We will set up 2 queues:
EQADC_CFIFO0 for software-triggered single scan EQADC_CFIFO1 for software-triggered continuous scan
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Programming the eQADC
Like other peripherals, the eQADC must be configured by writing commands to special purpose registers
eQADC Module Configuration Register (EQADC MCR) CFIFO Control Registers (EQADC CFCRn)
Structure to access these registers is included in MPC5553.h
EQADC_MCR described in Section 19.3.2.1 of the Reference Manual EQADC_CFCRn described in Section 19.3.2.6 and Tables 19-9 and 19-10
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EQADC_MCR
ESSIE: Synchronous Serial Interface enable (disable = 00) DBG: Debug mode enable (disable = 00)
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EQADC_CFCRn
SSE: Single scan enable CFINV: CFCR invalidate (CFINV = 0) MODE: Operating mode (Table 9-10)
0000: disabled 0001: software triggered single scan 1001: software triggered continuous scan
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Programming the eQADC
Unlike other peripherals, some eQADC registers are not accessible to the programmer Registers that control on-chip ADCs are programmed by sending 32-bit configuration and command messages to the CFIFO
Write Configuration Command Message
Sets the control registers of the on-chip ADCs.
Read Configuration Command Message
Reads the contents of the on-chip ADC registers which are only accessible via command messages
Conversion Command Message
Conversion result is returned with optional time stamp
Non-memory Mapped ADC Registers
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5 configuration registers for each ADC Control register (ADCn_CR)
Enables ADC Enables external multiplexing Sets the ADC clock speed
Other configuration registers enable time stamp and set calibration parameters
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ADCn_CR
ADCn_EN: Enable ADC ADCn_EMUX: Enable MUX ADCn_CLK_PS: ADC clock prescaler (see Table 19-28)
R/W Configuration Command Message Format
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EOQ: end-of-queue PAUSE: wait for trigger See Tables 19.35 and 36 EB: external buffer (0 for on-chip ADC) BN: buffer number (0 or 1) R/W: 0 = write; 1 = read command message ADC_REGISTER HIGH BYTE: value to be written into the most significant 8 bits of control/configuration register when the R/W bit is negated ADC_REGISTER LOW BYTE: value to be written into the least significant 8 bits of control/configuration register when the R/W bit is negated ADC_REG_ADDRESS: ADC register address (see Tables 19-25 and 26)
Configuration Command Message Format
As usual, we can use a structure or union to construct a configuration command message Access as a register or individual bit fields
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union adc_config_msg { vuint32_t R; struct { vuint32_t header:6; vuint32_t command:26; } BB; struct { vuint32_t EOQ:1; vuint32_t PAUSE:1; vuint32_t :3; vuint32_t EB:1; vuint32_t BN:1; vuint32_t RW:1; vuint32_t HIGH_BYTE:8; vuint32_t LOW_BYTE:8; vuint32_t ADC_REG_ADDRESS:8; } B; };
Configuration Command Message Format
Example: Select ACD0 and configure the ADC0_CR
union adc_config_msg config; /* ADC configurations- command internal ADC register parameters config.R = 0; config.B.BN = 0; config.B.HIGH_BYTE = 0x80; config.B.LOW_BYTE = 0x05; /* Command ADC 0 /* Enable ADC module /* Use clock prescaler of 10 /* ADC0_CR address
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config.B.ADC_REG_ADDRESS = 0x01;
Conversion Command Message Command Format
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Conversion Message Format
Our conversion command structure
union cfifo_msg{ vuint32_t R; struct{ vuint32_t header:6; vuint32_t command:26; } BB; struct{ vuint32_t EOQ:1; vuint32_t PAUSE:1; vuint32_t :3; vuint32_t EB:1; vuint32_t BN:1; vuint32_t CAL:1; vuint32_t MESSAGE_TAG:4; vuint32_t LST:2; vuint32_t TSR:1; vuint32_t FMT:1; vuint32_t CHANNEL_NUMBER:8; vuint32_t :8; } B; };
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Conversion Command Message Format
Conversion command message example:
union cfifo_msg cmd; cmd.R = cmd.B.EOQ = cmd.B.PAUSE = cmd.B.EB = cmd.B.BN = cmd.B.CAL = cmd.B.MESSAGE_TAG = cmd.B.LST = cmd.B.TSR = cmd.B.FMT = cmd.B.CHANNEL_NUMBER = 0; 1; /* end-of-queue */ 0; 0; 0; /* use first QADC unit */ 0; /* no calibration */ 0b0000; /* result queue 0 */ 0b10; /* sample time = 2 clks */ 0; 0; single_channel;
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Conversion Result Format
12-bit conversion is stored in a 16-bit RFIFO as a signed or unsigned integer In either case, the result is stored in bits [2:13], i.e., bit shifted 2 left
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Direct Memory Access (DMA)
Recall
We need to transfer ADC configuration and conversion commands from memory to CFIFO We need to transfer results from the RFIFO to memory
This could take lots of time if CPU intervention is required
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Direct Memory Access (DMA)
Direct Memory Access (DMA)
DMA services:
peripheral requests (eQADC, for example) software initiated requests
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Transfer Control Descriptor (TCD) used to define each channel (source and destination address, address increments, size etc..) See Chapter 9 in the Reference Manual, and Lab 3 document for description of DMA programming We have written the DMA code for Lab 3!
Direct Memory Access (DMA)
Function setupDMARequests continuously fills the CFIFO with commands from CONT_SCAN_QUEUE to read each ADC channel sequentially, and stores the results in CONT_SCAN_RESULTS
System RAM DMA
Ch0 Source Ch0 Destination Ch1 Source Ch1 Destination
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eQADC CMD queue start: &CONT_SCAN_QUEUE[0] eQADC-A CMD queue end
eQADC
CMD FIFO CMD Word RSLT FIFO CMD Word
eQADC Result queue start: &CONT_SCAN_RESULTS[0] eQADC Result queue end
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Lab 3 Software
As usual, you are given qadc.h with function prototypes; you will write the functions in qadc.c, plus application code in lab3.c Four functions (plus DMA) are required:
qadcInit: Initialize the eQADC:
Configure the conversion command queues Configure the ADC
fillCCMTable: Build command conversion lists
Single and continuous scan lists required
qadcRead1 and qadcRead2: Read the results
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Lab 3 Software
qadcInit: configuring the conversion command queues
Use the structure found in MPC553.h to access the MCR, CFIFO control registers and CFIFO push registers
Clear the MCR and set up one queue for software-triggered single scan and one queue for software-triggered continuous scan Use the configuration command message structure to enable ADC0 and set the clock prescaler
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Lab 3 ...