497 ECE JS Lecture - 17 On-Chip Power Distribution
Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois [e-mail]
ECE 497-JS, Spring 2004
Copyright by Jose E. Schutt-Aine , All Rights Reserved
1
Power-Supply-Level Fluctuations
Total capacitive load associated with an IC increases as minimum feature size shrinks Average current needed to charge capacitance increases Rate of change of current (dI/dt) also increases
Total chip current may change by large amounts within short periods of time Fluctuation at the power supply level due to self inductance in distribution lines
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
2
Reducing Power-Supply-Level Fluctuations
Minimize dI/dt noise Decoupling capacitors Multiple power & ground pins Taylored driver turn-on characteristics
Decoupling capacitors Large capacitor charges up during steady state Assumes role of power supply during current switching Leads should be small to minimize parasitic inductance Must be placed as close as possible to the chip
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
3
Effects of SSN
SSN can affect circuits in 3 ways 1) SSN may increase chip-to-chip delays 2) Affects the operation of the receiving chips 3) May affect gates on the sending chip Current driven off-chip has only one return path: power and ground pins of the chip carrier to minimize effective inductance of the return path and noise, many power/ground pins must be supplied for off-chip drivers
On-chip circuitry can close the loop by small inductance on chip lines
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
4
Model for On-Chip Power Distribution
VDD PINS L VDD RPU C + VDD L RPD C RPD GROUND C C RPD RPU RPU
GROUND PINS
1) 2) 3) 4) 5)
Portion of circuits switch Vdd-VSS is reduced Non-switching devices come to rescue (through low inductance) Share charge with switching capacitors Power-level collapse is prevented
ECE 497-JS, Spring 2004
Copyright by Jose E. Schutt-Aine , All Rights Reserved
5
Design Criteria for SSN
Inductive time constant must be much smaller than its capacitive time constant L R RC
Valid for external power distribution lines that carry the current to the chip and for external lines that distribute it on the chip - Presently satisfied by on-chip lines - Board and package power lines are too high to satisfy criteria
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
6
Design Criteria for SSN
Cannot distribute power on the board simply by using the printed circuit wires and connecting them to the power/ground pins of the chip directly. Off chip power distribution must employ methods that reduce the effects of line and pin inductance.
To insure reliable circuit operation:
dI L dt
VDD
Equivalence of 2 conditions is obtained by setting:
dI = VDD / R
dt = RC
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
7
Resonance Condition at Power-Supply Lines
- Periodic nature of digital circuits can cause resonance - Large fluctuation can build up and cause circuit to fail
Rchip Lmod Cchip Z(jw)
f chip
1 = 2 Lmod Cchip
Lmod Z ( j chip ) Rchip Cchip
- fchip should be much larger than the clock frequency - Impedance should be kept small
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
8
Delta-I Noise in CMOS Circuits
In a CMOS chip the portion of the circuit that is not switching (R1, C1) at a given system cycle helps the switching portion of the chip (R2, C2). L
ext
+ VDD -
R1
R2
C1
C2
C1 VDD + V = VDD C1 + C2
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
9
Delta-I Noise in ECL Bipolar Circuits
Because of diode structure of BJTs, current can only flow in one direction L Vx
ext
+ VDD R1 R2
DC current of gates (proportional to Vx) help reduce powersupply-level fluctuations R1 R1 V = VDD For turn on V = VDD for turn off + R1 R2 R2
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
10
Model for CMOS Power Distribution Network
POWER SUPPLY Lcon 2 1 L n cap 1 R n cap n Ccap Lcon 2 Lmod 2 BOARD MODULE Lmod 2
+ VDD -
Cboard
- n decoupling capacitors - Lcon is due to power connectors at edge of board - Cboard is intrinsic power and ground capacitance
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
11
Impedance of Power Distribution Network
Influenced by Package and Bypass Cap
Increase in low-frequency due to resonance frequency of board connector Increase in the high-frequency impedance due to resonance frequency of decoupling capacitor Keep both resonance frequencies away from operating frequency
Zo
Frequency
ECE 497-JS, Spring 2004
Copyright by Jose E. Schutt-Aine , All Rights Reserved
12
Off-Chip Driver SSN Calculations
- Worst case on-chip delta-I noise generated at beginning of clock cycle - Main problem for on-chip drivers is lack of low-inductance return path - Off-chip drivers are the major source of SSN
Problem:
32 low-impedance CMOS buffers (RS << Zo) are switched simultaneously. In addition, the line impedance is 50 , rise time is 2 nsec, output swing is 5 V, and the allowed power-supply-level fluctuation is 0.25V
Solution:
First, calculate the rate of change of the output voltage from the voltage swing and rise time
dV 80% Vswing 80% 5V = = = 2V / n sec dt tr 2n sec
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
13
Off-Chip Driver SSN Calculations
The current driven into the transmission line is I=V/Zo and its rate of change is:
dI 1 dV 2V / n sec = = = 0.04 A / n sec 50 dt Z o dt
Total current transient for 32 drivers:
dITOT dI = N drv = 1.28 A / n sec dt dt dI Through a 1nH inductance the voltage drop is V = L = 1.28V dt
To guarantee a maximum of 0.25V voltage fluctuation, the effective inductance is
L=
ECE 497-JS, Spring 2004
V = 0.2nH dI / dt
Copyright by Jose E. Schutt-Aine , All Rights Reserved
On-Chip Interconnection Resistance
R Zin C l
R : series resistance per unit length C : shunt capacitance per unit length
Rl C Rl coth (1 + j ) 2 R Zin = Rl C (1 + j ) 2 R
For very high , arg(Zin ) 45
ECE 497-JS, Spring 2004 Copyright by Jose E. Schutt-Aine , All Rights Reserved
15
RC Transmission Line
R Zin C l
First order approximation:
2 If << 2 then RCl
Zi...