to Introduction NIOS II Custom Instructions
Custom instructions can accelerate time-critical software algorithms
Digital Systems Design
Custom Instructions in NIOS II Systems
Reduce a complex sequence of standard instructions to a single instruction implemented in hardware Optimize software loops for computation intensive applications
Custom logic configured in the NIOS II processor as a part of the ALU
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 16-1 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 16-2
Custom Instruction Overview
NIOS II custom instructions are custom logic blocks adjacent to the ALU in the processors data path
Generally described via an HDL
Custom Instruction Operation
The basic operation of NIOS II custom instruction logic is to receive input on the dataa and/or datab port, and drive out the result on its result port The custom instruction logic provides a result based on the inputs provided by the NIOS II processor Support for multiple types of instructions
Combinational Multi-cycle Extended Register file
Dr. D. J. Jackson Lecture 16-4
Provides an ability to tailor the NIOS II processor core to meet the needs of a particular application Can accelerate time critical software algorithms by converting them to custom hardware logic blocks Provide a means to experiment with hardware/software tradeoffs at any point in the design process
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 16-3
Electrical & Computer Engineering
Custom Instruction Block Diagram
Implementing Custom Instruction Software
For each custom instruction, the NIOS II integrated development environment (IDE) generates a macro in the system header file, system.h. You can use the macro directly in your C or C++ application code, and you do not need to program assembly to access custom instructions Software can also invoke custom instructions in NIOS II processor assembly language
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 16-5
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 16-6
1
Custom Instruction Types
Custom Instruction Types (continued)
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 16-7
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 16-8
Combinational Custom Instruction
Combinational custom instruction consists of a logic block that is able to complete in a single clock cycle The combinational custom instruction uses the dataa and datab ports as inputs and drives the results on the result port Because the logic is able to complete in a single clock cycle, control ports are not needed The only required port for combinational custom instructions is the result port
The dataa and datab ports are optional Included only if the custom instruction functionality requires input operands If the custom instruction requires only a single input port, dataa is used
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 16-9
Combinational Custom Instruction Port Timing
The NIOS II processor presents the input data on the dataa and datab ports on the rising edge of the processor clock The processor reads the result port on the rising edge of the following processor clock
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 16-10
Multi-Cycle Custom Instruction
or Multi-cycle sequential, custom instructions consist of a logic block that requires two or more clock cycles to complete an operation Additional control ports are required for multi-cycle custom instructions Multi-cycle custom instructions can complete in either a fixed or variable number of clock cycles
Fixed length: specify the required number of clock cycles during system generation Variable length: The start and done ports are used in a handshaking scheme
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 16-11
Multi-Cycle Custom Instruction Ports
The clk, clk_en, and reset ports are required for multi-cycle custom instructions The start, done, dataa, datab, and result ports are optional Implement only if the custom instruction functionality specifically needs them
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 16-12
2
Multi-Cycle Port Operation
The processor asserts the active high start port on the first clock cycle of the custom instruction execution At this time, the dataa and datab ports have valid values and remain valid throughout the duration of the custom instruction execution The start signal is asserted for a single clock cycle Fixed or variable length custom instruction port operation:
Fixed length: Once the custom instruction is started, the processor waits a specified number of clock cycles, and then reads result
For an n-cycle operation, the custom logic block must present valid data on the nth rising edge after the custom instruction is executed
Multi-Cycle Custom Instruction Timing
Variable length: The processor waits until the active high done port is asserted
The processor reads the result port on the clock edge that done is asserted The custom logic block must present data on the result port on the same clock cycle that the done port is asserted
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 16-13 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 16-14
Other Custom Instruction Types
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