D Master-slave flip-flop
Consists of 2 gated D latches
The first, master, changes its state while clock=1 The second, slave, changes its state while clock=0
Master Q Slave m D Q Qs
ECE380 Digital Logic
Flip-Flops, Registers and Counters: Flip-Flops
D Clock
D
Q
Q Q
Clk Q
Clk Q
38 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-1 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-3
Flip-flops
The gated latch circuits presented are level sensitive and can change states more than once during the active period of the clock signal Circuits (storage elements) that can change their state no more than once during a clock period are also useful Two types of circuits with such behavior
Master-slave flip-flip Edge-triggered flip-flop
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-2
Master-slave D flip-flop
When clock=1, the master tracks the values of the D input signal and the slave does not change When the clock signal changes to 0, the master stage stops following the changes in the D input signal At the same time, the slave stage responds to the value of Qm and changes states accordingly Since Qm does not change when clock=0, the slave stage undergoes at most one change of state during a clock cycle From an output point of view, the circuit changes Qs (its output) at the negative edge of the clock signal
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-4
Thus Qm follows any changes in D and Qs remains constant
1
Master-slave D flip-flop
Clock D Qm Q = Qs D clock Q Q
Edge-triggered flip-flop
The previous circuit responds on the positive edge of the clock signal A negative-edge triggered D flip-flop can be constructed by replacing the NAND with NOR gates
D clock Q Q clock D Q Q
Positive-edge-triggered D type flip-flop
Negative-edge-triggered D type flip-flop
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-5
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-7
Edge-triggered flip-flop
A circuit, similar in functionality to the master-slave D flip-flop, be can constructed with 6 NAND gates
1 P3 P1 5 Q clock D Q Q
Comparing D storage elements
D clock D Q Qa clock Qb D Qa Qc Q b Q c
clk Q D Q Q D Q Q
2 Clock 3
P2
6
Q
Positive-edge-triggered D type flip-flop 24 transistors
Dr. D. J. Jackson Lecture 25-6
D
4
P4
Electrical & Computer Engineering
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-8
2
Clear and preset inputs
It may be desirable to specifically set (Q=1) or clear (Q=0) a flip-flop Practical flip-flops often have preset and clear inputs
Generally, these inputs are asynchronous (they do not depend on the clock signal)
Preset D clock Clear
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-9
T flip-flop
The name T derives from the behavior of the circuit, which toggles its state when T=1
This feature makes the T flip-flop a useful element when constructing counter circuits T Q(t+1) 0 1 Q(t) Q(t)
Clock T Q T clock
Electrical & Computer Engineering
Q Q
As long as Preset=0, Q=1 As long as Clear=0, Q=0
Q Q
Positive edge triggered
Dr. D. J. Jackson Lecture 25-11
T flip-flop
Another flip-flop type, the T flip-flop, can be derived from the basic D flip-flop presented Feedback connections make the input signal D equal to the value of Q or Q und...