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16 Pages

### cs281_lec03a

Course: CS 281, Fall 2000
School: Drexel
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Word Count: 812

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Architecture Systems I Lecture 3a: Review of Digital Circuits and Logic Design Jeremy R. Johnson Anatole D. Ruslanov Lec 3a Systems Architecture I 1 Introduction Objective: To understand how the simple model computer from the previous lecture could be implemented using logic gates. Review of Boolean functions and expressions Review of logic gates Decoders, Encoders, and Multiplexors Reading: Appendix B...

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Architecture Systems I Lecture 3a: Review of Digital Circuits and Logic Design Jeremy R. Johnson Anatole D. Ruslanov Lec 3a Systems Architecture I 1 Introduction Objective: To understand how the simple model computer from the previous lecture could be implemented using logic gates. Review of Boolean functions and expressions Review of logic gates Decoders, Encoders, and Multiplexors Reading: Appendix B Sections 2 and 3 the COD3 textbook. References: Dewdney, The New Turing Omnibus (Ch. 3, 13, and 28). Lec 3a Systems Architecture I 2 Boolean Functions A Boolean variable has two possible values (true/false) (1/0). A Boolean function has a number of Boolean input variables and has a Boolean valued output. A Boolean function can be described using a truth table. There are 22n Boolean functions of n variables. Lec 3a s x0 x1 f 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 x0 f x1 0 0 1 1 1 s 1 Multiplexor function 3 Systems Architecture I Boolean Expressions An expression built up from variables, and, or, and not. y xy 0 1 0 1 0 0 0 1 x 0 0 1 1 x 0 0 1 1 y x+y 0 1 0 1 0 1 1 1 x 0 1 x 1 0 and or not Lec 3a Systems Architecture I 4 Boolean Expressions A Boolean expression is a Boolean function. Any Boolean function can be written as a Boolean expression s x0 0 0 1 1 0 0 1 1 x1 0 1 0 1 0 1 0 1 f 0 0 1 1 0 1 0 1 5 Disjunctive normal form (sums of products) For each row in the truth table where the output is true, write a product such that the corresponding input is the only input combination that is true Not unique 0 0 0 0 1 E.G. (multiplexor function) s x0 x1 + s x0 x1 + s x0 x1 + s x0 x1 1 1 1 Lec 3a Systems Architecture I Boolean Logic Boolean expressions can be simplified using rules of Boolean logic Identity law: A + 0 = A and A 1 = A. Zero and One laws: A + 1 = 1 and A 0 = 0. Inverse laws: A + A = 1 and A A = 0. Commutative laws: A + B = B + A and A B = B A. Associative laws: A + (B + C) = (A + B) + C and A (B C) = (A B) C. Distributive laws: A (B + C) = (A B) + (A C) and A + (B C) = (A + B) (A + C) DeMorgan's laws: A + B = A B and A B = A + B The reason for simplifying is to obtain shorter expressions, which leads to simpler logic circuits. Systems Architecture I 6 Lec 3a Simplification of Boolean Expressions Simplifying multiplexor expression using Boolean algebra s x0 x1 + s x0 x1 + s x0 x1 + s x0 x1 = s x0 x1 + s x0 x1 + s x0 x1 + s x1 x0 (commutative law) = s x0 (x1 + x1) + s x1 (x0 + x0) = s x0 1 + s x1 1 = s x0 + s x1 (distributive law) (inverse law) (identity law) Verify that the Boolean function corresponding to this expression has the same truth table as the original function. Systems Architecture I 7 Lec 3a Logic Circuits A single line labeled x is a logic circuit. One end is the input and the other is the output. If A and B are logic circuits so are: and gate A B A B or gate inverter (not) Lec 3a A Systems Architecture I 8 Logic Circuits Given a Boolean expression it is easy to write down the corresponding logic circuit Here is the circuit for the original multiplexor expression x0 x1 s Lec 3a Systems Architecture I 9 Logic Circuits Here is the circuit for the simplified multiplexor expression x0 x1 s Lec 3a Systems Architecture I 10 Nand Gates A nand gate is an inverted and gate x 0 0 1 1 y x|y 0 1 0 1 1 1 1 0 nand All Boolean functions can be implemented using nand gates (and, or, and not can be implemented using nand) x = x x Lec 3a Systems Architecture I 11 Decoder A decoder is a logic circuit that has n inputs (think of this as a binary number) and 2n outputs. The output corresponding to the binary input is set to 1 and all other outputs are set to 0. d0 b0 b1 d1 d2 d3 Lec 3a Systems Architecture I 12 Encoder An encoder is the opposite of a decoder. It is a logic circuit that has 2n inputs and n outputs. The outp...

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Drexel - CS - 281
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SEXANTISOCSMATERSCONVENSANTISOCOMATEROCONVENOAGE01.44444441795349341.333333373069763410.044977188110401.222222208976752.666666746139533.599999904632572.8888888359069842.7999999523162812.719862937927211.111111164093022.666666
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SEXANTISOCSMATERSCONVENSANTISOCOMATEROCONVENOAGE01.44444441795349341.333333373069763410.044977188110401.222222208976752.666666746139533.599999904632572.8888888359069842.7999999523162812.719862937927211.111111164093022.666666
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2.1340624e-001 7.5672327e-001 -5.2103639e-001 -6.0533025e-001 -1.3913797e-001 2.0693860e-001 -1.1231593e-001 4.0004556e-001 2.5331727e-001 5.0603659e-001 1.9155456e-001 1.1482365e+000 -5.2876239e-001 -1.2066207e+000 2.2735487e-001 4
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Name _ME363 Exam 3/Fall 2006Honor Statement:Signed:_1Name _Concept Questions: Problem 1: Problem 2: Problem 3: Problem 4:/40 _/10 /15 _/19 /16Total:/1002Name _For the Concept Questions, pleasethe correct answer.a. b. c. d.
Wisconsin - ME - 363
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Wisconsin - ME - 363
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