Lecture 332:437 5 Verilog Tutorial
Structural Hardware Models 4Valued Logic Delay Instantiation Wiring Test Benches Behavioral Models Concurrency Summary
Material from The Verilog Hardware Description Language, By Thomas and Moorby, Kluwer Academic Publishers
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The Verilog Hardware Description Language
Professor Don Thomas Carnegie Mellon University (CMU)
[e-mail] http://www.ece.cmu.edu/~thomas The Verilog Hardware Description Language, Fifth Edition is available from Kluwer Academic Publishers, http://www.wkap.com. Phone: [phone] This is not one cohesive presentation on Verilog. The slides contained here are collected from different CMU classes at various academic levels. These slides are provided as an alternate aid to learning the language. You may find them helpful. Send bug reports to the above address -- there are some! Use or reproduction of the information provided in this file for commercial gain is strictly prohibited. Explicit permission is given for the reproduction and use of this information in an instructional setting.
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Representation: Structural Models
t Structural models
x x
Are built from gate primitives and/or other modules They describe the circuit using logic gates -- much as you would see in an implementation of a circuit. Gate instances, wire names, delay from a or b to f. This is a multiplexor -- it selects one of n inputs (2 here) and passes it on to the output a nsel b f2 f1 f module MUX (f, a, b, sel); output f; input a, b, sel; and #5 g1 (f1, a, nsel), g2 (f2, b, sel); or #5 g3 (f, f1, f2); not g4 (nsel, sel); endmodule
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t Identify:
x x
sel f=
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a sel' + b sel
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Representation: Gate-Level Models
t Need to model the gate's:
x x
Function Delay Generally, HDLs have built-in gate-level primitives
t Verilog has NAND, NOR, AND, OR, XOR, XNOR, BUF, NOT, and some others
t Function
x
x
The gates operate on input values producing an output value
t Typical Verilog gate instantiation is:
optional
"many"
and #delay instance-name (out, in1, in2, in3, ...); and #5 g1 (f1, a, nsel); a comma here let's you
list other instance names and their port lists.
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Four-Valued Logic
t Verilog Logic Values
x
The underlying data representation allows for any bit to have one of four values 1, 0, x (unknown), z (high impedance) x -- one of: 1, 0, z, or in the state of change z -- the high impedance output of a tri-state gate. 0, 1 ... no question z ... A tri-state gate drives either a zero or one on its output...and if it's not doing that, its output is high impedance (z). Tri-state gates are real devices and z is a real electrical affect. x ... not a real value. There is no real gate that drives an x on to a wire. x is used as a debugging aid. x means the simulator can't determine the answer and so maybe you should worry! All values in a simulation start as x. Verilog keeps track of more values than these in some situations.
Thomas: Digital Systems Design Lecture 5
x x x
t What basis do these have in reality?
x x
x
t BTW ...
x
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Four-Valued Logic
t Logic with multi-level logic values
x
Logic with these four values make sense
t Nand anything with a 0, and you get a 1. This includes having an x or z on the other input. That's the nature of the nand gate t Nand two x's and you get an x -- makes sense!
x
Note: z treated as an x on input. Their rows and columns are the same If you forget to connect an input ... it will be seen as an z. At the start of simulation, everything is an x. Input B Nand 0 1 x z 0 1 1 1 1 1 1 0 x x x 1 x x x z 1 x x x Input A A B A 4-valued truth table for a Nand gate with two inputs
x x
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Delay
t Transport delay -- input to output delay
x
"nand #35 (f1, a, b, c);"
#35 is the transport delay
t What if the input changes during that time?
x x
i.e., how wide must an input spike be to affect the output? Think of the gate as having inertia. -- The input change must be present long enough to get the output to change. (That "long enough" time is called inertial delay) in Verilog, this time is equal to the transport delay a b
x
a b
c
c pulse too small, no output change a b c
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-- transport delay
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Let's Build a Wider 2-bit MUX
t Build a 2-bit 2:1 MUX
x
OK, let's put two 1-bit 2:1 MUXes in the same module with a common select line What would it look like?
x
a0 b0 f0 a f a1 b1 f1 b sel
sel
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Reuse!
t Reuse of smaller objects
x x x
Can we use the MUX module that we already designed? A big idea -- instantiation Modules and primitive gates can be instantiated -- copied -- to many sites in a design Previously, two ANDs, one OR, and a NOT gate were instantiated into module MUX Now we instantiate two copies of module MUX into module wideMux Instantiate two MUX modules, name them, and specify connections (the order is important).
x
x
module wideMux (f1, f0, a1, a0, b1, b0, sel); input a1, a0, b1, b0, sel; output f1, f0; MUX endmodule
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bit1 (f1, a1, b1, sel), bit0 (f0, a0, b0, sel);
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Instantiation -- Copies
t Modules and gate primitives are instantiated == copied
x
Note the word "copies"
t The copies (also called instances) share the module (or primitive) definition t If we ever change a module definition, the copies will all change too t However, the internal entities (gate names, internal port names, and other things to come) are all private, separate copies
x
Don't think of module instantiations as subroutines that are called
t They are copies -- there are 2 MUX modules in wideMux with a total of: ______ AND gates, ______ OR gates, ______ NOT gates
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2 2
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Why Is This Cool?
t In Verilog
x x x
"Primitive" gates are predefined (NAND, NOR, ...) Other modules are built by instantiating these gates Other modules are built by instantiating other modules, ... Bigger modules of useful functionality are defined You can then design with these bigger modules
t You can reuse modules that you've already built and tested t You can hide the detail -- why show a bunch of gates and their interconnection when you know it's a mux!
t The design hierarchy of modules is built using instantiation
x x
t Instantiation & hierarchy control complexity.
x x
No one designs 1M+ random gates -- they use hierarchy. What are the software analogies?
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How to Wire Modules Together
t Real designs have many modules and gates
module putTogether (); wire w1, w2, w3, w4; bbb aaa ... module bbb (i1, i2, o1, clk); input i1, i2, clk; output o1; lucy ricky (w1, w2, w3, w4); (w3, w2, w1); what happens when out1 is set to 1?
module aaa (in1, out1, out2); input in1; output out1, out2; ... nand nand ... #2 (out1, in1, b); (out2, #6 in1, b);
xor (o1, i2, ...); ... Each module has it's own namespace. Wires connect elements of namespaces.
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Implicit Wires
t How come there were no wires declared in some of these modules?
x x
Gate instantiations implicitly declare wires for their outputs. All other connections must be explicitly declared as wires -- for instance, connections between module ports Output and input declarations are wires module mux (f, a, b, sel); output f; input a, b, sel; and #5 or #5 not endmodule g1 (f1, a, nsel), g2 (f2, b, sel); g3 (f, f1, f2); g4 (nsel, sel);
x
module putTogether (); wire w1, w2, w3, w4; mux aaa ... inst1 (w1, w2, w3, w4); duh (w3, w2, w1);
wires explicitly declared
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wires implicitly declared (f1, f2, nsel)
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How to Build and Test a Module
t Construct a "test bench" for your design
x
Develop your hierarchical system within a module that has input and output ports (called "design" here) Develop a separate module to generate tests for the module ("test") Connect these together within another module ("testbench") module design (a, b, c); input a, b; output c; ... module test (q, r); output q, r; initial begin //drive the outputs with signals ...
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x
x
module testbench (); wire l, m, n; design d (l, m, n); test t (l, m); initial begin //monitor and display ...
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Another View of This
t 3 chunks of Verilog, one for each of:
TESTBENCH is the final piece of hardware which connects DESIGN with TEST so the inputs generated go to the thing you want to test...
Another module, called TEST, to generate interesting inputs
Your hardware called DESIGN
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An Example
Module testAdd generated inputs for module halfAdd and displayed changes. Module halfAdd was the design
module tBench; wire su, co, a, b; halfAdd ad (su, co, a, b); testAddtb (a, b, su, co); endmodule module testAdd (a, b, sum, cOut); input sum, cOut; output a, b; reg a, b; initial begin $monitor ($time,, "a=%b, b=%b, sum=%b, cOut=%b", a, b, sum, cOut); a = 0; b = 0; #10 b = 1; #10 a = 1; #10 b = 0; #10 $finish; end endmodule
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module halfAdd (sum, cOut, a, b); output sum, cOut; input a, b; xor #2 and #2 endmodule
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(sum, a, b); (cOut, a, b);
Thomas: Digital Systems Design Lecture 5
The Test Module
t It's the test generator t $monitor
x x
prints its string when executed. after that, the string is printed when one of the listed values changes. only one monitor can be active at any time prints at end of current simulation time at time zero, print values and set a=b=0 after 10 time units, set b=1 after another 10, set a=1 after another 10 set b=0 then another 10 and finish
module testAdd(a, b, sum, cOut); input sum, cOut; output a, b; reg a, b; initial begin $monitor ($time,, "a=%b, b=%b, sum=%b, cOut=%b", a, b, sum, cOut); a = 0; b = 0; #10 b = 1; #10 a = 1; #10 b = 0; #10 $finish; end endmodule
x
x
t Function of this tester
x
x x x x
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Another Version of a Test Module
t Multi-bit "thingies"
x
test is a two-bit register and output It acts as a two-bit number (counts 0001-10-11-00...) Module tBench needs to connect it correctly -- mod halfAdd has 1bit ports.
module testAdd (test, sum, cOut); input sum, cOut; output [1:0] test; reg [1:0] test; initial begin $monitor ($time,, "test=%b, sum=%b, cOut=%b", test, sum, cOut); test = 0; #10 test = test + 1; #10 test = test + 1; #10 test = test + 1; #10 $finish; end endmodule Connects bit 0 or wire t to this port (b of the module halfAdder)
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x
x
module tBench; wire su, co; wire [1:0] t; halfAdd testAdd endmodule
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ad (su, co, t[1], t[0]); tb (t, su, co);
Thomas: Digital Systems Design Lecture 5
Another Version of testAdd
t Other procedural statements
x
You can use "for", "while", "if-then-else" and others here.
module testAdd (test, sum, cOut); input sum, cOut; output [1:0] test; reg [1:0] test; initial begin $monitor ($time,, "test=%b, sum=%b, cOut=%b", test, sum, cOut); for (test = 0; test &l...