Register now to access 7 million high quality study materials (What's Course Hero?) Course Hero is the premier provider of high quality online educational resources. With millions of study documents, online tutors, digital flashcards and free courseware, Course Hero is helping students learn more efficiently and effectively. Whether you're interested in exploring new subjects or mastering key topics for your next exam, Course Hero has the tools you need to achieve your goals.
20 Pages
cache-advanced
Course: CS 2410, Fall 2008School: Pittsburgh
Rating:
Word Count: 2324
Document Preview
Asmall,fullyassociativecachebetween VictimCache acacheandits fillpath Victimcachecontainsblocksdiscardedfromamiss(so calledvictims) Victimcachecheckedonamissfordatabeforegoing tolowerlevel , p OnamissandhitinVC,swapvictimblockwithblockin cache Noclockrateeffect! VictimCacheArchitecture Address Data in CPU Data out = Tag Data Victim Cache Vi i C h Write Buffer = Lower Level Page 1 VictimCache...
Unformatted Document Excerpt
Coursehero >> Pennsylvania >> Pittsburgh >> CS 2410Course Hero has millions of student submitted documents similar to the one
below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.
Course Hero has millions of student submitted documents similar to the one
below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.
Asmall,fullyassociativecachebetween VictimCache
acacheandits fillpath Victimcachecontainsblocksdiscardedfromamiss(so calledvictims) Victimcachecheckedonamissfordatabeforegoing tolowerlevel , p OnamissandhitinVC,swapvictimblockwithblockin cache Noclockrateeffect!
VictimCacheArchitecture
Address Data in CPU Data out
=
Tag Data Victim Cache Vi i C h Write Buffer
=
Lower Level
Page 1
VictimCache
Improvesmissratebykeepingblocksthatmight havebeenmistakenlyevicted Effectivelyincreasesassociativity reducesthe conflictmisses Afourentryvictimcacheworkswell
20 95%ofconflictmissesina4KBdirectmapped cacheareremoved h d
Typicallyusedwithdirectmappedcacheto achieveeffectofasetassociativecache
PseudoAssociativeCaches
Speedofdirectmappedwithmissrateoftwowayset associativecache Workslikeadirectmappedcacheinitially
Checkappropriateentryforahit Ifahit,returndata
Onamiss
Checkanothercacheentryinsamelevel forahit Thesecondentrysindexisformedbyinvertingmost significantbitofindexfield Noclockrateeffect speedofDMforfirstaccess
Page 2
PseudoAssociativeCaches
Fasthit:Hitsinthefirstentry(speedofDM) Slow hit (pseudo hit): Hits in the second entry Slowhit( pseudohit ):Hitsinthesecondentry Fasthitsindirectmappedcachecanbecome slowhitsinthepseudoassociativecache Whathappenswhenwehavelotsofslowhitsfor thesamedata? h d ? Swapfasthitentryandpseudohitentryona pseudohit(maycausethrashing)
HardwarePrefetching
Prefetching:Loaditemsbeforetheyareneeded
Instructionsanddata Loadedintocacheorbufferbetweenupperandlowerlevels
Instructionprefetching (onepossiblescheme)
Onamiss,getmissedblockandnextsubsequentblock Holdsubsequentblockinbufferuntilneeded(avoidsevictinga possiblyneededblock) Onamisstoaprefetched block,itiscopiedfromthe p , p instructionstreambuffertothecache 4blocksininstructionstreambuffer:instructionhitrate increasesby50%
Page 3
DataPrefetching
Applythesameidea On a miss prefetch the next block Onamiss,prefetch thenextblock
Atwist:Detectdataaccesspattern E.g.,strideofarrayaccesses Prefetch thenextpredictedblockbasedonthepast dataaccesspattern(stride)
Multiplestreambuffersfordata
Eachprefetch atadifferentaddress 4buffersincreasedatahitrateby43%
SoftwarePrefetching
Compilerinsertsprefetch instructions
Registerprefetch:Prefetched dataloadedintoaregister g p g Cacheprefetch:Prefetched dataloadedintothecache
Requiressomesupport
Nonfaultingprefetch instructions(nonbindingprefetch) Nonblocking caches:processorcancontinuewhile prefetching thedata
Overlapexecutionwithprefetching ofdata
Loops scheduleprefetches onearlieriterationssodata availableonlaterones(unrolling,softwarepipelining)
Page 4
ReducingCacheMissPenalty
Muchresearch hasfocusedoncachemissrates Butthelatencyofamissalsomatters Youcantreallyseparatethetwotogeta meaningfulunderstandingofwhatishappening A number of optimizations on how to handle Anumberofoptimizationsonhowtohandle missestoimprovetheirlatency Also,decreasethelatencyofthelowerlevel!
ReadPriorityoverWrite
Writethroughcache writebufferavoidsstalling Writebuffermayholdavaluethatisbeingloaded y g Readmisscanwaitforbuffertoempty
forWTcache,WB(fewwords)almostalwayshasdatainit Dontwait:Checkcontentsofwritebufferbeforesendingthe readmisstoalowerlevel
Writebackcosts wholecachelinewritten
On replacement write old line copy new line CPU executes Onreplacement,writeoldline,copynewline,CPUexecutes Better:moveoldlinetoawritebuffer,copynewline,CPU executes,writeoldlinetomemorywhenbusavailable Onamiss,CPUmustcheckthewritebuffer
Page 5
SubblockPlacement
Largeblocksconsumebandwidthbutsmalltags g g Biggerlines smallertagsforagivencapacity Useasingletag,butsubdividetheline
Lesstagmemory asingletagcorrespondstotwosub lines
Validbitpersubblock(line) On a read miss only load the needed sub block Onareadmiss,onlyloadtheneededsubblock
Tag V Block V Block V Block V Block
EarlyRestart CriticalWordFirst
CPUjustneedsoneword Why wait for entire cache line? Whywaitforentirecacheline? Earlyrestart senddatatoCPUdirectlyfrom memoryonareadmiss(nosecondaccess) Criticalwordfirst requestmissedwordfirstand fillcachelinewhileCPUexecuting Benefitsdesignswithlongcachelines(or,rather, cachefilltimeishighrelativetoCPUspeed)
Page 6
LockupFreeCaches
Outofordercompletion
DontstallCPUwaitingforcachemisstobeserviced g Continueexecutinginstructions
Lockupfreecache:Allowsdatacachetocontinue supplyingcachehitsduringcachemisses hitunder miss Multiplemisses:Cacheoverlapsmisshandlingof separatemisses(buffersloads) Multipleoutstandingaccesses:Complexity!
Blockingvs.LockupFreeCache
integer floating point ratio of memory stall time for blocking vs. lock-up free
Page 7
SecondLevelCaches
Tradeoff
MakeL1cachefastertokeepupwithCPU p p MakeL1cachelargertoreducemissrate
Whatstheexpenseofdoingthis? Instead,dobothbyaddingaL2cache
Firstlevel:Fastandsmall:keepsupwithCPU Secondlevel:Capturesmanymissesthatwouldgotomain p y g memory ReducesmisspenaltyofL1 Hardwareisrelativelystraightforward
Addadditionalcacheunitbetweenfirstlevelandmainmemory.
PerformanceAnalysis
Secondlevelmissratemeasuredonmissesfrom the first level cache thefirstlevelcache Localmissrate Numberofmissestothecache dividedbytotalnumberofmemoryaccesses Globalmissrate Numberofmissesincache dividedbytotalnumberofmemoryaccesses generatedbytheCPU(2ndlevelsglobalmissrate is:MissrateL1 *MissrateL2 )
Page 8
PerformanceAnalysis
Extendthememoryaccesstimeforonelevel cachetohandletwolevels h t h dl t l l Howcanwecomputetheoverallaccesstimefor bothlevelsofcache?
PerformanceAnalysis
L1averageaccesstimeis??? g
Time =HittimeL1 +MissrateL1 *MisspenaltyL1
ForL2,weknowthat
MissrateL1 israteofaccesses toL2 MisspenaltyL1 isaverageaccesstime forL2
WecanrewritemisspenaltyL1 intermsofL2 p y
MisspenaltyL1 =HittimeL2 +MissrateL2 *MisspenaltyL2
Then,overallaccesstimeis
Time=HittimeL1+MissrateL1*(HittimeL2+MissrateL2*MisspenaltyL2)
Page 9
L1vs.L2
Goalis:Fasthitswithfewmisses(smallglobal missrateoverall) miss rate overall) L1:Hittimesarecritical clockcycleimpact L2:Missratesarecritical avoidmemoryaccess Thus,L1focusesonreducinghittime,whileL2 focusesonreducingmissrate
L1vs.L2
Withinclusion,L2size>L1size
Somewhat larger L2: High local miss rate SomewhatlargerL2:Highlocalmissrate Hence,moderatelybigL2cachesarethenorm
Tendtohave>2wayassociativity L2associativity
(MRvs.hittime)
Different block sizes in L1 vs L2 DifferentblocksizesinL1vs.L2
L2mayfavorlargerblocksize(B/Wtomemory) Butforinclusion:MustinvalidateallblocksinL1 thatmaptothelargerL2block
Page 10
ReducingHitTime
Tagcomparisonisexpensivepartofhittime
Readtagmemory,comparetagtoaddress g y, p g
Smallandsimplecaches Small:Keepcachesmallenoughsoitfitsentirelyon chip avoidtheoffchipaccessexpense Simple:Directmappedcaches
Overlaptagcomparisonwithdeliveryofdata p g p y
Highclockrates:Encouragessmallcachesthatcanbe accessedinasinglecycle
AvoidAddressTranslation
Virtualaddress
Mapslogicaladdresstophysicaladdressinmemory p g p y y Virtualaddressondiskmappedtophysicaladdressinmain memory
Hitsmorecommonthanmisses
Avoidaddresstranslationsincemostarehits Arguesforcachingonvirtualaddress(virtualcache)
Virtual vs.physicalcache
Addressedusingvirtualaddress(tagcomparisononvaddr.) Noaddresstranslationbeforecacheaccess
Page 11
VirtualAddressTranslation
Virtual page number Page offset
Main memory Page table
Map logical address into a physical address located in memory
VirtualAddressTranslation
Virtual page number Page offset
Page table
Cache
Main memory
Physical cache - after mapping address
Page 12
VirtualAddressTranslation
Virtual page number Cache Main memory Page table Page offset
Virtual cache - addresses based virtual address
Disadvantages:VirtualCaches
Whathappenswithacontextswitch???? Onprocessswitch,cachemustbeflushed sincevirtual addressesfromoneprocessmaptoanother Howcanweavoidtheambiguity???? Avoidingflushes
AttachPIDtocacheaddresstag OnlyflushwhenaPIDisreassigned
Page 13
Disadvantages:VirtualCaches
Anotherproblem aliasing
OSanduserprogramsmayusedifferentvirtualaddresses p g y forthesamephysicaladdress Twocopiesofdataincacheatonce Mustupdateboth;orensurethateveryblockhasan uniquephysicaladdress(noduplicates)
Yetanotherproblem I/Olivesinphysicaladdress space
I/Ophysicaladdresseswouldhavetobemappedtovirtual addressesforavirtualcache MappingneededtotellthatanaddressisinI/Ospace
Solutions:VirtualCaches
Fasthits:Separatetranslationandcacheaccess
Separate pipeline stages Separatepipelinestages
Addresstranslationstage Cacheaccessstage(withphysicaladdress)
Fastcycletimewithslowcacheaccess(2cycles)
I.e.,increasedaccesstimewithafastclockrate
Increasesmisprediction branchpenalty
Afinalsolution:Usepageoffsettoindexcache
Socalledvirtuallyindexed,physicallytagged UsedinAlpha21064andothers
Page 14
VirtuallyIndexed,PhysicallyTagged
Virtual page number Page offset
Cache Page table
Main memory
=
Hit/miss
Page offset indexes cache, tags checked after address translation finishes
VirtuallyIndexed,PhysicallyTagged
Features
Tagcomparisononphysicaladdress Tagreadcanbe overlapped withaddresstranslation
Operation
Pageoffsetisnottranslatedduringvirtualaddresstranslation Readingtagsdoneconcurrentlywithaddresstranslation Tagcomparisonoccursonphysicaladdressaftertranslation
Limitation
DMcachecanbenolargerthanapagesize Increaseassociativity tokeepindexwithinonepagesize
Page 15
PipeliningWrites
Writehitstakelongerthanreads why???? Tagcomparisonbeforewritingthedata Pipeliningwrites
Separatetaganddatamemories On a write compare with tag Onawrite,comparewithtag Withadifferent address,awritecanproceedonaline withthetagcomparison I.e.,tagcomparisonforwriteI andwriteforwriteI1
OutofOrderProcessors
(ABriefTangent)
OOOhidessomeportionofmisslatency Whatthenisthemisslatency?
Theendtoendlatencyofamiss? Thecyclesthathavestalls?
Trytodefineas:
Memstalls/instr= Misses/instr*(Totalmisslat. overlappedmisslat.)
Page 16
OutofOrderProcessors
(ABriefTangent)
Itsnotquitesoobvious! Lengthofmemorylatency
Whatisthestartandendofamemoryoperation? Ininstructionwindow,addressgenerated,orsenttomemory
Lengthoflatencyoverlap
Whenisthereoverlap? Orhowdoweknowwhenamemoryopstallstheprocessor? Whotoattributethestallto?
OutofOrderProcessors
(ABriefTangent)
Anoptimizationforthememorysystem(or p ) y othercomponents)maynot havethe dramaticeffectthatyouexpect E.g.,ifwecancoverthemajorityofmisses, thenreducingthemisspenaltymaynothave asmuchaneffectasaveragememoryaccess timepredicts. Letsstickwiththeoriginaldefinitions. Wecansimulatewhennecessary.
Page 17
BlockSizeExample
40cyclememoryoverhead,16bytesdelivered every2cycles. E.g.,16bytesin42cycles,32bytesin44cycles Baselinecachesmissrates
1K,32Bline:13.34% 64K,32Bline:1.35% 1K,64Bline:13.76% 64K,64Bline:1.06%
Whatblocksizehastheminimumaccesstimefor thesefourcaches?
BlockSizeExample
Misspenaltybasedonlinesize whatisit???
32B:40cycleoverhead+(32/16)*2cycles=44cycles 64B:40cycleoverhead+(64/16)*2cycles=48cycles
Averagememoryaccesstime
Time=Hittime+Missrate*Misspenalty
1K,32B: 1cycle+(13.34%*44cycles)= 6.870cycles 1K,64B: 1cycle+(13.76%*48cycles)= 7.605cycles 64K,32B: 1cycle+(1.35%*44cycles)= 1.594cycles 64K,64B: 1cycle+(1.06%*48cycles)= 1.509cycles
Page 18
AssociativityExample
Supposeincreasingassociativity effectstheclockrate:
2way 2 way 4way 8way 10%penalty (1.1 base clock time) 10% penalty (1 1 *baseclocktime) 12%penalty (1.12*baseclocktime) 14%penalty (1.14*baseclocktime)
Hittimeis1clockcycle,misspenaltyfordirectmapped cacheis50cycles Missratesfora16Kcache
DM: 2.9% 4way: 2.0% 2way:2.2% 8way: 1.8%
Whatistheaccesstimeforeachcache?
AssociativityExample
Time=Hittime+Missrate*Misspenalty
DM: 2way: 4way: 8way: 1.0+2.9%*50= 1.1+2.2%*50= 1.12+2.0%*50= 1.14+1.8%*50= 2.45 2.2 2.12 2.04
Page 19
SecondLevelCacheExample
2waysetassociativeincreasesCPUclockcycle timeby10%(thus,hittimegoesupby10%) time by 10% (thus hit time goes up by 10%) HittimeforL2directmappedis10cycles LocalmissrateforL2DMis25% Localmissratefor2wayassociativeis20% MisspenaltyforL2is50cycles Whatstheimpactofthesecondlevelcaches associativity ontheL1cachesmisspenalty?
SecondLevelCacheExample
FordirectmappedL2cache,L1smisspenaltyis: MisspenaltyL1=L2hittime+L2missrate*L2misspenalty MisspenaltyL1=10+25%*50=22.5clockcycles
Letsaddassociativity 10%clockcyclepenalty,20%L2missrate: MisspenaltyL1=10.1+20%*50=20.1clockcycles
Clockcyclehastobeanintegralnumberofcycles,so10or11: MisspenaltyL1=10+20%*50=20.0clockcycles MisspenaltyL2=11+20%*50=21.0clockcycles
Page 20
Find millions of documents on Course Hero - Study Guides, Lecture Notes, Reference Materials, Practice Exams and more.
Course Hero has millions of course specific materials providing students with the best way to expand
their education.
Below is a small sample set of documents:
Below is a small sample set of documents:
Pittsburgh - CS - 0447
Pipelining How do we improve on the performance of the multi-cycle implementation? Key observation we can be doing multiple things at once Pipelining implementation technique to execute multiple instructions simultaneouslyPipelining is Natural! L
Acton School of Business - RUF - 102
1 (v) to cause to hear, to tell, to narrate (v) to leave, to let go (v) to think, to reect (nm) complaint, reproach (adj + nm) false, hypocritical, lying (v) to be broken, to break (on its own), to crack (nm) glass, bottle, mirror (nm) toy (pron
Laurentian - COSC - 4806
4/3/2009In this lecture IndexesWeb Data ManagementIndexes XSet Region algebras Indexes for Arbitrary Semistructured Data Dataguides T-indexes Index FabricResourcesIndex Structures for Path Expressions by Milo and Suciu, in ICDT'99
Texas A&M - MATH - 150
Math 150, Fall 2008, c Benjamin AurispaChapter 2, Continued2.4 Transformations of FunctionsThis section tells how transformations change the graph of a function. It is very useful in graphing functions, when you know its general shape. 1. Vertica
Texas A&M - MATH - 150
Math 150, Fall 2008, c Benjamin AurispaChapter 3, continued3.4 Complex NumbersThis section involves the imaginary number i. i= This means that i2 = 1 A complex number is an expression of the form a + bi, where a and b are real numbers. a is calle
Texas A&M - MATH - 150
Math 150, Fall 2008, c Benjamin AurispaChapter 5, continued5.3 Trigonometric GraphsDefinition: A function f is called periodic if it repeats itself over and over. Mathematically, there is a positive number p such that f (t + p) = f (t) for every
Acton School of Business - SPAC - 205
Light = Electromagnetic wave - a disturbance propagating in the ether with velocity c Ether: Penetrates "ponderable" matter but does not interact with it Is devoid of all physical properties (i.e., mass, density, etc.) expect that it defines a fr
Texas A&M - MATH - 609
MULTI-PARAMETER ITERATION(CONTINUED) Math. 609, Fall 2008 (updated: September 16, 2008) We continue the analysis of the multi-parameter iteration in the case when A is symmetric and positive definite and we have bounds on the spectrum, 0 < 0 , fo
Texas A&M - MATH - 311
MATH 311-504 Topics in Applied Mathematics Lecture 10: Inverse matrix (continued). Determinant.Inverse matrix Denition. Let A be an nn matrix. The inverse of A is an nn matrix, denoted A1 , such that AA1 = A1 A = I . If A1 exists then the matrix A
Texas A&M - MATH - 304
Math 304504 Linear Algebra Lecture 6: Inverse matrix (continued).Identity matrix Denition. The identity matrix (or unit matrix) is a diagonal matrix with all diagonal entries equal to 1. The nn identity matrix is denoted In or simply I . 1 0 0 1
Texas A&M - MATH - 166
Math 166, Spring 2008, c Benjamin AurispaChapter 9, Continued9.4 Game TheoryA zero-sum game is a game in which payo to one player results in an equal loss to the other. We will represent the possible scenarios of a game using a matrix, called a p
Acton School of Business - CAAM - 420
This code included with latex macro using verbatiminput\documentclass{article} % use the verbatim package \usepackage{verbatim} % define a macro myinput which takes as argument % your .c files name \newcommand{\myinput}[1] {\hrule\small\verbatiminpu
Texas A&M - AGEC - 677
Texas A&M - AGEC - 606
AgEc 606 (day 16): 3/12/20097. Water Marketing The term water marketing applies to natural water only unprocessed, except possibly for onstream storage does not apply to infrastructure the water pricing topic is better applied to wholesale and
Texas A&M - AGEC - 606
AgEc 606 (day 9): 2/17/2009InstitutionsI. Institutional Economics II. Water Institutions property forms first theorem of W. E. market failure property theory surface water doctrines ground water doctrines conjunctive management compacts
Texas A&M - MATH - 141
Math 141 WIR, Spring 2007, c Benjamin AurispaMath 141 Exam 1 Review Problem SetNote: Not every topic is covered in this review. Please also take a look at the previous Week in Reviews for more practice problems. 1. Find the equation of the line th
Acton School of Business - ECON - 508
Existence of an Equilibrium for a Competitive Economy Kenneth J. Arrow; Gerard Debreu Econometrica, Vol. 22, No. 3. (Jul., 1954), pp. 265-290.Stable URL: http:/links.jstor.org/sici?sici=0012-9682%28195407%2922%3A3%3C265%3AEOAEFA%3E2.0.CO%3B2-B Econo
UCSD - ECE - 111
ECE111 Winter 2009 Project 1 Due on Jan.15th Thursday in class Jan 15 Thursday, Finish Tutorial 1 before starting Project 1. Project 1 is the design of a Fibonacci calculator using Verilog HDL.Fibonacci (cont ) (cont.) F(n) = 0 when n=0 F(n) =
Pittsburgh - CS - 0016
CS 0016 : Intro to Programming Spring 2009 Lab 3 : Event Procedure1. Assignment 1.1 Launch Visual Basic Studio 2008, and create a project (Project name is Lab3) 1.2 Add the following controls (See Figure. 1) and define the properties in the Properti
Texas A&M - CPSC - 604
Programming Languages, CPSC 604-Slides 13Bounded QuantificationJaakko JrviApril 9, 20091 / 32IntroductionOutline1Introduction2Why F-bounds?2 / 32IntroductionBounded quantificationCombining subtyping and polymorphism Straigh
Acton School of Business - COMP - 210
From Programs to Executions: An Odyssey in Language Translation(with examples in Scheme)Keith D. CooperRice University Houston, Texas December 2000Copyright 2000, Keith D. CooperAn Example Sum the seriesn + n-1 + n-2 + + 1In Scheme, we mi
Acton School of Business - COMP - 210
From Programs to Executions: An Odyssey in Language Translation(with examples in Scheme)Keith D. CooperRice University Houston, Texas December 2000Copyright 2000, Keith D. CooperWhat commands does the "computer" run? Computer's instruction se
Texas A&M - AGECON - 350
Lecture 5A break down of valueTotal Economic ValueUse ValueNon-use ValueDirect UseIndirect UseBequest ValueExistence ValueOption ValueExtractive UsesNon-extractive UseAdapted from Asafu-Adjaye, J. Environmental Economics for No
Texas A&M - AGECON - 350
AGEC 350 Reading Guide Lecture #12 due October 19, 2006 Questions based on A Guide to Market-Based Approaches to Water Quality, available from the class home page: http:/agecon2.tamu.edu/people/faculty/woodward-richard/350/NNGuide.pdf1. What is the
Acton School of Business - CENG - 301
Problem #1 Mid Term Exam 2004a) Normally steady state except during startups or changing operations. Open non-reactiveb) Dynamic if there are plants present Open Reactivec) Dynamic if people are living in it Closed unless people an
Acton School of Business - PHYS - 112
Pittsburgh - IE - 3078
IE 3078: Convex Optimization Spring 2009 Syllabus Basic informationInstructor: Oleg Prokopyev, prokopyev@engr.pitt.edu Lectures: MW 3:00-4:15 pm Classroom: Benedum 1020 Office: Benedum 1037 Office hours: TBA Course website: http:/www.engr.pitt.edu/i
Pittsburgh - IE - 3078
IE 3078 Homework #2Due on Wednesday, February 11th at the beginning of class. 1. Prove Theorem 2.1.6 from the book. 2. (Defining the class of strongly convex function) Consider a hypothetical class of functions F satisfying the following assumptions
Pittsburgh - IE - 3078
IE 3078 Homework #1Due on Wednesday, February 4th at the beginning of class. 1. Show that function f (x) in the proof of Theorem 1.1.2 from the text is the constant L and its global optimal value is - . -Lipschitzcontinuous with2. Show that a
Pittsburgh - IE - 3078
IE 3078 Homework #3Due on Wednesday, March 18th at the beginning of class. 1. Consider the convex function f dened on Rn by +, 2, x2 , f (x) = x, +, Compute f (x). 2. Consider the problem min{f (x) : x Q}, where f is convex and Q is a cl
Pittsburgh - ENGR - 0715
Development of Hill District "Green-Up" Space Walking Route - Gantt ChartIDNameStartFinishTue 27 Wed 28January 2009 Thu 29 Fri 30 Sat 31 Sun 01 Mon 02 Tue 03 Wed 04 Thu 05 Fri 06 Sat 07 Sun 08 Mon 09 Tue 10 Wed 11 Thu 12 Fri 13February 2
Pittsburgh - ENGR - 0715
ENGR 0715: Engineering Applications for Society University of PittsburghTEAM 7Progress Report #10 Team Meeting Date: March 31, 2009 Meeting Roles Primary Facilitator Secondary Facilitator Scribe TimekeeperTeam Members: Rebecca McGinley (ram119@p
Pittsburgh - ENGR - 0715
What is a GreenUp Lot? The goal of the Green-Up lots is to create open recreational areas for the benefit of Hill District residents. The lots will serve as areas of vegetation and green growth, helping to balance the human and natural environments i
Pittsburgh - ENGR - 0715
Development of Hill District Green-Up Lot Walking TrailsNamesRebecca McGinley Blair Suter Michael Sweriduk Declan WilsonE-mailram119@pitt.edu bcs27@pitt.edu mes176@pitt.edu dww13@pitt.eduPhone(512) 971-8193 (304) 550-6078 (215) 767-0973 (412)
Texas A&M - GEOG - 390
GEOG 390/GEOG 660 Lab Assignment 02 IntroductionDr. Andrew KleinThis lab will serve as an introduction to GIS using ArcMap. This lab will also offer the opportunity to get your feet wet though we will not throw you in the deep end in problem so
Texas A&M - GEOG - 404
Being and Becoming a Geographer: An Agenda for Geography EducationRoger M. Downs Department of Geography, The Pennsylvania State Universityndicators of the health of geography as a field can be interpreted in tw o ways. O n the one hand, there is
Wisconsin - ME - 368
ME 368 Digital OscilloscopeA3 - Figure Questions2. The figure below shows an actual signal of precisely 1.000 kHz. Add dots at the locations you would expect data points to appear if the time per point was 1.000 ms.b. The figure below shows an
Pittsburgh - SOC - 0150
Soc 0150 Notes for April 18 Recorded by Brandon Dinney Background of Frankfurt School -explain why if proliferation of productivity and liberation why there wasnt a revolution (of proletariat) +expect Depression would have effect of consciousness of
Pittsburgh - CS - 1567
CS1567 Intermediate Programming and System Design Using a Mobile Robot Lab 0: Java Warm-upIn this course, we will be programming in Java. As an object-oriented programming language, Java is similar in many ways to C+, so you will be able to start us
East Los Angeles College - LEED - 2110
A Curry with a Difference You are an employee with the Leeds branch of NCH. The company's fundraising team is acknowledged as one of the best in the charity sector. They have corporate partnerships with, for example Barclays, HP, Tesco, TK Maxx and
Pittsburgh - SIS - 2720
GSM PHASE 2+ GENERAL PACKET RADIO SERVICE GPRS: ARCHITECTURE, PROTOCOLS, AND AIR INTERFACECHRISTIAN BETTSTETTER, HANS-JRG VGEL, AND JRG EBERSPCHER TECHNISCHE UNIVERSITT MNCHEN (TUM) ABSTRACTThe General Packet Radio Service (GPRS) is a new bearer se
Pittsburgh - SIS - 2720
Intersystem Operation and Mobility ManagementDavid Tipper Associate Professor Graduate Program in Telecommunications and Networking University of Pittsburgh Telcom 2720 Slides 6http:/www.tele.pitt.edu/tipper.html http:/www.tele.pitt.edu/tipper.htm
Wisconsin - ECE - 352
Department of Electrical and Computer Engineering University of Wisconsin MadisonECE/Comp Sci. 352 Digital Systems Fundamentals Homework 7 (Fall 2001)Homework 7 covers materials in sections 7.1 through 7.10 and 8.1 through 8.9 of the textbook. Y
Wisconsin - ECE - 352
ECE/CompDepartment of Electrical and Computer Engineering University of Wisconsin - Madison Sci 352 Digital System Fundamentals - Fall2002-2003DESIGN PROJECT 2: BCD CALCULATOR PART 2: Control DesignDue: Friday, December 6, 2002 (in class); 15%
McGill - COUNCIL - 0809
AGENDA for the Council Meeting of Wednesday, March 4th, 2009, 18h30 C09-03-#09 Call to Order 1. Approval of the Agenda 2. Speaker's Report 3. Announcements 3.1 Upcoming Events 3.2 Committee Vacancies 3.3 PGSS Annual General Meeting 3.4 Introduction o
Texas A&M - PHYS - 208
Texas A&M - PHYS - 208
Bonus CountingsFinal Exam Score (out of 200) for 70% of 750 WebCT Correction WebCT (max = 50) Exam 1+2+3 (avg) HW S0&S1 (6/10) Bonus Cointing TOTAL Exam 1+2 (avg)Letter GradePrev. Lab (%)WebCT (7/24)-3 11 31 41 48 57 64 65 66 67 71 78 79 83
Wisconsin - ECE - 551
ECE 551 - Digital System Design & SynthesisExercise 1 Sections 2, 3, and 7 of IEEE Std 1364-2001 - AnswersSpring 2003 Write in the answer at A: for each of the following questions and bring to class on Thursday, January 30 whether complete or not
Wisconsin - ECE - 551
3/19/2002Overview VHDL Language introductionECE 551: Digital System Design & SynthesisVHDL versus Verilog Lectures Set 8 Part 1 VHDL (1 Lecture) History of VHDL and Verilog Comparison using different metric (Ref: CRK) Comparison Summary
Texas A&M - PHYS - 218
Physics 218Lecture 19: Dynamics of Rotational MotionDr. Igor Roshchin1Checklist for Today Things due Yesterday Chapters 10 & 11 in WebCT, and 12-13 in notebooks Things that are due for today Read Chapters 14-16 Things that are due for Re
Acton School of Business - ARCH - 315
Temple Expiatori de la Sagrada FamiliaStructures Presentation 02 08 05 Nicholas Hofstede50 %
Texas A&M - PHYS - 218
Physics 218 Lecture 9Dr. David TobackPhysics 218, Lecture IX 1Overview Todays lecture is about problem solving for Chapters 4 & 5 Learn how to use everything weve learned so far to solve problems with: Rope Friction Friction and Uniform Circ
Acton School of Business - ARCH - 316
Arch 516 Environmental Control Systems Thermal and Mechanical Building Documentation Report (graduate students only) Suggested list of buildings: City Hall GSW Headquarters Hotel du Department Pola Museum Burton Barr Central Library Beddington Zero E
Washington - STAT - 494
Preliminary Battle Plan CSSS/POLS 494: Advanced Quantitative Political MethodologyProfessor: Kevin Quinn, Political Science and CSSS Spring Quarter 2002Class Room Office1:30 - 4:20 PM Tuesday 242 Mary Gates HallC-14-C Padelford Hall Phone: (206
Texas A&M - CVEN - 322
Washington - STAT - 560
%!PS-Adobe-2.0 %Creator: dvips(k) 5.86 Copyright 1999 Radical Eye Software %Title: BayesLike.dvi %Pages: 15 %PageOrder: Ascend %BoundingBox: 0 0 612 792 %DocumentFonts: Helvetica Helvetica-Bold Helvetica-Oblique %+ Helvetica-BoldOblique Symbol %EndCo
Washington - STAT - 536
%!PS-Adobe-2.0 %Creator: dvips(k) 5.86 Copyright 1999 Radical Eye Software %Title: BayesLike.dvi %Pages: 15 %PageOrder: Ascend %BoundingBox: 0 0 612 792 %DocumentFonts: Helvetica Helvetica-Bold Helvetica-Oblique %+ Helvetica-BoldOblique Symbol %EndCo
Washington - STAT - 536
%!PS-Adobe-2.0 %Creator: dvips(k) 5.86 Copyright 1999 Radical Eye Software %Title: LogitMotiv.dvi %Pages: 11 %PageOrder: Ascend %BoundingBox: 0 0 612 792 %DocumentFonts: Helvetica Helvetica-Bold Helvetica-Oblique %+ Helvetica-BoldOblique Symbol %EndC
Washington - STAT - 536
%!PS-Adobe-2.0 %Creator: dvips(k) 5.86 Copyright 1999 Radical Eye Software %Title: discrete-dist.dvi %Pages: 13 %PageOrder: Ascend %BoundingBox: 0 0 612 792 %DocumentFonts: Helvetica Helvetica-Bold Helvetica-Oblique %+ Helvetica-BoldOblique Symbol %E
Washington - STAT - 536
%!PS-Adobe-2.0 %Creator: dvips(k) 5.86e Copyright 2001 Radical Eye Software %Title: mathreview.dvi %Pages: 10 %PageOrder: Ascend %BoundingBox: 0 0 596 842 %EndComments %DVIPSWebPage: (www.radicaleye.com) %DVIPSCommandLine: dvips -o mathreview.ps -O 0
Washington - STAT - 536
%!PS-Adobe-3.0 %Pages: (atend) %BoundingBox: 71 46 541 725 %HiResBoundingBox: 71.500000 46.000000 540.600000 724.300000 %. %Creator: GNU Ghostscript 550 (pswrite) %CreationDate: 2002/05/08 17:27:13 %DocumentData: Clean7Bit %LanguageLevel: 2 %EndComme