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Course: CPATEL 313, Fall 2009
School: UMBC
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B B-3 Appendix - Reduction of Digital Logic Reduction (Simplification) of Boolean Expressions Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-4 Appendix B - Reduction of Digital Logic Reduced Majority Function Circuit Compared with the AND-OR circuit for the unreduced majority function, the inverter for C has been eliminated, one AND gate has been...

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B B-3 Appendix - Reduction of Digital Logic Reduction (Simplification) of Boolean Expressions Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-4 Appendix B - Reduction of Digital Logic Reduced Majority Function Circuit Compared with the AND-OR circuit for the unreduced majority function, the inverter for C has been eliminated, one AND gate has been eliminated, and one AND gate has only two inputs instead of three inputs. Can the function by reduced further? How do we go about it? Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-5 Appendix B - Reduction of Digital Logic The Algebraic Method Consider the majority function, F. We apply the algebraic method to reduce F to its minimal two-level form: Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-6 Appendix B - Reduction of Digital Logic The Algebraic Method This majority circuit is functionally equivalent to the previous majority circuit, but this one is in its minimal two-level form: Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-7 Appendix B - Reduction of Digital Logic Karnaugh Maps: Venn Diagram Representation of Majority Function Each distinct region in the Universe represents a minterm. This diagram can be transformed into a Karnaugh Map. Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-8 Appendix B - Reduction of Digital Logic K-Map for Majority Function Place a 1 in each cell that corresponds to that minterm. Cells on the outer edge of the map wrap around Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-9 Appendix B - Reduction of Digital Logic Adjacency Groupings for Majority Function F = BC + AC + AB Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-10 Appendix B - Reduction of Digital Logic Minimized AND-OR Majority Circuit F = BC + AC + AB The K-map approach yields the same minimal two-level form as the algebraic approach. Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-11 Appendix B - Reduction of Digital Logic 3-Level Majority Circuit K-Kap Reduction results in a reduced two-level circuit (that is, AND followed by OR. Inverters are not included in the two-level count). Algebraic reduction can result in multi-level circuits with even fewer logic gates and fewer inputs to the logic gates. Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-12 Appendix B - Reduction of Digital Logic K-Map Groupings Minimal grouping is on the left, non-minimal (but logically equivalent) grouping is on the right. obtain To minimal grouping, create smallest groups first. Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-13 Appendix B - Reduction of Digital Logic K-Map Corners are Logically Adjacent Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-14 Appendix B - Reduction of Digital Logic Truth Table with Dont Cares A truth table representation of a single function with dont cares. Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-15 Appendix B - Reduction of Digital Logic K-Maps and Dont Cares There can be more than one minimal grouping, as a result of dont cares. Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-16 Appendix B - Reduction of Digital Logic Five-Variable K-Map Visualize two 4-variable K-maps stacked one on top of the other; groupings are made in three dimensional cubes. Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-17 Appendix B - Reduction of Digital Logic Six-Variable K-Map Visualize four 4-variable K-maps stacked one on top of the other; groupings are made in three dimensional cubes. Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-18 Appendix B - Reduction of Digital Logic Map-Entered Variables An example of a K-map with a map-entered variable D. Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdoc c a and V. He uring B-19 Appendix B - Reduction of Digital Logic Two Map-Entered Variables A K-map with two map-entered variables D...

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