Simulation SystemC Envronment for a PLX-based Multimedia SoC Platform
Abstract This SystemC simulation environment is built for evaluating the functions of an H.264 encoder, especially that of the Motion Estimator, in a PLX-based Multimedia SoC platform (See Fig. 1). In this SoC platform, the video stream is get from CMOS Sensor, and the encoded sequence is stored in CF Card. Software, including BIOS, is stored in CF card and loaded into Embedded SDRAM through DMA PE (Processing Element). A non-cached Embedded SRAM is used to preload the multimedia stream data, which is predicted by software function. A timer is used for multi-task context switching. Serial interface I2C and UART is used for communicating with other systems. The PLX core uses a five-stage pipeline architecture, designed to maximize the 8-bit sub-word performance. After the simulation is performed, we plan to tapeout his chip in TSMC 0.18um process through the support of Chip Implementation Center.
PLX CORE Decoder Instruct Cache Reg File
Interrupt Controller
Timer Keyboard I2C UART KeyMatrix I2C RS232
Arbiter Bridge Data Cache Embed SRAM Smart DMA DMA PE CCIR PE IDE PE CMOS Sensor CF Card
DDR SDRAM
Figure 1. System Architecture of the PLX-based SoC platform
Memory Hierarchy External Double Data Rate (DDR) SDRAM is used as the main memory. External SRAM is faster and easier to control, but its capacity is not enough for video frame storage. For cost efficiency, DRAM is the best for external main memory. Software code should be loaded into SDRAM from IDE disk. On this platform the CF card is adapted as the disk, whose protocol is same as IDE disk but the I/O pin voltage is 3.3V, is compatible to DDR SDRAM pin voltage. The disk data is transfer to/from SDRAM by DMA channel. Embedded ROM is not implemented. An unchangeable ROM code is not suitable for a new design platform. The reset signal of CPU is hold after external reset, and a boot sector is loading into SDRAM address 0 by DMA PE. After the loading finish, the reset signal is released and the CPU starts to work. On chip cache is an expensive component both for chip area and power consumption. For multimedia application, large data is processing sequentially based on unit of block. The base address of next block is predictable by software. To preload the predicted block into embedded non-cached SRAM can get better performance compare with large data cache, and reduce the power consumption and chip area for tag field. A smaller 4-way set associate data cache is still needed for stack and local variable. Smart DMA Processing Element A smart DMA processing element is necessary to efficiently pre-load the multimedia content from SDRAM into embedded SRAM. The frame data stored in SDRAM is in one order such as row by row bitmap and luminance/chrominance interleaved, but the data willing to process is in another order such as 16x16 block with luminance only. To convert the data order is a heavy loading for processor. The convert is best done on DMA transferring. To pre-define all possible orders, or to design a reconfigurable order generator which can cover all possible orders, is next research topic. Three DMA transfer may occur concurrently, the SDRAM to SRAM, SDRAM to IDE and CCIR to SDRAM, DMA PE should dispatch the bandwidth. IDE Processing Element IDE PE receives the logic block address (LBA) and the required sector number from CPU, then initial the DMA transfer and maintain the IDE protocol. After the transfer finish, an interrupt signal generated. The disk file system is maintained by OS.
CCIR Processing Element The output of CMOS sensor is CCIR format at a fixed real-time rate, maximum 27MHz. CPU can set a lower rate to reduce the required frame rate. It needs software to adjust the Auto Exposure Time and Auto White Balance. It should be sub-sampled into required frame size. The adjusted data is sent to SDRAM by DMA channel. After a frame sent, an interrupt signal is generated.
Register File The register file data width is 32-bit or 64-bit, which is an option at tape-out, restricted by CIC recommended chip size. Cache and embedded SRAM size is also by restricted CIC. ALU Architecture Video processing is mostly 8-bit sub-word calculation. The CPU is optimized at 8-bit sub-word by designing most 8-bit sub-word instructions and address generator at one execution cycle, and higher sub-word instruction takes two or more execution cycle. The 32-bit ALU is pipelined into three stages, the first stage is 8-bit sub-word result, the second stage is 16-bit sub-word result, and the third stage is the 32-bit result. 64-bit ALU needs the forth stage. Multiplier is in recursive architecture to reuse 8x8 multipliers. The first stage is the 8-bit sub-word multipliers. To do a 32x32 calculation, four 32x8 sub-products are generated at first stage and then summarized at second stage, it takes five clock to execute. To save power, unused combinational functional blocks are disabled by input port gated, and D-FFs are disabled by clock gated. The disable signal is generated when data is issued to the target stage.
Reg1 Reg2
32-bit mul 8-bit stage
16-bit stage 32-bit stage Reg waiting flag forward
Figure 2. ALU architecture
Pipeline Architecture The control unit is designed as five stage pipeline architecture. These stages are (1) Instruction fetch stage Fetch instruction code from instruction cache. If code is not in instruction, set the fetched code as NOP and wait for cache refresh. (2) Decode stage Decode the fetched code into control signals. Memory read address is generated at this stage. (3) Operand fetch stage If the required source registers is ready, write them into ALU input buffer. If one of the registers is not ready, the pipeline paused. (4) Execution stage Whenever the ALU first stage is set as enabled, it begin to work. (5) Write back stage Whenever the 8-bit sub-word result is ready at first stage, or 16-bit sub-word result is ready at second stage, or 32-bit sub-word result is ready at third stage, the result is write back into register file.
Register wait flag A bit array Reg_Waiting_Flag is used to help check a register is valid to use as operand. At the Operand fetch stage, the bit in this array relative to result register is set to indicate it is not ready for next instruction. At Write back stage the bit is cleared to indicate it is ready for use. Register result forward If the operand of one instruction is the result register of previous instruction, data dependence occurred. To increase the performance, the operand should forward from the result of ALU. To forward from ALU combina...