353 ECE Introduction to Microprocessor Systems
Week 7
Michael Schulte
Administrative Matters
Homework #4 is due Friday, April 4th, 2008 Quiz #2 is rescheduled for Thursday, April 10th from 7:15 to 8:30 Discussion section tonight 6:308:00pm in 3534 Engineering Hall
Reading for week8
Memory Maps and Address Decoding
ADuC702X Datasheet 5360, 7173, 7579
Topics
Microprocessor support circuits
Clock and reset generation Power control Microprocessor supervisors GPIO pin construction I/O port design I/O decoding I/O synchronization ADuC7026 GPIO
I/O subsystems
ADuC7026 Block Diagram
Clocks
Clock Generation
Clock oscillators External clocks Phaselocked loops (PLLs) ADuC7026 clocking
PLLCON
Operation and design issues
Power Control
ADuC7026 operating modes
POWCON
ADuC7026 pinout
Reset
The reset signal is used to force the processor into a known state from which operation can reliably be started. On power up, the reset signal should be asserted long enough to ensure that the supply voltages are stable and the oscillator is running and stable Reset Generation
RC reset circuit operation Shortcomings
ADuC7026 pinout
Microprocessor Supervisors
Microprocessor supervisors provide reset functionality for a variety of circumstances
They can also provide a number of other services
Powerup Brownout Glitches
MAX807
ADuC7026 pinout
Basic System Bus Operation
Address
Data
Unidirectional from CPU Bidirectional /RS or /RD output from CPU
Control
/WS or /WR output from CPU
Indicates a read operation in progress Indicates a write operation in progress Used by external device to signal that it is not able to
/WAIT or /READY input to CPU
complete transfer yet
Read/Write Sequence
I/O Port Basics
I/O subsystems allow the CPU to interact with the outside world Basic GPIO pin requirements
Configurable vs. multiplexed pins Unconditional I/O
Configurable as input or output Can set value driven out on the pin Can read the current value on the pin
The I/O device can accept or return data ADuC7026 pinout without delay
MSI I/O Ports
Medium Scale Integration (MSI) circuits are available to construct ports Simple byte input ports can be constructed from...
Octal buffers
Octal registers
Simple byte output ports can be constructed from octal registers
P Compatible I/O Devices
Complex I/O devices typically require more sophisticated interface and control logic P compatible I/O devices have the necessary logic built in to the device itself
Device controllers
Interface designed to be reasonably compatible with many microprocessor buses Need to add decoding/selection logic Example An organizational model commonly used to interface to complex I/O devices (serial ports, LCDs, disk drives, etc.) Generic model Example Hitachi HD44780U LCD Controller
I/O Address Decoding
I/O address decoding determines the logical location of the I/O device
Input vs. output ports
Isolated Memorymapped I/O I/O
Exhaustive address decoding Partial address decoding
Same address does not guarantee same function!
I/O Address Decoding (cont.)
Linear selection decoding
A single address line is used as the selection criteria for each device Can have n input/output devices in a system with an nbit address bus Hazards and opportunities Note that this idea has a very limited application space!
Conditional I/O
Conditional vs. unconditional transfers
Hardware example Polling
I/O synchronization
Software exercise
Overhead Flags / semaphores Wait loops Timeouts
ADuC7026 GPIO Ports
The ADuC7026 has 40 pins organized as 5 ports that can be used as digital GPIO
All pins have multiple functions in addition being able to be used as GPIO The configuration selection is set through the GPxCON MMR.
ADuC7026 GPIO MMRs
GPxCON
Determine which of a pin's functions are active This is the configuration column selection on the previous slide
aduc7026.inc
ADuC7026 GPIO MMRs (cont)
GPxPAR
Does not apply to ports 2 and 4
PARameters Controls whether or not the internal pullups are used.
ADuC7026 GPIO MMRs (cont)
GPxDAT
Control the pin direction Set the output state Read the pin value Read the pin values that were present at reset
ADuC7026 GPIO MMRs (cont)
GPxSET
Write 1s to set the output value 0s have no effect
ADuC7026 GPIO MMRs (cont)
GPxCLR
Write 1s to clear the output value 0s have no effect
General Purpose I/O Exercise
Write a program that
1) Configures port P1 as a GP input port and P2 as a GP output port. 2) Sets P2 to 0xF7 3) Reads the value on P1 at reset 4) Copies the value on P1 to P2 5) Changes the least significant nibble of P2 to C, without changing the more significant nibble
Wrapp...