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### t3_fall2005_4743

Course: ECE 4743, Fall 2009
School: Mississippi State
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Word Count: 496

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Sp ECE4743/6743 2005 Test 3 Page 1 of 6 Closed book, one page notes Name ____________________________ 1. Given the equation Y = (X*a0) + (X@1*a1) + (Z*b0) + (Z@1*b1) and hardware constraints of one adder and two 2-stage pipelined multipliers, a) [10 pts.] Draw the dataflow graph (label all nodes!) b) [5 pts.] Schedule the operations for minimum clock cycles using the above constraints. (Note: not all clock...

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Sp ECE4743/6743 2005 Test 3 Page 1 of 6 Closed book, one page notes Name ____________________________ 1. Given the equation Y = (X*a0) + (X@1*a1) + (Z*b0) + (Z@1*b1) and hardware constraints of one adder and two 2-stage pipelined multipliers, a) [10 pts.] Draw the dataflow graph (label all nodes!) b) [5 pts.] Schedule the operations for minimum clock cycles using the above constraints. (Note: not all clock cycles may be used in the table below) Use only node names in the table. Mult A Clk 1 Clk 2 Clk 3 Clk 4 Clk 5 Clk 6 Clk 7 Clk 8 Clk 9 Mult B Adder I/O ECE4743/6743 Sp 2005 Test 3 Page 2 of 6 Name ____________________________ Use the schedule and datapath shown for the flow graph below in problems 2 and 3. Assume the delay of the multiplier is 12 ns, the adder delay is 7 ns, Tsu = 1 ns, Thd = 1 ns, Tc2q = 2ns Sample J N1 N3, N2 (depends on N4 Sample J-1) N4 Sample J+1 Figure 2 X N1, N3, N2 (depends on N4 sample J) N4 * N3 N4 + Y Clk 1 Clk 2 Clk 3 Clk 4 Clk 5 Clk 6 N1 a0 Y@1 N2 * b1 X Reg a0 R1 R2=Y@1 Reg b1 * (N2) R3 * (N3) R4 + Y ECE4743/6743 Sp 2005 Test 3 Page 3 of 6 Name ____________________________ 2. [25 pts.] a) What is the worst-case register-to-register delay? b) What is the worst-case clock-to-output delay? c) What is the minimum clock period? d) How long does it take to compute the first 10 samples (in nanoseconds)? 3. [20 pts.] a) Assume the multiplier now has a pipeline stage, and create a new schedule with the minimum latency and rate. initiation Sample J Sample J+1 Clk N Clk N+1 Clk N+2 Clk N+3 Clk N+4 Clk N+5 Clk N+6 Clk N+7 d) What is the minimum clock period of the new datapath with the pipelined multiplier? e) How long does it take to compute 10 sample values (in nanoseconds)? ECE4743/6743 Sp 2005 Test 3 Page 4 of 6 Name ____________________________ 4. [25 pts.] Given the following datapath planning of an FIR filter, draw the datapath. Be sure to label the control for each MUX. Multiplier A: Left sources: RA, RB Multiplier B: Left sources: RC, RD Adder: Left sources: RE RA source: RB source: RC source: RD source: RE source: RF source: X RA RB RC, MultA, Adder MultA, MultB, Adder MultB Right sources: a0, a1 Right sources: a2, a3 Right sources: RF, RD ECE4743/6743 Sp 2005 Test 3 Page 5 of 6 Name ____________________________ 5. [5 pts.] If the VGA output on the Pegasus board had two bits for Red,...

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