468 ELEN Advanced Logic Design
Lecture 15 Synthesis of Language Construct I
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Synthesis of Nets
An explicitly declared net may be eliminated in synthesis Primary input and output (ports) are always retained in synthesis Synthesis tool will implement trireg, tri0 and tri1 nets as physical wires
module and3( y, a, b, c ); input a, b, c; output y; wire y1; assign y1 = a & b; assign y = y1 & c; endmodule
b
a c
y
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Synthesis of Register Variables
A hardware register will be generated for a register variable when
Multiphased latches may not be supported in synthesis
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It is referenced before value is assigned in a behavior Assigned value in an edgesensitive behavior and is referenced by an assignment outside the behavior Assigned value in one clock cycle and referenced in another clock cycle
Synthesis of Integers
Initially implemented as a 32bit register Always specify size when declare a constant
For example, parameter a = 3'b7 will consume 3 bits while default is 32 bits
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Unsupported Data Types
real time realtime string
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Synthesis of Memories
No direct support Usually implemented as array of registers Not efficient as external memory Minimize the usage of such memory
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Synthesis of "x" and "z"
A description that uses explicit "x" or "z" values for data selection cannot be synthesized The only allowed usage of "x" is in casex and casez statements and in defaults of conditionals The only allowed use for "z" is in constructs that imply 3states device If a UDP assigns a value of "x" to a wire or reg, it will be treated as "don't care" If "x" is a default assignment in a conditional, it will be treated as "don't care"
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Synthesis of Arithmetic Operators
If corresponding library cell exists, an operator will be directly mapped to it Synthesis tool may select among different options in library cell, for example, when synthesize an adder
Implementation of "*" and "/"
Small wordlength > ripplecarry adder Long wordlength > carrylookahead adder Need small area > bitserial adder
May be inefficient when both operands are variables If a multiplier or the divisor is a power of two, can be implemented through shift register
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Synthesis of Shift Operators
Synthesis tools normally support shifting by a constant number of bits Cannot support a variable shift
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Relational Operators
Relational operators ( <, >, >=, <= ) can be implemented through
Combinational logic
module compare ( lt, gt, eq, A, B ); input A, B; output lt, gt, eq; assign lt = ( A < B ); assign gt = ( A > B ); assign eq = ( A == B ); endmodule
Adder/subtractor
bitextended In format Calculate A B, check extended bit of result
0 > A >= B 1 > A < B
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Synthesis of Identity Operators
The logical identity operators ( ==, != ) and the case identity operators ( ===, ! == ) are normally synthesized to combinational logic If they are used to support data select in either if or case statement, they will be synthesized to gates
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Reduction, Bitwise and Logical Operators They are translated into a set of equivalent Boolean equations and synthesized into combinational logic
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Conditional Operator
The conditional operator ( ? ... : ) synthesizes into library muxes or gates that implement the functionality of a mux The expression to the left of ? is formed as control logic for the mux
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Concatenation Operator
Equivalent to a logical bus No functionality of its own Generally supported by synthesis tool
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Grouping of Operators
module operator_group ( sum1, sum2, a, b, c, d ); input a, b, c, d; output sum1, sum2; assign sum1 = a + b + c + d; assign sum2 = ( a + b ) + ( c + d ); endmodule
b c adde r
a
adde r
adde r adde r sum2
d
adde r adde r sum1
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Synthesis of Assignment
Support by synthesis is vendorspecific Continuous assignment can be mapped directly to combinational logic Procedural assignment, LHS must be register variable Procedural continuous assignment
Supported by some tools
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Expression Substitution in Procedural Assignment
module multiple_assign ( out1, out2, a, b, c, d, sel, clk ); output [4:0] out1, out2; input [3:0] a, b, c, d; input sel, clk; reg [4:0] out1, out2; always @ ( posedge clk ) begin o...