320 CS Final Exam Take Home Portion
Name_________________________ April 28, 2009
For all of your problems show all of your work for full credit. Download this file as a Word document and type your answers directly below each question. 1. Assume that a computer has eight pages of virtual memory, four pages of physical memory, a fully associative cache, and the following sequence of unduplicated page references (i.e., with successive references to the same page omitted.) 14317536327026303126157173254264236153 For each of the following page replacement policies, determine (1) the sequence of pages loaded, and (2) the number of page faults. a. LRU Loading sequence________________________________________________________ Number of page faults______ b. Optimal Loading sequence________________________________________________________ Number of page faults______ 2. For a paged virtual memory system A) List the disadvantages that occur when the page size is too large. B) List the disadvantages that occur when the page size is too small. 3. What determines the total amount of virtual memory that a computer can have. 4. List at least 5 characteristics of RISC machines, at least 5 characteristics of CISC machines, and summarize the current state of computer architecture with regard to the RISC/CISC controversy. 5. Many machines are microprogrammed. Only a few are user microprogrammed. User microprogrammed machines are typically bit slice architectures and the user develops the assembly language instruction set. A) What are bit-slice architectures? B) What are the advantages of doing this. C) Why is this not popular and widely available.
6. A disk drive has the following characteristics: 8 surfaces 1024 tracks per surface 128 sectors per track 512 bytes per sector Track-to-track seek time of 7 msec Rotational speed of 7000 rpm A) Find the capacity of the drive? B) Find the access time for the drive. 7. Suppose that we have an unpipelined architecture that can be divided into 5 modules each of which may become one stage of a pipeline. If the time required to process data for each stage is 2, 3, 5, 3, and 4 nsec respectively and there is a 1 nsec latency between stages for the pipeline registers, what is the maximum clock frequency that this machine could run at. Show your work. 8. A given system has a main memory access time of 200 nsec and a cache access time of 40 nsec with a hit ratio of .85. Which of the following three cases would do most to improve the average access time of the system: A) Increase the main memory access time to 150 nsec. B) Increase cache the access time to 30 nsec. C) Increase the hit ratio of the cache to 90%. Show your calculations and justify your result for full credit. 9. Pipelining has been a mainstay of computer architecture since the early eighties. A) What factors in computer design ultimately limit the amount of speed that can be gained by doing a pipelined architecture? B) What factors keep any n-stage pipelined machine from being n times faster than a non pipelined machine. 10. Explain the difference between a linear address space, a paged address space, and a segmented address space. 11. Suppose a memory chip is organized as 2Meg x 4. Answer the following questions: A) How many bits can be stored on the chip? __________ B) How many address lines are needed to address all of the memory on the chip?______ C) How many data lines are needed? ________ 12. Cache memory systems and virtual memory systems have many key elements in common. Yet one of these is implemented in software and one in hardware. Give two reasons why this is so? 13. Instructions can have either a long format or a short format. List 3 advantages and 3 disadvantages of long instruction formats.
14. Write a short sequence of instructions in assembly language that illustrate a true data dependency when executed on a machine that does out-of-order execution and register renaming. Use the following instructions:
mov log jmp jnz ry, rx rx, ry, rz target target //move rx into ry //logic or arith instruction on rx and ry with result to rz // branch to target //conditional bran...