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Course: ELEC 4605, Fall 2009School: Allan Hancock College
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Computer ELEC4605 Architecture ELEC4605 Computer Architecture Week 3 School of Electrical and Information Engineering James G Rathmell (jimr@ee.usyd.edu.au) Overview Tutorial 1 Review Topics for today VHDL Design & Design Verification (Continued) Computer Components Computer Components Week 3 Tutorial 2 Preview Semester 1, 2009 ELEC4605(2009) Week-03 2009-02-02 12:34:56 jimr@ee.usyd.edu.au...
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Computer ELEC4605 Architecture
ELEC4605 Computer Architecture
Week 3
School of Electrical and Information Engineering James G Rathmell (jimr@ee.usyd.edu.au)
Overview
Tutorial 1 Review Topics for today
VHDL Design & Design Verification (Continued) Computer Components
Computer Components Week 3
Tutorial 2 Preview
Semester 1, 2009
ELEC4605(2009) Week-03 2009-02-02 12:34:56 jimr@ee.usyd.edu.au
ELEC4605(2009) Week-03 2009-02-02 12:34:56 jimr@ee.usyd.edu.au
Slide 1 of 6
ELEC4605 Computer Architecture
Week 3
ELEC4605 Computer Architecture
Week 3
Announcements
no announcement
Tutorial 1 Review
Introduction to laboratory equipment and design tools Mixed schematic and VHDL design Note that mapping of the input and outputs of the FPGA is done in the constraint file Make use of the debugging tools Any questions?
ELEC4605(2009) Week-03 2009-02-02 12:34:56 jimr@ee.usyd.edu.au
Slide 2 of 6
ELEC4605(2009) Week-03 2009-02-02 12:34:56 jimr@ee.usyd.edu.au
Slide 3 of 6
ELEC4605 Computer Architecture
Week 3
ELEC4605 Computer Architecture
Week 3
Topics for Today
VHDL Design Design Verification Computer Components
Tutorial Preview
2 VHDL design, simulation and implementation Follow the instructions on the tutorial work sheet for creating a design for simulation Be careful not to name projects, sheets and VHDL files and entities with the same name as this can cause problems with the software An example of stimulus code which is added to the test-bench template:
-- i n s e r t s t i m u l u s here SW <= b " 00000000 " ; wait SW <= b " 10000000 " ; wait SW <= b " 01000000 " ; wait SW <= b " 11000000 " ; wait for for for for 50ns ; 50ns ; 50ns ; 50ns ;
Implementation of a decoder and latch Optionally implement the bi-directional octal register
V...
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