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Coursehero >> Georgia >> Georgia Tech >> CHAPTER 3055

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2.5 3.0 Relative performance 2.0 1.5 1.0 0.0 0.5 1 2 4 Pipel...

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Georgia Tech - CHAPTER - 3055
Multicycle datapath (section 5.4)Pipelined datapath (Chapter 6)Clock rateFasterSingle-cycle datapath (section 5.3)SlowerSlowerFasterInstruction throughput (instructions per clock cycle or 1/CPI)
Georgia Tech - CHAPTER - 3055
SpecializedSingle-cycle datapath (section 5.3)Pipelined datapath (Chapter 6)Hardware SharedMulticycle datapath (section 5.4)1SeveralClock cycles of latency for an instruction
Georgia Tech - ECE - 3055
Georgia Tech - ECE - 3055
A BA B
Georgia Tech - ECE - 3055
3DecoderOut0 Out1 Out2 Out3 Out4 Out5 Out6 Out7a. A 3-bit decoder
Georgia Tech - ECE - 3055
AB0 M u x 1A C C BSS
Georgia Tech - ECE - 3055
Falling edgeClock periodRising edge
Georgia Tech - ECE - 3055
RQS_ Q
Georgia Tech - ECE - 3055
C Q_ Q D
Georgia Tech - ECE - 3055
DCQ
Georgia Tech - ECE - 3055
DD CD latchQDQ D latch _ C QQ _ QC
Georgia Tech - ECE - 3055
DCQ
Georgia Tech - ECE - 3055
D Set-up time Hold timeC
Georgia Tech - ECE - 3055
Read register number 1 Read register number 2 Write register Write dataRead data 1Register fileRead data 2 Write
Georgia Tech - ECE - 3055
Write 0 1 Register number C Register 0 D C Register 1 Dn-to-1 decoder n1 nC Register n 1 D C Register n Register data D
Georgia Tech - ECE - 3055
Address Chip select Output enable Write enable Din[70]15SRAM 32K 8 88Dout[70]
Georgia Tech - ECE - 3055
Select 0 Data 0 Select 1 Data 1 Select 2 Data 2 Select 3 Data 3 In In In InEnable OutEnable OutEnable OutOutputEnable Out
Georgia Tech - ECE - 3055
Din[1]Din[0]Write enable 0D D C latch Q EnableD D C latch Q Enable2-to-4 decoderD D C latch Q EnableD D C latch Q Enable1AddressD D C latch Q Enable 2D D C latch Q EnableD D C latch Q Enable 3D D C latch Q EnableDout[1]D
Georgia Tech - ECE - 3055
Address [146]9-to-512 decoder 512512 64 512 64 512 64 512 64 512 64 512 64 512 64 512 64 SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM64 Address [50] Mux Mux Mux Mux Mux Mux Mux MuxDout7Dout6Dout5Dout4Dout3Dout2Dout1Dout0
Georgia Tech - ECE - 3055
Word line Pass transistor CapacitorBit line
Georgia Tech - ECE - 3055
Row decoder 11-to-20482048 2048 arrayAddress[100]Column latchesMuxDout
Georgia Tech - ECE - 3055
Current stateNext-state functionNext stateClock InputsOutput functionOutputs
Georgia Tech - ECE - 3055
EWcarNSgreen NSlite NScar EWliteEWgreen_ EWcar_ NScar
Georgia Tech - ECE - 3055
Outputs Combinational logicNext stateState registerInputs
Georgia Tech - ECE - 3055
Q D Flip-flop CCombinational logic blockD Q Flip-flop Ctproptcombinationaltsetup
Georgia Tech - ECE - 3055
Clock arrives at time tD Q Flip-flop CCombinational logic block with delay time of Clock arrives after t + D Q Flip-flop C
Georgia Tech - ECE - 3055
1 2 Nonoverlapping periods
Georgia Tech - ECE - 3055
D 1 Latch CQCombinational logic blockD 2 Latch CQCombinational logic blockD 1 Latch C
Georgia Tech - ECE - 3055
Asynchronous input ClockD Q Flip-flop CSynchronous output
Georgia Tech - ECE - 3055
Asynchronous input ClockD Q Flip-flop CD Q Flip-flop CSynchronous output
Georgia Tech - ECE - 3055
ALUOp ALU control block ALUOp0 ALUOp1F3 F2 F (50) F1Operation2 Operation1 Operation0 OperationF0