8255TechSheet
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8255TechSheet

Course Number: LECTURE 800, Fall 2009

College/University: Drexel

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E2O0020-27-X3 Semiconductor MSM82C55A-2RS/GS/VJS Semiconductor CMOS PROGRAMMABLE PERIPHERAL INTERFACE This version: Jan. 1998 MSM82C55A-2RS/GS/VJS Previous version: Aug. 1996 GENERAL DESCRIPTION The MSM82C55A-2 is a programmable universal I/O interface device which operates as high speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best fit as an I/O port in a system which...

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Semiconductor E2O0020-27-X3 MSM82C55A-2RS/GS/VJS Semiconductor CMOS PROGRAMMABLE PERIPHERAL INTERFACE This version: Jan. 1998 MSM82C55A-2RS/GS/VJS Previous version: Aug. 1996 GENERAL DESCRIPTION The MSM82C55A-2 is a programmable universal I/O interface device which operates as high speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best fit as an I/O port in a system which employs the 8-bit parallel processing MSM80C85AH CPU. This device has 24-bit I/O pins equivalent to three 8-bit I/O ports and all inputs/outputs are TTL interface compatible. FEATURES High speed and low power consumption due to 3m silicon gate CMOS technology 3 V to 6 V single power supply Full static operation Programmable 24-bit I/O ports Bidirectional bus operation (Port A) Bit set/reset function (Port C) TTL compatible Compatible with 8255A-5 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C55A-2RS) 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C55A-2VJS) 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C55A-2GS-2K) 1/26 Semiconductor MSM82C55A-2RS/GS/VJS CIRCUIT CONFIGURATION 8 VCC 8 GND 8 Group A Control 4 Group A Port C (High Order 4 Bits) 4 PC4 - PC7 Group A Port A (8) 8 PA0 - PA7 8 D 0 - D7 Data Bus Buffer 8 Internal Bus Line 4 8 RD WR RESET CS A0 A1 Read/ Write Control Logic Group B Control 8 Group B Port C (Low Order 4 Bits) 4 PC0 - PC3 Group B Port B (8) 8 PB0 - PB7 2/26 Semiconductor MSM82C55A-2RS/GS/VJS PIN CONFIGURATION (TOP VIEW) 40 pin Plastic DIP 1 2 3 4 RD 5 CS 6 GND 7 A1 8 A0 9 PC7 10 PC6 11 PC5 12 PC4 13 PC0 14 PC1 15 PC2 16 PC3 17 PB0 18 PB1 19 PB2 20 PA3 PA2 PA1 PA0 33 32 31 30 29 28 27 26 25 24 23 NC 12 PC3 13 PB0 14 PB1 15 PB2 16 17 PB3 18 PB4 19 PB5 20 PB6 21 NC 22 VCC 44 pin Plastic QFP 44 RD 43 PA0 42 PA1 41 PA2 40 PA3 38 PA4 37 PA5 36 PA6 35 PA7 34 WR 39 VCC 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3 CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 1 2 3 4 5 6 7 8 9 10 11 RESET D0 D1 D2. D3 D4 D5 D6 D7 VCC PB7 6 RD 5 PA0 44 pin Plastic QFJ 4 PA1 3 PA2 2 PA3 44 PA4 43 PA5 42 PA6 41 PA7 40 WR 1 NC CS GND A1 A0 PC7 NC PC6 PC5 PC4 PC0 PC1 7 8 9 10 11 12 13 14 15 16 17 PB0 20 PB1 21 PB2 22 NC 23 PB3 24 PB4 25 PB5 26 PB6 27 PC2 18 PC3 19 PB7 28 39 38 37 36 35 34 33 32 31 30 29 RESET D0 D1 D2. D3 NC D4 D5 D6 D7 VCC 3/26 Semiconductor MSM82C55A-2RS/GS/VJS ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation Symbol VCC VIN VOUT TSTG PD Conditions Ta = 25C with respect to GND -- Ta = 25C 1.0 Rating MSM82C55A-2RS MSM82C55A-2GS MSM82C55A-2vJS Unit V V V C 1.0 W 0.5 to +7 0.5 to VCC +0.5 0.5 to VCC +0.5 55 to +150 0.7 OPERATING RANGE Parameter Supply Voltage Operating Temperature Symbol VCC Top Range 3 to 6 40 to 85 Unit V C RECOMMENDED OPERATING RANGE Parameter Supply Voltage Operating Temperature "L" Input Voltage "H" Input Voltage Symbol VCC Top VIL VIH Min. 4.5 40 0.3 2.2 Typ. 5 +25 -- -- Max. 5.5 +85 +0.8 VCC + 0.3 Unit V C V V DC CHARACTERISTICS MSM82C55A-2 Min. -- 4.2 3.7 VCC = 4.5 V to 5.5 V Ta = 40C to +85C (CL = 0 pF) 1 10 -- Typ. -- -- -- -- -- 0.1 Max. 0.4 -- -- 1 10 10 Parameter "L" Output Voltage "H" Output Voltage Input Leak Current Output Leak Current Supply Current (Standby) Average Supply Current (Active) Symbol VOL VOH ILI ILO ICCS Conditions IOL = 2.5 mA IOH = 40 mA IOH = 2.5 mA 0 VIN VCC 0 VOUT VCC CS VCC 0.2 V VIH VCC 0.2 V VIL 0.2 V I/O Wire Cycle 82C55A-2 ...8 MHzCPU Timing Unit V V V mA mA mA ICC -- -- 8 mA 4/26 Semiconductor MSM82C55A-2RS/GS/VJS AC CHARACTERISTICS Parameter Setup Time of Address to the Falling Edge of RD Hold Time of Address to the Rising Edge of RD RD Pulse Width Delay Time from the Falling Edge of RD to the Output of Defined Data Delay Time from the Rising Edge of RD to the Floating of Data Bus Time from the Rising Edge of RD or WR to the Next Falling Edge of RD or WR Setup Time of Address before the Falling Edge of WR Hold Time of Address after the Rising Edge of WR WR Pulse Width Setup Time of Bus Data before the Rising Edge of WR Hold Time of Bus Data after the Rising Edge of WR Delay Time from the rising Edge of WR to the Output of Defined Data Setup Time of Port Data before the Falling Edge of RD Hold Time of Port Data after the Rising Edge of RD ACK Pulse Width STB Pulse Width Setup Time of Port Data before the rising Edge of STB Hold Time of Port Bus Data after the rising Edge of STB Delay Time from the Falling Edge of ACK to the Output of Defined Data Delay Time from the Rising Edge of ACK to the Floating of Port (Port A in Mode 2) Delay Time from the Rising Edge of WR to the Falling Edge of OBF Delay Time from the Falling Edge of ACK to the Rising Edge of OBF Delay Time from the Falling Edge of STB to the Rising Edge of IBF Delay Time from the Rising Edge of RD to the Falling Edge of IBF Delay Time from the the Falling Edge of RD to the Falling Edge of INTR Delay Time from the Rising Edge of STB to the Rising Edge of INTR Delay Time from the Rising Edge of ACK to the Rising Edge of INTR Delay Time from the Falling Edge of WR to the Falling Edge of INTR (VCC = 4.5 V to 5.5 V, Ta = 40 to +85C) MSM82C55A-2 Symbol Unit Remarks Min. Max. tAR tRA tRR tRD tDF tRV tAW tWA tWW tDW tWD tWB tIR tHR tAK tST tPS tPH tAD tKD tWOB tAOB tSIB tRIB tRIT tSIT tAIT tWIT 20 0 100 -- 10 200 0 20 150 50 30 -- 20 10 100 100 20 50 -- 20 -- -- -- -- -- -- -- -- -- -- -- 120 75 -- -- -- -- -- -- 200 -- -- -- -- -- -- 150 250 150 150 150 150 200 150 150 250 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Load 150 pF Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs. 5/26 Semiconductor MSM82C55A-2RS/GS/VJS TIMING DIAGRAM Basic Input Operation (Mode 0) tRR RD tIR Port Input tAR CS, A1, A0 D7 - D0 tRD tDF tRA tHR Basic Output Operation (Mode 0) tWW WR tDW D 7 - D0 tAW CS, A1, A0 Port Output tWB tWA tWD Strobe Input Operation (Mode 1) tST STB tSIB IBF INTR RD tPH Port Input tPS tSIT tRIT tRIB 6/26 Semiconductor Strobe Output Operation (Mode 1) MSM82C55A-2RS/GS/VJS WR tAOB OBF tWOB INTR tWIT ACK Port Output tWB tAK tAIT Bidirectional Bus Operation (Mode 2) WR tAOB OBF tWOB INTR tAK ACK STB IBF tPS Port A RD tPH tRIB tSIB tAD tKD tST 7/26 Semiconductor MSM82C55A-2RS/GS/VJS OUTPUT CHARACTERISTICS (REFERENCE VALUE) 1 Output "H" Voltage (VOH) vs. Output Current (IOH) 5 Output "H" Voltage VOH (V) 4 3 2 1 0 0 1 Ta = 40 to + 85C VCC = 5.0 V 2 3 4 5 Output Current IOH (mA) 2 Output "L" Voltage (VOL) vs. Output Current (IOL) 5 Output "L" Voltage VOL (V) 4 3 2 1 0 0 1 2 3 4 5 VCC = 5.0 V Ta = 40 to +85C Output Current IOL (mA) Note: The direction of flowing into the device is taken as positive for the output current. 8/26 Semiconductor MSM82C55A-2RS/GS/VJS PIN DESCRIPTION Pin No. Item Bidirectional Data Bus Input/Output Input and Output Function These are three-state 8-bit bidirectional buses used to write and read data upon receipt of the WR and RD signals from CPU and also used when control words and bit set/reset data are transferred from CPU to MSM82C55A-2. This signal is used to reset the control register and all internal registers when it is in high level. At this time, ports are all made into the input mode (high impedance status). all port latches are cleared to 0. and all ports groups are set to mode 0. When the CS is in low level, data transmission is enabled with CPU. When it is in high level, the data bus is made into the high impedance status where no write nor read operation is performed. Internal registers hold their previous status, however. When RD is in low level, data is transferred from MSM82C55A-2 to CPU. When WR is in low level, data or control words are transferred from CPU to MSM82C55A-2. By combination of A0 and A1, either one is selected from among port A, port B, port C, and control register. These pins are usually connected to low order 2 bits of the address bus. These are universal 8-bit I/O ports. The direction of inputs/ outputs can be determined by writing a control word. Especially, port A can be used as a bidirectional port when it is set to mode 2. These are universal 8-bit I/O ports. The direction of inputs/outputs ports can be determined by writing a control word. These are universal 8-bit I/O ports. The direction of inputs/outputs can be determined by writing a control word as 2 ports with 4 bits each. When port A or port B is used in mode 1 or mode 2 (port A only), they become control pins. Especially, when port C is used as an output port, each bit can set/reset independently. +5V power supply. GND D 7 - D0 RESET Reset Input Input CS Chip Select Input Input RD WR Read Input Write Input Input Input A0 , A 1 Port Select Input (Address) Input PA7 - PA0 Port A Input and Output Input and Output PB7 - PB0 Port B PC7 - PC0 Port C Input and Output VCC GND 9/26 Semiconductor MSM82C55A-2RS/GS/VJS BASIC FUNCTIONAL DESCRIPTION Group A and Group B When setting a mode to a port having 24 bits, set it by dividing it into two groups of 12 bits each. Group A: Port A (8 bits) and high order 4 bits of port C (PC7~PC4) Group B: Port B (8 bits) and low order 4 bits of port C (PC3~PC0) Mode 0, 1, 2 There are 3 types of modes to be set by grouping as follows: Mode 0: Basic input operation/output operation (Available for both groups A and B) Mode 1: Strobe input operation/output operation (Available for both groups A and B) Mode 2: Bidirectional bus operation (Available for group A only) When used in mode 1 or mode 2, however, port C has bits to be defined as ports for control signal for operation ports (port A for group A and port B for group B) of their respective groups. Port A, B, C The internal structure of 3 ports is as follows: Port A: One 8-bit data output latch/buffer and one 8-bit data input latch Port B: One 8-bit data input/output latch/buffer and one 8-bit data input buffer Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input) Single bit set/reset function for port C When port C is defined as an output port, it is possible to set (to turn to high level) or reset (to turn to low level) any one of 8 bits individually without affecting other bits. 10/26 Semiconductor MSM82C55A-2RS/GS/VJS OPERATIONAL DESCRIPTION Control Logic Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table below: Operaiton Input A1 0 0 1 0 Output Control Others 0 1 1 1 A0 0 1 0 0 1 0 1 1 CS 0 0 0 0 0 0 0 0 1 WR 1 1 1 0 0 0 0 1 RD 0 0 0 1 1 1 1 0 Operation Port A Data Bus Port B Data Bus Port C Data Bus Data Bus Port A Data Bus Port B Data Bus Port C Data Bus Control Register Illegal Condition Data bus is in the high impedance status. Setting of Control Word The control register is composed of 7-bit latch circuit and 1-bit flag as shown below. Group A Control Bits D7 D6 D5 D4 D3 Group B Control Bits D2 D1 D0 Definition of input/ output of low order 4 bits of port C. Definition of input/ output of 8 bits of port B. Mode definition of group B. Definition of input/ output of high order 4 bits of port C. Definition of input/ output of 8 bits of port A. 0 = Output 1 = Input 0 = Output 1 = Input 0 = Mode 0 1 = Mode 1 0 = Output 1 = Input 0 = Output 1 = Input Mode definition of group A. Control word Identification flag Be sure to set 1 for the control word to define a mode and input/output. When set to 0, it becomes the control word for bit set/ reset. D6 D5 0 0 0 1 1 Mode Mode 0 Mode 1 Mode 2 11/26 Semiconductor Precaution for Mode Selection MSM82C55A-2RS/GS/VJS The output registers for ports A and C are cleared to f each time data is written in the command register and the mode is changed, but the port B state is undefined. Bit Set/Reset Function When port C is defined as output port, it is possible to set (set output to 1) or reset (set output to 0) any one of 8 bits without affecting other bits as shown below. D7 D6 D5 D4 D3 D2 D1 D0 Definition of set/reset for a desired bit. 0 = Reset 1 = Set Definition of bit wanted to be set or reset. Port C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 D3 D2 D1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Dont's Care Control word Identification flag Be sure to set to 0 for bit set/reset When set to 1, it becomes the control word to define a mode and input/output. Interrupt Control Function When the MSM82C55A-2 is used in mode 1 or mode 2, the interrupt signal for the CPU is provided. The interrupt request signal is output from port C. When the internal flip-flop INTE is set beforehand at this time, the desired interrupt request signal is output. When it is reset beforehand, however, the interrupt request signal is not output. The set/reset of the internal flip-flop is made by the bit set/reset operation for port C virtually. Bit set INTE is set Interrupt allowed Bit reset INTE is reset Interrupt inhibited Operational Description by Mode 1. Mode 0 (Basic input/output operation) Mode 0 makes the MSM82C55A-2 operate as a basic input port or output port. No control signals such as interrupt request, etc. are required in this mode. All 24 bits can be used as two-8-bit ports and two 4-bit ports. Sixteen combinations are then possible for inputs/ outputs. The inputs are not latched, but the outputs are. 12/26 Semiconductor MSM82C55A-2RS/GS/VJS Control Word Type D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Port A Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Group A High Order 4 Bits of Port C Output Output Output Output Input Input Input Input Output Output Output Output Input Input Input Input Port B Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Group B Low Order 4 Bits of Port C Output Input Output Input Output Input Ouput Input Output Input Output Input Output Input Output Input Notes: When used in mode 0 for both groups A and B 2. Mode 1 (Strobe input/output operation) In mode 1, the strobe, interrupt and other control signals are used when input/output operations are made from a specified port. This mode is available for both groups A and B. In group A at this time, port A is used as the data line and port C as the control signal. Following is a description of the input operation in mode 1. STB (Strobe input) When this signal is low level, the data output from terminal to port is fetched into the internal latch of the port. This can be made independent from the CPU, and the data is not output to the data bus until the RD signal arrives from the CPU. IBF (Input buffer full flag output) This is the response signal for the STB. This signal when turned to high level indicates that data is fetched into the input latch. This signal turns to high level at the falling edge of STB and to low level at the rising edge of RD. INTR (Interrupt request output) This is the request interrupt signal for the CPU of the data fetched into the input latch. It is indicated by high level only when the internal INTE flip-flop is set. This signal turns to high level at the rising edge of the STB (IBF = 1 at this time) and low level at the falling edge of the RD when the INTE is set. INTE A of group A is set when the bit for PC4 is set, while INTE B of group B is set when the bit for PC2 is set. Following is a description of the output operation of mode 1. 13/26 Semiconductor MSM82C55A-2RS/GS/VJS OBF (Output buffer full flag output) This signal when turned to low level indicates that data is written to the specified port upon receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK. ACK (Acknowledge input) This signal when turned to low level indicates that the terminal has received data. INTR (Interrupt request output) This is the signal used to interrupt the CPU when a terminal receives data from the CPU via the MSM82C55A-5. It indicates the occurrence of the interrupt in high level only when the internal INTE flip-flop is set. This signal turns to high level at the rising edge of the ACK (OBF = 1 at this time) and low level at the falling edge of WR when the INTE B is set. INTE A of group A is set when the bit for PC6 is set, while INTE B of group B is set when the bit for PC2 is set. Mode 1 Input (Group A) PA7 8 (Group B) PB7 INTEB STBA IBFA RD PC3 INTRA PC0 INTRB PB0 PC2 PC1 STBB IBFB 8 - INTEA PA0 PC4 PC5 RD Note: Although belonging to group B, PC3 operates as the control signal of group A functionally. Mode 1 Output (Group A) PA7 8 (Group B) PB7 INTEB OBFA ACKA WR PC3 INTRA PC0 INTRB PB0 PC1 PC2 OBFB ACKB 8 - INTEA PA0 PC7 PC6 WR - - 14/26 Semiconductor Port C Function Allocation in Mode 1 Combination of Input/Output Port C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Group A: Input Group B: Input INTRB IBFB STBB INTRA STBA IBFA I/O I/O MSM82C55A-2RS/GS/VJS Group A: Input Group A: Output Group B: Output Group B: Input INTRB OBFB ACKB INTRA STBA IBFA I/O I/O INTRB IBFB STBB INTRA I/O I/O ACKA OBFA Group A: Output Group B: Output INTRB OBFB ACKB INTRA I/O I/O ACKA OBFA Note: I/O is a bit not used as the control signal, but it is available as a port of mode 0. Examples of the relation between the control words and pins when used in mode 1 are shown below: (a) When group A is mode 1 output and group B is mode 1 input. D7 Control Word 1 D6 0 D5 1 D4 0 D3 1/0 D2 1 D1 1 D0 As all of PC0 - PC3 bits become a control pin in this case, this bit is "Don't Care". Selection of I/O of PC4 and PC5 when not defined as a control pin. 1 = Input 0 = Output PA7 - PA0 PC7 PC6 PC3 PC4, PC5 2 PB7 - PB0 PC2 PC1 PC0 8 8 WR OBFA ACKA INTRA I/O STBB IBFB INTRB Group A: Mode 1 Output Group B: Mode 1 Input RD 15/26 Semiconductor MSM82C55A-2RS/GS/VJS (b) When group A is mode 1 input and group B is mode 1 output. D7 1 D6 0 D5 1 D4 1 D3 1/0 D2 1 D1 0 D0 Selection of I/O of PC6 and PC7 when not defined as a control pin. 1 = Input 0 = Output RD PA7 - PA0 PC4 PC5 PC3 PC6, PC7 PB7 - PB0 PC1 PC2 PC0 8 2 8 STBA IBFA INTRA I/O OBFB ACKB INTRB Group A: Mode 1 Input Group B: Mode 1 Output WR 3. Mode 2 (Strobe bidirectional bus I/O operation) In mode 2, it is possible to transfer data in 2 directions through a single 8-bit port. This operation is akin to a combination between input and output operations. Port C waits for the control signal in this case, too. Mode 2 is available only for group A, however. Next, a description is made on mode 2. OBF (Output buffer full flag output) This signal when turned to low level indicates that data has been written to the internal output latch upon receipt of the WR signal from the CPU. At this time, port A is still in the high impedance status and the data is not yet output to the outside. This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK. ACK (Acknowledge input) When a low level signal is input to this pin, the high impedance status of port A is cleared, the buffer is enabled, and the data written to the internal output latch is output to port A. When the input returns to high level, port A is made into the high impedance status. STB (Strobe input) When this signal turns to low level, the data output to the port from the pin is fetched into the internal input latch. The data is output to the data bus upon receipt of the RD signal from the CPU, but it remains in the high impedance status until then. IBF (Input buffer full flag output) This signal when turned to high level indicates that data from the pin has been fetched into the input latch. This signal turns to high level at the falling edge of the STB and low level at the rising edge of the RD. 16/26 Semiconductor MSM82C55A-2RS/GS/VJS INTR (Interrupt request output) This signal is used to interrupt the CPU and its operation in the same as in mode 1. There are two INTE flip-flops internally available for input and output to select either interrupt of input or output operation. The INTE1 is used to control the interrupt request for output operation and it can be reset by the bit set for PC6. INTE2 is used to control the interrupt request for the input operation and it can be set by the bit set for PC4. Mode 2 I/O Operation PC3 PA7 PA0 PC7 INTE1 PC6 8 INTRA - OBFA ACKA WR RD INTE2 PC4 PC5 STBA IBFA Port C Function Allocation in Mode 2 Port C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 INTRA STBA IBFA ACKA OBFA Confirmed to the Group B Mode Function Following is an example of the relation between the control word and the pin when used in mode 2. When input in mode 2 for group A and in mode 1 for group B. 17/26 Semiconductor MSM82C55A-2RS/GS/VJS D7 1 D6 1 D5 D4 D3 D2 1 D1 1 D0 As all of 8 bits of port C become control pins in this case, D3 and D0 bits are treated as "Don't Care". No I/O specification is required for mode 2, since it is a bidirectional operation. This bit is therefore treated as "Don't Care". When group A is set to mode 2, this bit is treated as "Don't Care". PC3 PA7 - PA0 PC7 PC6 PC4 PC5 RD WR PB7 - PB0 PC2 PC1 PC0 INTRA 8 OBFA ACKA STBA IBFA 8 Group A: Mode 2 Group B: Mode 1 Input STBB IBFB INTRB 18/26 Semiconductor 4. When Group A is Different in Mode from Group B MSM82C55A-2RS/GS/VJS Group A and group B can be used by setting them in different modes each other at the same time. When either group is set to mode 1 or mode 2, it is possible to set the one not defined as a control pin in port C to both input and output as port which operates in mode 0 at the 3rd and 0th bits of the control word. (Mode combinations that define no control bit at port C) Group A 1 2 3 4 5 6 7 8 9 Mode 1 input Mode 0 Output Mode 0 Mode 0 Mode 1 Input Mode 1 Input Mode 1 Output Mode 1 Output Mode 2 Group B Mode 0 Mode 0 Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 0 Port C PC4 PC3 STBA I/O I/O I/O STBA STBA I/O I/O STBA INTRA INTRA I/O I/O INTRA INTRA INTRA INTRA INTRA PC7 I/O OBFA I/O I/O I/O I/O OBFA OBFA OBFA PC6 I/O ACKA I/O I/O I/O I/O ACKA ACKA ACKA PC5 IBFA I/O I/O I/O IBFA IBFA I/O I/O IBFA PC2 I/O I/O STBB ACKB STBB ACKB STBB ACKB I/O PC1 I/O I/O IBFB OBFB IBFB OBFB IBFB OBFB I/O PC0 I/O I/O INTRB INTRB INTRB INTRB INTRB INTRB I/O Controlled at the 3rd bit (D3) of the Control Word Controlled at the 0th bit (D0) of the Control Word When the I/O bit is set to input in this case, it is possible to access data by the normal port C read operation. When set to output, PC7-PC4 bits can be accessed by the bit set/reset function only. Meanwhile, 3 bits from PC2 to PC0 can be accessed by normal write operation. The bit set/reset function can be used for all of PC3-PC0 bits. Note that the status of port C varies according to the combination of modes like this. 19/26 Semiconductor 5. Port C Status Read MSM82C55A-2RS/GS/VJS When port C is used for the control signal, that is, in either mode 1 or mode 2, each control signal and bus status signal can be read out by reading the content of port C. The status read out is as follows: Group A 1 2 3 4 5 6 7 8 9 10 11 Mode 1 Input Mode 1 Output Mode 0 Mode 0 Mode 1 Input Mode 1 Input Mode 1 Output Mode 1 Output Mode 2 Mode 2 Mode 2 Group B Mode 0 Mode 0 Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 0 Mode 1 Input Mode 1 Output Status Read on the Data Bus D5 D4 D3 D2 IBFA I/O I/O I/O IBFA IBFA I/O I/O IBFA IBFA IBFA INTEA I/O I/O I/O INTEA INTEA I/O I/O INTE2 INTE2 INTE2 INTRA INTRA I/O I/O INTRA INTRA INTRA INTRA INTRA INTRA INTRA I/O I/O INTEB INTEB INTEB INTEB INTEB INTEB I/O INTEB INTEB D7 I/O OBFA I/O I/O I/O I/O OBFA OBFA OBFA OBFA OBFA D6 I/O INTEA I/O I/O I/O I/O INTEA INTEA INTE1 INTE1 INTE1 D1 I/O I/O IBFB OBFB IBFB OBFB IBFB OBFB I/O IBFB OBFB D0 I/O I/O INTRB INTRB INTRB INTRB INTRB INTRB I/O INTRB INTRB 6. Reset of MSM82C55A-2 Be sure to keep the RESET signal at power ON in the high level at least for 50 ms. Subsequently, it becomes the input mode at a high level pulse above 500 ns. Note: Comparison of MSM82C55A-5 and MSM82C55A-2 MSM82C55A-5 After a write command i...

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Caltech - MATH - 120
MATH 120C, PROBLEM SET 1Due Wednesday, April 16. (1) (2) (3) (4) Read Lang, Section V, 5. Do Problems 14, 16, 18 and 24 in Lang, Section V. Prove that if E/F is separable then its normal closure E/F is also separable. 2 Let F be a finite field wit
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Texas A&M - OCEN - 672
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Utah - M - 5010
Test 2 Mathematics 5010, Section 1, Fall 2004 Instructor: D.A. LevinName YOU MUST SHOW YOUR WORK TO RECEIVE CREDIT. A CORRECT ANSWER WITHOUT SHOWING YOUR REASONING WILL NOT RECEIVE CREDIT.1Problem 1. Let X have a Gamma(, ) distribution. That is
Contra Costa College - COEN - 311
Utah - CS - 7810
Lecture 1: Introduction Course organization: 13 lectures on parallel architectures ~5 lectures on cache coherence, consistency ~3 lectures on TM ~2 lectures on interconnection networks ~2 lectures on large cache hierarchies ~1 lecture on parallel al
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BYU - CS - 652
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BYU - CS - 652
ku x u q s j q r q x msWyYsWmxylYWxYllY6v9YuYWCl9mvs YmsW1Wr$Wmxylnvl YsrYs&YsaYYWYs5r s j xj rj x uj s u q qj q u u q x rj j u k x u kj u j sju lWyrYuWFdYsmq1WWmWaytmwmklxCYslpvlvs u u x s q x u ju s u q x
BYU - CS - 652
Visual Web Information Extraction with LixtoRobert BaumgartnerDBAI, TU Wien Favoritenstr. 9 1040 Vienna Austria baumgart@dbai.tuwien.ac.atSergio FlescaDEIS, Universit` della Calabria a Via Pietro Bucci, 41C-42C 87030 Rende (CS) Italy flesca@deis
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BYU - CS - 652
IST Project IST-1999-10132 On-To-Knowledge On-To-Knowledge: Content-driven Knowledge management Tools through Evolving OntologiesDel 6: CORPORUM-OntoExtractOntology Extraction ToolRobert Engels, CognIT a.sIdentifier Class Version Version date
BYU - CS - 652
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BYU - CS - 652
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IIo[,.ttetr+^4i.lterm #z Mathematics 3150 2, Summer 2006 Department Mathemaiics, of Universityof Urah June 26, 2006Student ID Number:This is a closed-book, clGed nor6 exadination_ This exam besins at ll:00 a n. and ends ai 12:00 E.n sharD. Th6
Utah - MATH - 3150
On Sines and Cosines Math 3150Summer 2006Davar Khoshnevisan Department of Mathematics, The University of Utah 155 S. 1400 E. Salt Lake City, UT 841120090 May 20, 20061Trigonometry via Complex NumbersThe right denition of sin and cos is as foll