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mosdev2

Course: ECE 4273, Fall 2009
School: Mississippi State
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Word Count: 1545

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In 144. the following circuit what is (a) the threshold for transistor M2 when the output rises to V1 = 1.72 V, given the indicated set of (MOSIS) parameters. (b) Assume W1 = 20 m, W2 = 10 m and L2 = 4 m and determine the current through the transistors when V1 = 1.72V. Note that these are nMOS transistors. u o o~ } ) VV|R { % # # R # v 5 # Q 3k z...

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In 144. the following circuit what is (a) the threshold for transistor M2 when the output rises to V1 = 1.72 V, given the indicated set of (MOSIS) parameters. (b) Assume W1 = 20 m, W2 = 10 m and L2 = 4 m and determine the current through the transistors when V1 = 1.72V. Note that these are nMOS transistors. u o o~ } ) VV|R { % # # R # v 5 # Q 3k z VmXSyHyD"7xwbIIfWwdId7Pu S s Q # q p % t7!r \$f1WU l o Q # # 5 #v U # U # # l k % j Xk &7n7mW7H"S73WmU 1 ih) Q # ge ) w7rfd# fd U # 5 U U # b5 Q b 5 D70"" "IIDC x b u t sv b u t t q i f e b Q # Y 2 U R Q E C A 9 8 # 5 2 ) ' % # yITBIDTTrphgw6dcVH7X`X0WVTGFDB@f643Dd1(0d!Dd\$ 142. 105 pF/cm2, 48.3 nm, 104 pF/cm2, 0.632 V x I q x x t ' x WwD7 D Dt XB f o o~ } ) VV|R { z % # # R # v 5 # Q 3k DVmXSyHyD"7xwbIIfWwdId7Pu S s Q # q p % t7!r \$f1WU l o Q # # 5 #v U # U # # l k % j Xk &7n7mW7H"S73WmU 1 ih) Q # ge ) w7rfd# Xd U # 5 U U # b5 Q b 5 D70"" "IIDC x b u qv b u t s q i f e b Q # Y 2 U R Q E C A 9 8 # 5 2 ) ' % # yIwDTTrphg!\$dcVaH7X`X0WVTSDPIHG6FDB@!764310(&\$"! 141. Chapter 14 MOSFET DEVICE PROBLEMS version 2.2 N42W SPICE LEVEL 2 PARAMETERS .MODEL CMOSN NMOS LEVEL=2 PHI=0.600000 TOX=3.8100E08 XJ=0.200000U TPG=1 + VTO=0.8773 DELTA=8.1780E+00 LD=3.4510E07 KP=5.3438E05 + UO=589.6 UEXP=1.7180E01 UCRIT=8.4370E+04 RSH=1.8240E+01 + GAMMA=0.9516 NSUB=2.2410E+16 NFS=3.91E+11 VMAX=6.8840E+04 + LAMBDA=2.4560E02 CGDO=4.6917E10 CGSO=4.6917E10 .MODEL CMOSP PMOS LEVEL=2 PHI=0.600000 TOX=3.8100E08 XJ=0.200000U TPG=1 + VTO=0.7106 DELTA=1.3700E+00 LD=3.6020E07 KP=2.0945E05 + UO=231.1 UEXP=3.8580E01 UCRIT=7.9980E+04 RSH=6.6000E+01 + GAMMA=0.5159 NSUB=6.5870E+15 NFS=3.23E+11 VMAX=9.9990E+05 143. For an nMOS structure having gate oxide thickness tox = 45 nm and Si substrate doped at NA = 4 1016 #/cm3 find: (a) Oxide capacitance COX in pF/cm2 (b) Debye length, LB , of substrate (c) Fermi potential F. (d) Bulk coefficient GAMMA (= ) 105 pF/cm2, 20.5 nm, 0.382 V, 1.51 V +4.5V GND M1 M2 V1 u u x D XB + LAMBDA=5.3330E02 CGDO=4.8969E10 CGSO=4.8969E10 145. In the following circuit what is (a) the threshold for transistor M2 when the output falls to V1 = 2.68 V, given the indicated set of (MOSIS) parameters. (b) Assume W1 = 20 m, W2 = 10 m and L2 = 4 m and determine the current through the transistors when V1 = 2.68V. Note that these are pMOS transistors. N42W SPICE LEVEL 2 PARAMETERS .MODEL CMOSN NMOS LEVEL=2 PHI=0.600000 TOX=3.8100E08 XJ=0.200000U TPG=1 + VTO=0.8773 DELTA=8.1780E+00 LD=3.4510E07 KP=5.3438E05 + UO=589.6 UEXP=1.7180E01 UCRIT=8.4370E+04 RSH=1.8240E+01 + GAMMA=0.9516 NSUB=2.2410E+16 NFS=3.91E+11 VMAX=6.8840E+04 + LAMBDA=2.4560E02 CGDO=4.6917E10 CGSO=4.6917E10 .MODEL CMOSP PMOS LEVEL=2 PHI=0.600000 TOX=3.8100E08 XJ=0.200000U TPG=1 + VTO=0.7106 DELTA=1.3700E+00 LD=3.6020E07 KP=2.0945E05 + UO=231.1 UEXP=3.8580E01 UCRIT=7.9980E+04 RSH=6.6000E+01 + GAMMA=0.5159 NSUB=6.5870E+15 NFS=3.23E+11 VMAX=9.9990E+05 + LAMBDA=5.3330E02 CGDO=4.8969E10 CGSO=4.8969E10 146. A silicon gate nMOS transistor with TPG = +1, is made on a ptype substrate with NA = 4 1015 #/cm3. The SiO2 thickness is 45 nm, and trapped (+) oxide charge of area density Nox = 1.6 1010 #/cm2 is present. Determine: (a) VFB , and VTH . (b) Wd at VGS = VTH . Assume VSB = 0. (c) Find CMOS (min) (d) Using the values from (a) and (b) mark the corners for capacitance characteristics, and sketch the CV curve for this device. Be sure to identify (1) upper and lower capacitance limits, and (2) voltage rolloff points. 147. A silicon gate pMOS transistor with TPG = 1, is created on an ntype substrate with ND = 1 1015 #/cm3. The SiO2 thickness is 69 nm, and trapped (+) oxide charge of area density Nox = 1.6 1010 #/cm2 is present. Determine: (a) VFB , and VTH (assume VBS = 0). (b) Find Cox and CMOS (min) (c) Using the values from (a) and (b) mark corners for capacitance characterstics, and sketch the CV curve for this device. Identify upper and lower capacitance limits and voltage rolloff points (as you calculated in parts (a) and (b). B (a) (b) (c) (d) (e) (Assume that VBS = 0 V in determining these quantities.) GAMMA 0.8 V , VGS = 6.0 and VDS = 3.0 find: VTO (= zerobias threshold) Inversion charge/area QI at the source Inversion charge/area QI at the drain Depletion charge QB at the source Depletion charge QB at the drain. 148. For an nMOS transistor with VFB = 0.7V, Answers: 0.324 V, 1.277 V, 104 pF/cm2, 103 pF/cm2 = 0.9V, COX = 0.682 105 pF/cm2 , CFBS = 2.4 105 pF/cm2, +4.5V M1 V1 M2 GND 149. For VTO = 0.8V (a) (nMOS), VSB = 1 V (b) VSB = 2 V (c) VSB = 5 V B = 0.85 V and 1.2 V Answers: 1.326 V, 1.719 V, 2.60 V B (a) VBS = 1 V (b) VBS = 2 V (c) VBS = 5 V 1411. Find the threshold voltage for a highvoltage (= thick oxide) nMOS transistor which has tox = 0.8 m = 800 nm. Assume NB = 2 1015 #/cm3, VFB = 0.7 V, and B = Lindner potential = 2.1 F + 2.08 VT. In your analysis identify the value of gamma. Answers: 6.00 V , 4.995 V 1412. The gate oxide of a MOS device has a field strength (breaksdown field) of approximately 3.5 106 V/cm. Determine the maximum drain voltage VD for an oxide of thickness (a) 50 nm (b) 800 nm, assuming gate voltage VG = 2 V. 1413. The figure shown represents a crosssection of a CMOS inverter fabricated using a typical pwell CMOS process. Both the n and p channel inverters have a gate oxide thickness tox = 50 nm and n + polysilicon gates. The area density of oxide fixed trapped charge is Nox = 5 1010 #/cm2. The ntype susbstrate has a doping level ND = 2 1015 #/cm3 and the pwell has doping NA = 2 1016 #/cm3. a) Find the zerobias threshold voltages, VTN and VTP for these two transistors from the above information. Assume B = Lindner potential = 2.1 F + 2.08 VT. b) It is desired to shift the threshold voltages of the n and p channel transistors, as found in part (a), using an implant so that they are equal in magnitude, that is, VTN = VTP . To simplify processing, a blanket implant is applied, with all portions of the wafer receiving the same dose. Should a boron or a phosphorus implant be applied? What implant dose is required? thin oxide nMOS metal interconnect Field oxide p+ Field threshold adjust implant G n+ poly S n+ n+ D p+ metal interconnect Field oxide n+ nsubstrate Field threshold adjust implant G n+ poly S p+ p+ D pMOS metal interconnect Field oxide n+ pwell Figure P1413. CMOS device crosssection, pwell fabrication protocell Answers: (a) VTN = .757V, VTP = 1.335V, (b) NI = 1.38 1011 #/cm2 1410. For VTO = 1.0V, (pMOS), = 0.75 V and 0.7 V find VTH when the backgate bias is: find VTH when the backgate bias is: 1414. A highvoltage power MOSFET is constructed as shown. Note that this is a vertical transistor with an lightlydoped (n) layer (ND = 5 1014 #/cm3) in series with the drain. If this layer is 10 m thick and the breakdown voltage of Si is 3 105 V/cm, determine (a) the maximum reverse VDS that this transistor can withstand. (b) the series resistance of this layer for a transistor of gate dimensions 20 m 100 m. Assume n = 2/Vs. Note that most of the conduction takes place below the gate. 1300cm Figure 1414 The power MOSFET: (a) crosssections (b) ID vs VGS output characteristics, (c) ID vs VDS output characteristics. 1415. Find the implant dose NI of ions/cm2 needed to form (a) an nchannel enhancement transistor with VTH = +1.8V, using a Boron implant and (...

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