Architecture ARM Reference Manual
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100I
ARM Architecture Reference Manual
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
Release Information The following changes have been made to this document.
Change History Date February 1996 July 1997 April 1998 February 2000 June 2000 July 2004 December 2004 March 2005 July 2005 Issue A B C D E F G H I Change First edition Updated and index added Updated Updated for ARM architecture v5 Updated for ARM architecture v5TE and corrections to Part B Updated for ARM architecture v6 (Confidential) Updated to incorporate corrections to errata Updated to incorporate corrections to errata Updated to incorporate corrections to pseudocode and graphics
Proprietary Notice ARM, the ARM Powered logo, Thumb, and StrongARM are registered trademarks of ARM Limited. The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, PrimeCell, ARM7TDMI, ARM7TDMI-S, ARM9TDMI, ARM9E-S, ETM7, ETM9, TDMI, STRONG, are trademarks of ARM Limited. All other products or services mentioned herein may be trademarks of their respective owners. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. 1. Subject to the provisions set out below, ARM hereby grants to you a perpetual, non-exclusive, nontransferable, royalty free, worldwide licence to use this ARM Architecture Reference Manual for the purposes of developing; (i) software applications or operating systems which are targeted to run on microprocessor cores distributed under licence from ARM; (ii) tools which are designed to develop software programs which are targeted to run on microprocessor cores distributed under licence from ARM; (iii) or having developed integrated circuits which incorporate a microprocessor core manufactured under licence from ARM. 2. Except as expressly licensed in Clause 1 you acquire no right, title or interest in the ARM Architecture Reference Manual, or any Intellectual Property therein. In no event shall the licences granted in Clause 1, be construed as granting you expressly or by implication, estoppel or otherwise, licences to any ARM technology other than the ARM Architecture Reference Manual. The licence grant in Clause 1 expressly excludes any rights for you to use or take into use any ARM patents. No right is granted to you under the provisions of Clause 1 to; (i) use the ARM Architecture Reference Manual for the purposes of developing or having developed microprocessor cores or models thereof which are compatible in whole or part with either or both the instructions or programmer's models described in this ARM Architecture Reference
ii
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Manual; or (ii) develop or have developed models of any microprocessor cores designed by or for ARM; or (iii) distribute in whole or in part this ARM Architecture Reference Manual to third parties, other than to your subcontractors for the purposes of having developed products in accordance with the licence grant in Clause 1 without the express written permission of ARM; or (iv) translate or have translated this ARM Architecture Reference Manual into any other languages. 3.THE ARM ARCHITECTURE REFERENCE MANUAL IS PROVIDED "AS IS" WITH NO WARRANTIES EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE. 4. No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of Clause 1, to use the ARM tradename, in connection with the use of the ARM Architecture Reference Manual or any products based thereon. Nothing in Clause 1 shall be construed as authority for you to make any representations on behalf of ARM in respect of the ARM Architecture Reference Manual or any products based thereon. Copyright 1996-1998, 2000, 2004, 2005 ARM limited 110 Fulbourn Road Cambridge, England CB1 9NJ Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19 This document is Non-Confidential. The right to use, copy and disclose this document is subject to the licence set out above.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
iii
iv
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Contents ARM Architecture Reference Manual
Preface
About this manual ................................................................................ xii Architecture versions and variants ...................................................... xiii Using this manual .............................................................................. xviii Conventions ........................................................................................ xxi Further reading .................................................................................. xxiii Feedback .......................................................................................... xxiv
Part A
Chapter A1
CPU Architecture
Introduction to the ARM Architecture
A1.1 A1.2 A1.3 About the ARM architecture ............................................................. A1-2 ARM instruction set .......................................................................... A1-6 Thumb instruction set ..................................................................... A1-11
Chapter A2
Programmers Model
A2.1 A2.2 A2.3 A2.4 A2.5 Data types ........................................................................................ A2-2 Processor modes ............................................................................. A2-3 Registers .......................................................................................... A2-4 General-purpose registers ............................................................... A2-6 Program status registers ................................................................ A2-11
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
v
Contents
A2.6 A2.7 A2.8 A2.9 A2.10 A2.11
Exceptions ..................................................................................... Endian support ............................................................................... Unaligned access support .............................................................. Synchronization primitives ............................................................. The Jazelle Extension .................................................................... Saturated integer arithmetic ...........................................................
A2-16 A2-30 A2-38 A2-44 A2-53 A2-69
Chapter A3
The ARM Instruction Set
A3.1 A3.2 A3.3 A3.4 A3.5 A3.6 A3.7 A3.8 A3.9 A3.10 A3.11 A3.12 A3.13 A3.14 A3.15 A3.16 Instruction set encoding ................................................................... A3-2 The condition field ............................................................................ A3-3 Branch instructions .......................................................................... A3-5 Data-processing instructions ............................................................ A3-7 Multiply instructions ........................................................................ A3-10 Parallel addition and subtraction instructions ................................. A3-14 Extend instructions ......................................................................... A3-16 Miscellaneous arithmetic instructions ............................................ A3-17 Other miscellaneous instructions ................................................... A3-18 Status register access instructions ................................................ A3-19 Load and store instructions ............................................................ A3-21 Load and Store Multiple instructions .............................................. A3-26 Semaphore instructions ................................................................. A3-28 Exception-generating instructions .................................................. A3-29 Coprocessor instructions ............................................................... A3-30 Extending the instruction set .......................................................... A3-32
Chapter A4
ARM Instructions
A4.1 A4.2 Alphabetical list of ARM instructions ................................................ A4-2 ARM instructions and architecture versions ................................. A4-286
Chapter A5
ARM Addressing Modes
A5.1 A5.2 A5.3 A5.4 A5.5 Addressing Mode 1 - Data-processing operands ............................. A5-2 Addressing Mode 2 - Load and Store Word or Unsigned Byte ...... A5-18 Addressing Mode 3 - Miscellaneous Loads and Stores ................. A5-33 Addressing Mode 4 - Load and Store Multiple ............................... A5-41 Addressing Mode 5 - Load and Store Coprocessor ....................... A5-49
Chapter A6
The Thumb Instruction Set
A6.1 A6.2 A6.3 A6.4 A6.5 A6.6 A6.7 A6.8 About the Thumb instruction set ...................................................... A6-2 Instruction set encoding ................................................................... A6-4 Branch instructions .......................................................................... A6-6 Data-processing instructions ............................................................ A6-8 Load and Store Register instructions ............................................. A6-15 Load and Store Multiple instructions .............................................. A6-18 Exception-generating instructions .................................................. A6-20 Undefined Instruction space .......................................................... A6-21
vi
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Contents
Chapter A7
Thumb Instructions
A7.1 A7.2 Alphabetical list of Thumb instructions ............................................. A7-2 Thumb instructions and architecture versions .............................. A7-125
Part B
Chapter B1
Memory and System Architectures
Introduction to Memory and System Architectures
B1.1 B1.2 B1.3 B1.4 B1.5 B1.6 B1.7 B1.8 About the memory system ............................................................... B1-2 Memory hierarchy ............................................................................ B1-4 L1 cache .......................................................................................... B1-6 L2 cache .......................................................................................... B1-7 Write buffers ..................................................................................... B1-8 Tightly Coupled Memory .................................................................. B1-9 Asynchronous exceptions .............................................................. B1-10 Semaphores ................................................................................... B1-12
Chapter B2
Memory Order Model
B2.1 B2.2 B2.3 B2.4 B2.5 B2.6 B2.7 About the memory order model ........................................................ B2-2 Read and write definitions ................................................................ B2-4 Memory attributes prior to ARMv6 ................................................... B2-7 ARMv6 memory attributes - introduction .......................................... B2-8 Ordering requirements for memory accesses ................................ B2-16 Memory barriers ............................................................................. B2-18 Memory coherency and access issues .......................................... B2-20
Chapter B3
The System Control Coprocessor
B3.1 B3.2 B3.3 B3.4 B3.5 About the System Control coprocessor ............................................ B3-2 Registers .......................................................................................... B3-3 Register 0: ID codes ........................................................................ B3-7 Register 1: Control registers .......................................................... B3-12 Registers 2 to 15 ............................................................................ B3-18
Chapter B4
Virtual Memory System Architecture
B4.1 B4.2 B4.3 B4.4 B4.5 B4.6 B4.7 B4.8 B4.9 About the VMSA .............................................................................. B4-2 Memory access sequence ............................................................... B4-4 Memory access control .................................................................... B4-8 Memory region attributes ............................................................... B4-11 Aborts ............................................................................................. B4-14 Fault Address and Fault Status registers ....................................... B4-19 Hardware page table translation .................................................... B4-23 Fine page tables and support of tiny pages ................................... B4-35 CP15 registers ............................................................................... B4-39
Chapter B5
Protected Memory System Architecture
B5.1 About the PMSA .............................................................................. B5-2
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
vii
Contents
B5.2 B5.3 B5.4 B5.5 B5.6 B5.7
Memory access sequence ............................................................... B5-4 Memory access control .................................................................... B5-8 Memory access attributes .............................................................. B5-10 Memory aborts (PMSAv6) .............................................................. B5-13 Fault Status and Fault Address register support ............................ B5-16 CP15 registers ............................................................................... B5-18
Chapter B6
Caches and Write Buffers
B6.1 B6.2 B6.3 B6.4 B6.5 B6.6 About caches and write buffers ........................................................ B6-2 Cache organization .......................................................................... B6-4 Types of cache ................................................................................. B6-7 L1 cache ........................................................................................ B6-10 Considerations for additional levels of cache ................................. B6-12 CP15 registers ............................................................................... B6-13
Chapter B7
Tightly Coupled Memory
B7.1 B7.2 B7.3 B7.4 B7.5 About TCM ....................................................................................... TCM configuration and control ......................................................... Accesses to TCM and cache ........................................................... Level 1 (L1) DMA model .................................................................. L1 DMA control using CP15 Register 11 ......................................... B7-2 B7-3 B7-7 B7-8 B7-9
Chapter B8
Fast Context Switch Extension
B8.1 B8.2 B8.3 B8.4 B8.5 About the FCSE ............................................................................... Modified virtual addresses ............................................................... Enabling the FCSE .......................................................................... Debug and Trace ............................................................................. CP15 registers ................................................................................. B8-2 B8-3 B8-5 B8-6 B8-7
Part C
Chapter C1
Vector Floating-point Architecture
Introduction to the Vector Floating-point Architecture
C1.1 C1.2 C1.3 C1.4 About the Vector Floating-point architecture .................................... C1-2 Overview of the VFP architecture .................................................... C1-4 Compliance with the IEEE 754 standard ......................................... C1-9 IEEE 754 implementation choices ................................................. C1-10
Chapter C2
VFP Programmers Model
C2.1 C2.2 C2.3 C2.4 C2.5 C2.6 C2.7 Floating-point formats ...................................................................... C2-2 Rounding .......................................................................................... C2-9 Floating-point exceptions ............................................................... C2-10 Flush-to-zero mode ........................................................................ C2-14 Default NaN mode ......................................................................... C2-16 Floating-point general-purpose registers ....................................... C2-17 System registers ............................................................................ C2-21
viii
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Contents
C2.8
Reset behavior and initialization .................................................... C2-29
Chapter C3
VFP Instruction Set Overview
C3.1 C3.2 C3.3 C3.4 Data-processing instructions ............................................................ C3-2 Load and Store instructions ........................................................... C3-14 Single register transfer instructions ................................................ C3-18 Two-register transfer instructions ................................................... C3-22
Chapter C4 Chapter C5
VFP Instructions
C4.1 Alphabetical list of VFP instructions ................................................. C4-2
VFP Addressing Modes
C5.1 C5.2 C5.3 C5.4 C5.5 Addressing Mode 1 - Single-precision vectors (non-monadic) ......... C5-2 Addressing Mode 2 - Double-precision vectors (non-monadic) ....... C5-8 Addressing Mode 3 - Single-precision vectors (monadic) .............. C5-14 Addressing Mode 4 - Double-precision vectors (monadic) ............ C5-18 Addressing Mode 5 - VFP load/store multiple ................................ C5-22
Part D
Chapter D1
Debug Architecture
Introduction to the Debug Architecture
D1.1 D1.2 D1.3 Introduction ...................................................................................... D1-2 Trace ................................................................................................ D1-4 Debug and ARMv6 ........................................................................... D1-5
Chapter D2
Debug Events and Exceptions
D2.1 D2.2 D2.3 D2.4 Introduction ...................................................................................... D2-2 Monitor debug-mode ........................................................................ D2-5 Halting debug-mode ......................................................................... D2-8 External Debug Interface ............................................................... D2-13
Chapter D3
Coprocessor 14, the Debug Coprocessor
D3.1 D3.2 D3.3 D3.4 D3.5 Coprocessor 14 debug registers ...................................................... D3-2 Coprocessor 14 debug instructions .................................................. D3-5 Debug register reference ................................................................. D3-8 Reset values of the CP14 debug registers ..................................... D3-24 Access to CP14 debug registers from the external debug interface ......... D3-25
Glossary
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ix
Contents
x
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Preface
This preface describes the versions of the ARM architecture and the contents of this manual, then lists the conventions and terminology it uses. About this manual on page xii Architecture versions and variants on page xiii Using this manual on page xviii Conventions on page xxi Further reading on page xxiii Feedback on page xxiv.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
xi
Preface
About this manual
The purpose of this manual is to describe the ARM instruction set architecture, including its high code density Thumb subset, and three of its standard coprocessor extensions: The standard System Control coprocessor (coprocessor 15), which is used to control memory system components such as caches, write buffers, Memory Management Units, and Protection Units. The Vector Floating-point (VFP) architecture, which uses coprocessors 10 and 11 to supply a high-performance floating-point instruction set. The debug architecture interface (coprocessor 14), formally added to the architecture in ARM v6 to provide software access to debug features in ARM cores, (for example, breakpoint and watchpoint control).
The 32-bit ARM and 16-bit Thumb instruction sets are described separately in Part A. The precise effects of each instruction are described, including any restrictions on its use. This information is of primary importance to authors of compilers, assemblers, and other programs that generate ARM machine code. Assembler syntax is given for most of the instructions described in this manual, allowing instructions to be specified in textual form. However, this manual is not intended as tutorial material for ARM assembler language, nor does it describe ARM assembler language at anything other than a very basic level. To make effective use of ARM assembler language, consult the documentation supplied with the assembler being used. The memory and system architecture definition is significantly improved in ARM architecture version 6 (the latest version). Prior to this, it usually needs to be supplemented by detailed implementation-specific information from the technical reference manual of the device being used.
xii
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Preface
Architecture versions and variants
The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. Six major versions of the instruction set have been defined to date, denoted by the version numbers 1 to 6. Of these, the first three versions including the original 26-bit architecture (the 32-bit architecture was introduced at ARMv3) are now OBSOLETE. All bits and encodings that were used for 26-bit features become RESERVED for future expansion by ARM Ltd. Versions can be qualified with variant letters to specify collections of additional instructions that are included as an architecture extension. Extensions are typically included in the base architecture of the next version number, ARMv5T being the notable exception. Provision is also made to exclude variants by prefixing the variant letter with x, for example the xP variant described below in the summary of version 5 features.
Note
The xM variant which indicates that long multiplies (32 x 32 multiplies with 64-bit results) are not supported, has been withdrawn. The valid architecture variants are as follows (variant in brackets for legacy reasons only): ARMv4, ARMv4T, ARMv5T, (ARMv5TExP), ARMv5TE, ARMv5TEJ, and ARMv6 The following architecture variants are now OBSOLETE: ARMv1, ARMv2, ARMv2a, ARMv3, ARMv3G, ARMv3M, ARMv4xM, ARMv4TxM, ARMv5, ARMv5xM, and ARMv5TxM Details on OBSOLETE versions are available on request from ARM. The ARM and Thumb instruction sets are summarized by architecture variant in ARM instructions and architecture versions on page A4-286 and Thumb instructions and architecture versions on page A7-125 respectively. The key differences introduced since ARMv4 are listed below.
Version 4 and the introduction of Thumb (T variant)
The Thumb instruction set is a re-encoded subset of the ARM instruction set. Thumb instructions execute in their own processor state, with the architecture defining the mechanisms required to transition between ARM and Thumb states. The key difference is that Thumb instructions are half the size of ARM instructions (16 bits compared with 32 bits). Greater code density can usually be achieved by using the Thumb instruction set in preference to the ARM instruction set. However, the Thumb instruction set does have some limitations: Thumb code usually uses more instructions for a given task, making ARM code best for maximizing performance of time-critical code. ARM state and some associated ARM instructions are required for exception handling.
The Thumb instruction set is always used in conjunction with a version of the ARM instruction set.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
xiii
Preface
New features in Version 5T
This version extended architecture version 4T as follows: Improved efficiency of ARM/Thumb interworking Count leading zeros (CLZ, ARM only) and software breakpoint (BKPT, ARM and Thumb) instructions added Additional options for coprocessor designers (coprocessor support is ARM only) Tighter definition of flag setting on multiplies (ARM and Thumb) Introduction of the E variant, adding ARM instructions which enhance performance of an ARM processor on typical digital signal processing (DSP) algorithms: Several multiply and multiply-accumulate instructions that act on 16-bit data items. Addition and subtraction instructions that perform saturated signed arithmetic. Saturated arithmetic produces the maximum positive or negative value instead of wrapping the result if the calculation overflows the normal integer range. Load (LDRD), store (STRD) and coprocessor register transfer (MCRR and MRRC) instructions that act on two words of data. A preload data instruction PLD.
Introduction of the J variant, adding the BXJ instruction and the other provisions required to support the Jazelle architecture extension.
Note
Some early implementations of the E variant omitted the LDRD, STRD, MCRR, MRCC and PLD instructions. These are designated as conforming to the ExP variant, and the variant is defined for legacy reasons only.
xiv
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Preface
New features in Version 6
The following ARM instructions are added:
CPS, SRS and RFE instructions for improved exception handling REV, REV16 and REVSH byte reversal instructions SETEND for a revised endian (memory) model LDREX and STREX exclusive access instructions SXTB, SXTH, UXTB, UXTH byte/halfword extend instructions
A set of Single Instruction Multiple Data (SIMD) media instructions Additional forms of multiply instructions with accumulation into a 64-bit result.
The following Thumb instructions are added:
CPS, CPY (a form of MOV), REV, REV16, REVSH, SETEND, SXTB, SXTH, UXTB, UXTH
Other changes to ARMv6 are as follows: The architecture name ARMv6 implies the presence of all preceding features, that is, ARMv5TEJ compliance. Revised Virtual and Protected Memory System Architectures. Provision of a Tightly Coupled Memory model. New hardware support for word and halfword unaligned accesses. Formalized adoption of a debug architecture with external and Coprocessor 14 based interfaces. Prior to ARMv6, the System Control coprocessor (CP15) described in Chapter B3 was a recommendation only. Support for this coprocessor is now mandated in ARMv6. For historical reasons, the rules relating to unaligned values written to the PC are somewhat complex prior to ARMv6. These rules are made simpler and more consistent in ARMv6. The high vectors extension prior to ARMv6 is an optional (IMPLEMENTATION DEFINED) part of the architecture. This extension becomes obligatory in ARMv6. Prior to ARMv6, a processor may use either of two abort models. ARMv6 requires that the Base Restored Abort Model (BRAM) is used. The two abort models supported previously were: The BRAM, in which the base register of any valid load/store instruction that causes a memory system abort is always restored to its pre-instruction value. The Base Updated Abort Model (BUAM), in which the base register of any valid load/store instruction that causes a memory system abort will have been modified by the base register writeback (if any) of that instruction.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
xv
Preface
The restriction that multiplication destination registers should be different from their source registers is removed in ARMv6. In ARMv5, the LDM(2) and STM(2) ARM instructions have restrictions on the use of banked registers by the immediately following instruction. These restrictions are removed from ARMv6. The rules determining which PSR bits are updated by an MSR instruction are clarified and extended to cover the new PSR bits defined in ARMv6. In ARMv5, the Thumb MOV instruction behavior varies according to the registers used (see note). Two changes are made in ARMv6. The restriction about the use of low register numbers in the MOV (3) instruction encoding is removed. In order to make the new side-effect-free MOV instructions available to the assembler language programmer without changing the meaning of existing assembler sources, a new assembler syntax CPY Rd,Rn is introduced. This always assembles to the MOV (3) instruction regardless of whether Rd and Rn are high or low registers.
Note
In ARMv5, the Thumb MOV Rd,Rn instructions have the following properties: If both Rd and Rn are low registers, the instruction is the MOV (2) instruction. This instruction sets the N and Z flags according to the value transferred, and sets the C and V flags to 0. If either Rd or Rn is a high register, the instruction is the MOV (3) instruction. This instruction leaves the condition flags unchanged.
This situation results in behavior that varies according to the registers used. The MOV(2) side-effects also limit compiler flexibility on use of pseudo-registers in a global register allocator.
Naming of ARM/Thumb architecture versions
To name a precise version and variant of the ARM/Thumb architecture, the following strings are concatenated: 1. The string ARMv. 2. The version number of the ARM instruction set. 3. Variant letters of the included variants. 4. In addition, the letter P is used after x to denote the exclusion of several instructions in the ARMv5TExP variant. The table Architecture versions on page xvii lists the standard names of the current (not obsolete) ARM/Thumb architecture versions described in this manual. These names provide a shorthand way of describing the precise instruction set implemented by an ARM processor. However, this manual normally uses descriptive phrases such as T variants of architecture version 4 and above to avoid the use of lists of architecture names.
xvi
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Preface
All architecture names prior to ARMv4 are now OBSOLETE. The term all is used throughout this manual to refer to all architecture versions from ARMv4 onwards.
Architecture versions Name ARMv4 ARMv4T ARMv5T ARMv5TExP ARM instruction set version 4 4 5 5 Thumb instruction set version None 1 2 2 Notes Enhanced DSP instructions except
LDRD, MCRR, MRRC, PLD, and STRD
ARMv5TE ARMv5TEJ
5 5
2 2
Enhanced DSP instructions Addition of BXJ instruction and Jazelle Extension support over ARMv5TE Additional instructions as listed in Table A4-2 on page A4-286 and Table A7-1 on page A7-125.
ARMv6
6
3
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
xvii
Preface
Using this manual
The information in this manual is organized into four parts, as described below.
Part A - CPU Architectures
Part A describes the ARM and Thumb instruction sets, and contains the following chapters: Chapter A1 Chapter A2 Gives a brief overview of the ARM architecture, and the ARM and Thumb instruction sets. Describes the types of value that ARM instructions operate on, the general-purpose registers that contain those values, and the Program Status Registers. This chapter also describes how ARM processors handle interrupts and other exceptions, endian and unaligned support, information on + synchronization primitives, and the Jazelle extension. Gives a description of the ARM instruction set, organized by type of instruction. Contains detailed reference material on each ARM instruction, arranged alphabetically by instruction mnemonic. Contains detailed reference material on the addressing modes used by ARM instructions. The term addressing mode is interpreted broadly in this manual, to mean a procedure shared by many different instructions, for generating values used by the instructions. For four of the addressing modes described in this chapter, the values generated are memory addresses (which is the traditional role of an addressing mode). The remaining addressing mode generates values to be used as operands by data-processing instructions. Gives a description of the Thumb instruction set, organized by type of instruction. This chapter also contains information about how to switch between the ARM and Thumb instruction sets, and how exceptions that arise during Thumb state execution are handled. Contains detailed reference material on each Thumb instruction, arranged alphabetically by instruction mnemonic.
Chapter A3 Chapter A4 Chapter A5
Chapter A6
Chapter A7
xviii
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Preface
Part B - Memory and System Architectures
Part B describes standard memory system features that are normally implemented by the System Control coprocessor (coprocessor 15) in an ARM-based system. It contains the following chapters: Chapter B1 Chapter B2 Chapter B3 Chapter B4 Chapter B5 Chapter B6 Gives a brief overview of this part of the manual. The memory order model. Gives a general description of the System Control coprocessor and its use. Describes the standard ARM memory and system architecture based on the use of a Virtual Memory System Architecture (VMSA) based on a Memory Management Unit (MMU). Gives a description of the simpler Protected Memory System Architecture (PMSA) based on a Memory Protection Unit (MPU). Gives a description of the standard ways to control caches and write buffers in ARM memory systems. This chapter is relevant both to systems based on an MMU and to systems based on an MPU. Describes the Tightly Coupled Memory (TCM) architecture option for level 1 memory. Describes the Fast Context Switch Extension and Context ID support (ARMv6 only).
Chapter B7 Chapter B8
Part C - Vector Floating-point Architecture
Part C describes the Vector Floating-point (VFP) architecture. This is a coprocessor extension to the ARM architecture designed for high floating-point performance on typical graphics and DSP algorithms. Chapter C1 Chapter C2 Chapter C3 Chapter C4 Chapter C5 Gives a brief overview of the VFP architecture and information about its compliance with the IEEE 754-1985 floating-point arithmetic standard. Describes the floating-point formats supported by the VFP instruction set, the floating-point general-purpose registers that hold those values, and the VFP system registers. Describes the VFP coprocessor instruction set, organized by type of instruction. Contains detailed reference material on the VFP coprocessor instruction set, organized alphabetically by instruction mnemonic. Contains detailed reference material on the addressing modes used by VFP instructions. One of these is a traditional addressing mode, generating addresses for load/store instructions. The remainder specify how the floating-point general-purpose registers and instructions can be used to hold and perform calculations on vectors of floating-point values.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
xix
Preface
Part D - Debug Architecture
Part D describes the debug architecture. This is a coprocessor extension to the ARM architecture designed to provide configuration, breakpoint and watchpoint support, and a Debug Communications Channel (DCC) to a debug host. Chapter D1 Chapter D2 Chapter D3 Gives a brief introduction to the debug architecture. Describes the key features of the debug architecture. Describes the Coprocessor Debug Register support (cp14) for the debug architecture.
xx
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Preface
Conventions
This manual employs typographic and other conventions intended to improve its ease of use.
General typographic conventions
typewriter
Is used for assembler syntax descriptions, pseudo-code descriptions of instructions, and source code examples. In the cases of assembler syntax descriptions and pseudo-code descriptions, see the additional conventions below. The typewriter font is also used in the main text for instruction mnemonics and for references to other items appearing in assembler syntax descriptions, pseudo-code descriptions of instructions and source code examples.
italic bold
SMALL CAPITALS
Highlights important notes, introduces special terminology, and denotes internal cross-references and citations. Is used for emphasis in descriptive lists and elsewhere, where appropriate. Are used for a few terms which have specific technical meanings. Their meanings can be found in the Glossary.
Pseudo-code descriptions of instructions
A form of pseudo-code is used to provide precise descriptions of what instructions do. This pseudo-code is written in a typewriter font, and uses the following conventions for clarity and brevity: Indentation is used to indicate structure. For example, the range of statements that a for statement loops over, goes from the for statement to the next statement at the same or lower indentation level as the for statement (both ends exclusive). Comments are bracketed by /* and */, as in the C language. English text is occasionally used outside comments to describe functionality that is hard to describe otherwise. All keywords and special functions used in the pseudo-code are described in the Glossary. Assignment and equality tests are distinguished by using = for an assignment and == for an equality test, as in the C language. Instruction fields are referred to by the names shown in the encoding diagram for the instruction. When an instruction field denotes a register, a reference to it means the value in that register, rather than the register number, unless the context demands otherwise. For example, a Rn == 0 test is checking whether the value in the specified register is 0, but a Rd is R15 test is checking whether the specified register is register 15. When an instruction uses an addressing mode, the pseudo-code for that addressing mode generates one or more values that are used in the pseudo-code for the instruction. For example, the AND instruction described in AND on page A4-8 uses ARM addressing mode 1 (see Addressing Mode 1 Data-processing operands on page A5-2). The pseudo-code for the addressing mode generates two values shifter_operand and shifter_carry_out, which are used by the pseudo-code for the AND instruction.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
xxi
Preface
Assembler syntax descriptions
This manual contains numerous syntax descriptions for assembler instructions and for components of assembler instructions. These are shown in a typewriter font, and are as follows:
<>
Any item bracketed by < and > is a short description of a type of value to be supplied by the user in that position. A longer description of the item is normally supplied by subsequent text. Such items often correspond to a similarly named field in an encoding diagram for an instruction. When the correspondence simply requires the binary encoding of an integer value or register number to be substituted into the instruction encoding, it is not described explicitly. For example, if the assembler syntax for an ARM instruction contains an item <Rn> and the instruction encoding diagram contains a 4-bit field named Rn, the number of the register specified in the assembler syntax is encoded in binary in the instruction field. If the correspondence between the assembler syntax item and the instruction encoding is more complex than simple binary encoding of an integer or register number, the item description indicates how it is encoded.
{}
Any item bracketed by { and } is optional. A description of the item and of how its presence or absence is encoded in the instruction is normally supplied by subsequent text. This indicates an alternative character string. For example, LDM|STM is either LDM or STM. Single spaces are used for clarity, to separate items. When a space is obligatory in the assembler syntax, two or more consecutive spaces are used. This indicates an optional + or - sign. If neither is coded, + is assumed. When used in a combination like <immed_8> * 4, this describes an immediate value which must be a specified multiple of a value taken from a numeric range. In this instance, the numeric range is 0 to 255 (the set of values that can be represented as an 8-bit immediate) and the specified multiple is 4, so the value described must be a multiple of 4 in the range 4*0 = 0 to 4*255 = 1020.
|
spaces
+/*
All other characters must be encoded precisely as they appear in the assembler syntax. Apart from { and }, the special characters described above do not appear in the basic forms of assembler instructions documented in this manual. The { and } characters need to be encoded in a few places as part of a variable item. When this happens, the long description of the variable item indicates how they must be used.
Note
This manual only attempts to describe the most basic forms of assembler instruction syntax. In practice, assemblers normally recognize a much wider range of instruction syntaxes, as well as various directives to control the assembly process and additional features such as symbolic manipulation and macro expansion. All of these are beyond the scope of this manual.
xxii
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Preface
Further reading
This section lists publications from both ARM Limited and third parties that provide additional information on the ARM family of processors. ARM periodically provides updates and corrections to its documentation. See http://www.arm.com for current errata sheets and addenda, and the ARM Frequently Asked Questions.
ARM publications
ARM External Debug Interface Specification.
External publications
The following books are referred to in this manual, or provide additional information: IEEE Standard for Shared-Data Formats Optimized for Scalable Coherent Interface (SCI) Processors, IEEE Std 1596.5-1993, ISBN 1-55937-354-7, IEEE). The Java Virtual Machine Specification Second Edition, Tim Lindholm and Frank Yellin, published by Addison Wesley (ISBN: 0-201-43294-3) JTAG Specification IEEE1149.1
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
xxiii
Preface
Feedback
ARM Limited welcomes feedback on its documentation.
Feedback on this book
If you notice any errors or omissions in this book, send email to errata@arm giving: the document title the document number the page number(s) to which your comments apply a concise explanation of the problem. General suggestions for additions and improvements are also welcome.
xxiv
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Part A
CPU Architecture
Chapter A1 Introduction to the ARM Architecture
This chapter introduces the ARM architecture and contains the following sections: About the ARM architecture on page A1-2 ARM instruction set on page A1-6 Thumb instruction set on page A1-11.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A1-1
Introduction to the ARM Architecture
A1.1
About the ARM architecture
The ARM architecture has evolved to a point where it supports implementations across a wide spectrum of performance points. Over two billion parts have shipped, establishing it as the dominant architecture across many market segments. The architectural simplicity of ARM processors has traditionally led to very small implementations, and small implementations allow devices with very low power consumption. Implementation size, performance, and very low power consumption remain key attributes in the development of the ARM architecture. The ARM is a Reduced Instruction Set Computer (RISC), as it incorporates these typical RISC architecture features: a large uniform register file a load/store architecture, where data-processing operations only operate on register contents, not directly on memory contents simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only uniform and fixed-length instruction fields, to simplify instruction decode.
In addition, the ARM architecture provides: control over both the Arithmetic Logic Unit (ALU) and shifter in most data-processing instructions to maximize the use of an ALU and a shifter auto-increment and auto-decrement addressing modes to optimize program loops Load and Store Multiple instructions to maximize data throughput conditional execution of almost all instructions to maximize execution throughput.
These enhancements to a basic RISC architecture allow ARM processors to achieve a good balance of high performance, small code size, low power consumption, and small silicon area.
A1-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to the ARM Architecture
A1.1.1
ARM registers
ARM has 31 general-purpose 32-bit registers. At any one time, 16 of these registers are visible. The other registers are used to speed up exception processing. All the register specifiers in ARM instructions can address any of the 16 visible registers. The main bank of 16 registers is used by all unprivileged code. These are the User mode registers. User mode is different from all other modes as it is unprivileged, which means: User mode can only switch to another processor mode by generating an exception. The SWI instruction provides this facility from program control. Memory systems and coprocessors might allow User mode less access to memory and coprocessor functionality than a privileged mode.
Three of the 16 visible registers have special roles: Stack pointer Link register Software normally uses R13 as a Stack Pointer (SP). R13 is used by the PUSH and POP instructions in T variants, and by the SRS and RFE instructions from ARMv6. Register 14 is the Link Register (LR). This register holds the address of the next instruction after a Branch and Link (BL or BLX) instruction, which is the instruction used to make a subroutine call. It is also used for return address information on entry to exception modes. At all other times, R14 can be used as a general-purpose register. Register 15 is the Program Counter (PC). It can be used in most instructions as a pointer to the instruction which is two instructions after the instruction being executed. In ARM state, all ARM instructions are four bytes long (one 32-bit word) and are always aligned on a word boundary. This means that the bottom two bits of the PC are always zero, and therefore the PC contains only 30 non-constant bits. Two other processor states are supported by some versions of the architecture. Thumb state is supported on T variants, and Jazelle state on J variants. The PC can be halfword (16-bit) and byte aligned respectively in these states.
Program counter
The remaining 13 registers have no special hardware purpose. Their uses are defined purely by software. For more details on registers, refer to Registers on page A2-4.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A1-3
Introduction to the ARM Architecture
A1.1.2
Exceptions
ARM supports seven types of exception, and a privileged processing mode for each type. The seven types of exception are: reset attempted execution of an Undefined instruction software interrupt (SWI) instructions, can be used to make a call to an operating system Prefetch Abort, an instruction fetch memory abort Data Abort, a data access memory abort IRQ, normal interrupt FIQ, fast interrupt. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for R13 and R14. The fast interrupt mode has additional banked registers for fast interrupt processing. When an exception handler is entered, R14 holds the return address for exception processing. This is used to return after the exception is processed and to address the instruction that caused the exception. Register 13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without the need to save or restore these registers. There is a sixth privileged processing mode, System mode, which uses the User mode registers. This is used to run tasks that require privileged access to memory and/or coprocessors, without limitations on which exceptions can occur during the task. In addition to the above, reset shares the same privileged mode as SWIs. For more details on exceptions, refer to Exceptions on page A2-16.
The exception process
When an exception occurs, the ARM processor halts execution in a defined manner and begins execution at one of a number of fixed addresses in memory, known as the exception vectors. There is a separate vector location for each exception, including reset. Behavior is defined for normal running systems (see section A2.6) and debug events (see Chapter D3 Coprocessor 14, the Debug Coprocessor) An operating system installs a handler on every exception at initialization. Privileged operating system tasks are normally run in System mode to allow exceptions to occur within the operating system without state loss.
A1-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to the ARM Architecture
A1.1.3
Status registers
All processor state other than the general-purpose register contents is held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: four condition code flags (Negative, Zero, Carry and oVerflow). one sticky (Q) flag (ARMv5 and above only). This encodes whether saturation has occurred in saturated arithmetic instructions, or signed overflow in some specific multiply accumulate instructions. four GE (Greater than or Equal) flags (ARMv6 and above only). These encode the following conditions separately for each operation in parallel instructions: whether the results of signed operations were non-negative whether unsigned operations produced a carry or a borrow. two interrupt disable bits, one for each type of interrupt (two in ARMv5 and below). one (A) bit imprecise abort mask (from ARMv6) five bits that encode the current processor mode. two bits that encode whether ARM instructions, Thumb instructions, or Jazelle opcodes are being executed. one bit that controls the endianness of load and store operations (ARMv6 and above only). Each exception mode also has a Saved Program Status Register (SPSR) which holds the CPSR of the task immediately before the exception occurred. The CPSR and the SPSRs are accessed with special instructions. For more details on status registers, refer to Program status registers on page A2-11. Table A1-1 Status register summary
Field
NZCV J GE[3:0] E A I F T Mode[4:0]
Description Condition code flags Jazelle state flag SIMD condition flags Endian Load/Store Imprecise Abort Mask IRQ Interrupt Mask FIQ Interrupt Mask Thumb state flag Processor mode
Architecture All 5TEJ and above 6 6 6 All All 4T and above All
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A1-5
Introduction to the ARM Architecture
A1.2
ARM instruction set
The ARM instruction set can be divided into six broad classes of instruction: Branch instructions Data-processing instructions on page A1-7 Status register transfer instructions on page A1-8 Load and store instructions on page A1-8 Coprocessor instructions on page A1-10 Exception-generating instructions on page A1-10. Most data-processing instructions and one type of coprocessor instruction can update the four condition code flags in the CPSR (Negative, Zero, Carry and oVerflow) according to their result. Almost all ARM instructions contain a 4-bit condition field. One value of this field specifies that the instruction is executed unconditionally. Fourteen other values specify conditional execution of the instruction. If the condition code flags indicate that the corresponding condition is true when the instruction starts executing, it executes normally. Otherwise, the instruction does nothing. The 14 available conditions allow: tests for equality and non-equality tests for <, <=, >, and >= inequalities, in both signed and unsigned arithmetic each condition code flag to be tested individually. The sixteenth value of the condition field encodes alternative instructions. These do not allow conditional execution. Before ARMv5 these instructions were UNPREDICTABLE.
A1.2.1
Branch instructions
As well as allowing many data-processing or load instructions to change control flow by writing the PC, a standard Branch instruction is provided with a 24-bit signed word offset, allowing forward and backward branches of up to 32MB. There is a Branch and Link (BL) option that also preserves the address of the instruction after the branch in R14, the LR. This provides a subroutine call which can be returned from by copying the LR into the PC. There are also branch instructions which can switch instruction set, so that execution continues at the branch target using the Thumb instruction set or Jazelle opcodes. Thumb support allows ARM code to call Thumb subroutines, and ARM subroutines to return to a Thumb caller. Similar instructions in the Thumb instruction set allow the corresponding Thumb ARM switches. An overview of the Thumb instruction set is provided in Chapter A6 The Thumb Instruction Set. The BXJ instruction introduced with the J variant of ARMv5, and present in ARMv6, provides the architected mechanism for entry to Jazelle state, and the associated assertion of the J flag in the CPSR.
A1-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to the ARM Architecture
A1.2.2
Data-processing instructions
The data-processing instructions perform calculations on the general-purpose registers. There are five types of data-processing instructions: Arithmetic/logic instructions Comparison instructions Single Instruction Multiple Data (SIMD) instructions Multiply instructions on page A1-8 Miscellaneous Data Processing instructions on page A1-8.
Arithmetic/logic instructions
The following arithmetic/logic instructions share a common instruction format. These perform an arithmetic or logical operation on up to two source operands, and write the result to a destination register. They can also optionally update the condition code flags, based on the result. Of the two source operands: one is always a register the other has two basic forms: an immediate value a register value, optionally shifted. If the operand is a shifted register, the shift amount can be either an immediate value or the value of another register. Five types of shift can be specified. Every arithmetic/logic instruction can therefore perform an arithmetic/logic operation and a shift operation. As a result, ARM does not have dedicated shift instructions. The Program Counter (PC) is a general-purpose register, and therefore arithmetic/logic instructions can write their results directly to the PC. This allows easy implementation of a variety of jump instructions.
Comparison instructions
The comparison instructions use the same instruction format as the arithmetic/logic instructions. These perform an arithmetic or logical operation on two source operands, but do not write the result to a register. They always update the condition flags, based on the result. The source operands of comparison instructions take the same forms as those of arithmetic/logic instructions, including the ability to incorporate a shift operation.
Single Instruction Multiple Data (SIMD) instructions
The add and subtract instructions treat each operand as two parallel 16-bit numbers, or four parallel 8-bit numbers. They can be treated as signed or unsigned. The operations can optionally be saturating, wrap around, or the results can be halved to avoid overflow. These instructions are available in ARMv6.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A1-7
Introduction to the ARM Architecture
Multiply instructions
There are several classes of multiply instructions, introduced at different times into the architecture. See Multiply instructions on page A3-10 for details.
Miscellaneous Data Processing instructions
These include Count Leading Zeros (CLZ) and Unsigned Sum of Absolute Differences with optional Accumulate (USAD8 and USADA8).
A1.2.3
Status register transfer instructions
The status register transfer instructions transfer the contents of the CPSR or an SPSR to or from a general-purpose register. Writing to the CPSR can: set the values of the condition code flags set the values of the interrupt enable bits set the processor mode and state alter the endianness of Load and Store operations.
A1.2.4
Load and store instructions
The following load and store instructions are available: Load and Store Register Load and Store Multiple registers on page A1-9 Load and Store Register Exclusive on page A1-9. There are also swap and swap byte instructions, but their use is deprecated in ARMv6. It is recommended that all software migrates to using the load and store register exclusive instructions.
Load and Store Register
Load Register instructions can load a 64-bit doubleword, a 32-bit word, a 16-bit halfword, or an 8-bit byte from memory into a register or registers. Byte and halfword loads can be automatically zero-extended or sign-extended as they are loaded. Store Register instructions can store a 64-bit doubleword, a 32-bit word, a 16-bit halfword, or an 8-bit byte from a register or registers to memory. From ARMv6, unaligned loads and stores of words and halfwords are supported, accessing the specified byte addresses. Prior to ARMv6, unaligned 32-bit loads rotated data, all 32-bit stores were aligned, and the other affected instructions UNPREDICTABLE.
A1-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to the ARM Architecture
Load and Store Register instructions have three primary addressing modes, all of which use a base register and an offset specified by the instruction: In offset addressing, the memory address is formed by adding or subtracting an offset to or from the base register value. In pre-indexed addressing, the memory address is formed in the same way as for offset addressing. As a side effect, the memory address is also written back to the base register. In post-indexed addressing, the memory address is the base register value. As a side effect, an offset is added to or subtracted from the base register value and the result is written back to the base register.
In each case, the offset can be either an immediate or the value of an index register. Register-based offsets can also be scaled with shift operations. As the PC is a general-purpose register, a 32-bit value can be loaded directly into the PC to perform a jump to any address in the 4GB memory space.
Load and Store Multiple registers
Load Multiple (LDM) and Store Multiple (STM) instructions perform a block transfer of any number of the general-purpose registers to or from memory. Four addressing modes are provided: pre-increment post-increment pre-decrement post-decrement. The base address is specified by a register value, which can be optionally updated after the transfer. As the subroutine return address and PC values are in general-purpose registers, very efficient subroutine entry and exit sequences can be constructed with LDM and STM: A single STM instruction at subroutine entry can push register contents and the return address onto the stack, updating the stack pointer in the process. A single LDM instruction at subroutine exit can restore register contents from the stack, load the PC with the return address, and update the stack pointer.
LDM and STM instructions also allow very efficient code for block copies and similar data movement
algorithms.
Load and Store Register Exclusive
These instructions support cooperative memory synchronization. They are designed to provide the atomic behavior required for semaphores without locking all system resources between the load and store phases. See LDREX on page A4-52 and STREX on page A4-202 for details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A1-9
Introduction to the ARM Architecture
A1.2.5
Coprocessor instructions
There are three types of coprocessor instructions: Data-processing instructions These start a coprocessor-specific internal operation. Data transfer instructions These transfer coprocessor data to or from memory. The address of the transfer is calculated by the ARM processor. Register transfer instructions These allow a coprocessor value to be transferred to or from an ARM register, or a pair of ARM registers.
A1.2.6
Exception-generating instructions
Two types of instruction are designed to cause specific exceptions to occur. Software interrupt instructions
SWI instructions cause a software interrupt exception to occur. These are normally used to
make calls to an operating system, to request an OS-defined service. The exception entry caused by a SWI instruction also changes to a privileged processor mode. This allows an unprivileged task to gain access to privileged functions, but only in ways permitted by the OS. Software breakpoint instructions
BKPT instructions cause an abort exception to occur. If suitable debugger software is installed on the abort vector, an abort exception generated in this fashion is treated as a breakpoint. If debug hardware is present in the system, it can instead treat a BKPT instruction directly as a breakpoint, preventing the abort exception from occurring.
In addition to the above, the following types of instruction cause an Undefined Instruction exception to occur: coprocessor instructions which are not recognized by any hardware coprocessor most instruction words that have not yet been allocated a meaning as an ARM instruction. In each case, this exception is normally used either to generate a suitable error or to initiate software emulation of the instruction.
A1-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to the ARM Architecture
A1.3
Thumb instruction set
The Thumb instruction set is a subset of the ARM instruction set, with each instruction encoded in 16 bits instead of 32 bits. For details see Chapter A6 The Thumb Instruction Set.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A1-11
Introduction to the ARM Architecture
A1-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Chapter A2 Programmers Model
This chapter introduces the ARM Programmers Model. It contains the following sections: Data types on page A2-2 Processor modes on page A2-3 Registers on page A2-4 General-purpose registers on page A2-6 Program status registers on page A2-11 Exceptions on page A2-16 Endian support on page A2-30 Unaligned access support on page A2-38 Synchronization primitives on page A2-44 The Jazelle Extension on page A2-53 Saturated integer arithmetic on page A2-69.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-1
Programmers Model
A2.1
Data types
ARM processors support the following data types: Byte Halfword Word 8 bits 16 bits 32 bits
Note
Support for halfwords was introduced in version 4. ARMv6 has introduced unaligned data support for words and halfwords. See Unaligned access support on page A2-38 for more information. When any of these types is described as unsigned, the N-bit data value represents a non-negative integer in the range 0 to +2N-1, using normal binary format. When any of these types is described as signed, the N-bit data value represents an integer in the range -2N-1 to +2N-1-1, using two's complement format. Most data operations, for example ADD, are performed on word quantities. Long multiplies support 64-bit results with or without accumulation. ARMv5TE introduced some halfword multiply operations. ARMv6 introduced a variety of Single Instruction Multiple Data (SIMD) instructions operating on two halfwords or four bytes in parallel. Load and store operations can transfer bytes, halfwords, or words to and from memory, automatically zero-extending or sign-extending bytes or halfwords as they are loaded. Load and store operations that transfer two or more words to and from memory are also provided. ARM instructions are exactly one word and are aligned on a four-byte boundary. Thumb instructions are exactly one halfword and are aligned on a two-byte boundary. Jazelle opcodes are a variable number of bytes in length and can appear at any byte alignment.
A2-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.2
Processor modes
The ARM architecture supports the seven processor modes shown in Table A2-1. Table A2-1 ARM processor modes Processor mode User FIQ IRQ Supervisor Abort Undefined System usr fiq irq svc abt und sys Mode number
0b10000 0b10001 0b10010 0b10011 0b10111 0b11011 0b11111
Description Normal program execution mode Supports a high-speed data transfer or channel process Used for general-purpose interrupt handling A protected mode for the operating system Implements virtual memory and/or memory protection Supports software emulation of hardware coprocessors Runs privileged operating system tasks (ARMv4 and above)
Mode changes can be made under software control, or can be caused by external interrupts or exception processing. Most application programs execute in User mode. When the processor is in User mode, the program being executed is unable to access some protected system resources or to change mode, other than by causing an exception to occur (see Exceptions on page A2-16). This allows a suitably-written operating system to control the use of system resources. The modes other than User mode are known as privileged modes. They have full access to system resources and can change mode freely. Five of them are known as exception modes: FIQ IRQ Supervisor Abort Undefined. These are entered when specific exceptions occur. Each of them has some additional registers to avoid corrupting User mode state when the exception occurs (see Registers on page A2-4 for details). The remaining mode is System mode, which is not entered by any exception and has exactly the same registers available as User mode. However, it is a privileged mode and is therefore not subject to the User mode restrictions. It is intended for use by operating system tasks that need access to system resources, but wish to avoid using the additional registers associated with the exception modes. Avoiding such use ensures that the task state is not corrupted by the occurrence of any exception.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-3
Programmers Model
A2.3
Registers
The ARM processor has a total of 37 registers: Thirty-one general-purpose registers, including a program counter. These registers are 32 bits wide and are described in General-purpose registers on page A2-6. Six status registers. These registers are also 32 bits wide, but only some of the 32 bits are allocated or need to be implemented. The subset depends on the architecture variant supported. These are described in Program status registers on page A2-11.
Registers are arranged in partially overlapping banks, with the current processor mode controlling which bank is available, as shown in Figure A2-1 on page A2-5. At any time, 15 general-purpose registers (R0 to R14), one or two status registers, and the program counter are visible. Each column of Figure A2-1 on page A2-5 shows which general-purpose and status registers are visible in the indicated processor mode.
A2-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Modes
Privileged modes Exception modes
User
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC
System
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC
Supervisor
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc PC
Abort
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt PC
Undefined
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und PC
Interrupt
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq PC
Fast interrupt
R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq PC
CPSR
CPSR
CPSR SPSR_svc
CPSR SPSR_abt
CPSR SPSR_und
CPSR SPSR_irq
CPSR SPSR_fiq
indicates that the normal register used by User or System mode has been replaced by an alternative register specific to the exception mode
Figure A2-1 Register organization
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-5
Programmers Model
A2.4
General-purpose registers
The general-purpose registers R0 to R15 can be split into three groups. These groups differ in the way they are banked and in their special-purpose uses: The unbanked registers, R0 to R7 The banked registers, R8 to R14 Register 15, the PC, is described in Register 15 and the program counter on page A2-9.
A2.4.1
The unbanked registers, R0 to R7
Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-bit physical register in all processor modes. They are completely general-purpose registers, with no special uses implied by the architecture, and can be used wherever an instruction allows a general-purpose register to be specified.
A2.4.2
The banked registers, R8 to R14
Registers R8 to R14 are banked registers. The physical register referred to by each of them depends on the current processor mode. Where a particular physical register is intended, without depending on the current processor mode, a more specific name (as described below) is used. Almost all instructions allow the banked registers to be used wherever a general-purpose register is allowed.
Note
There are a few exceptions to this rule for processors pre-ARMv6, and they are noted in the individual instruction descriptions. Where a restriction exists on the use of banked registers, it always applies to all of R8 to R14. For example, R8 to R12 are subject to such restrictions even in systems in which FIQ mode is never used and so only one physical version of the register is ever in use. Registers R8 to R12 have two banked physical registers each. One is used in all processor modes other than FIQ mode, and the other is used in FIQ mode. Where it is necessary to be specific about which version is being referred to, the first group of physical registers are referred to as R8_usr to R12_usr and the second group as R8_fiq to R12_fiq. Registers R8 to R12 do not have any dedicated special purposes in the architecture. However, for interrupts that are simple enough to be processed using registers R8 to R14 only, the existence of separate FIQ mode versions of these registers allows very fast interrupt processing. Registers R13 and R14 have six banked physical registers each. One is used in User and System modes, and each of the remaining five is used in one of the five exception modes. Where it is necessary to be specific about which version is being referred to, you use names of the form:
R13_<mode> R14_<mode>
where <mode> is the appropriate one of usr, svc (for Supervisor mode), abt, und, irq and fiq.
A2-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Register R13 is normally used as a stack pointer and is also known as the SP. The SRS instruction, introduced in ARMv6, is the only ARM instruction that uses R13 in a special-case manner. There are other such instructions in the Thumb instruction set, as described in Chapter A6 The Thumb Instruction Set. Each exception mode has its own banked version of R13. Suitable uses for these banked versions of R13 depend on the architecture version: In architecture versions earlier than ARMv6, each banked version of R13 will normally be initialized to point to a stack dedicated to that exception mode. On entry, the exception handler typically stores the values of other registers that it wants to use on this stack. By reloading these values into the register when it returns, the exception handler can ensure that it does not corrupt the state of the program that was being executed when the exception occurred. If fewer exception-handling stacks are desired in a system than this implies, it is possible instead to initialize the banked version of R13 for an exception mode to point to a small area of memory that is used for temporary storage while transferring to another exception mode and its stack. For example, suppose that there is a requirement for an IRQ handler to use the Supervisor mode stack to store SPSR_irq, R0 to R3, R12, R14_irq, and then to execute in Supervisor mode with IRQs enabled. This can be achieved by initializing R13_irq to point to a four-word temporary storage area, and using the following code sequence on entry to the handler:
STMIA MRS MOV MOV MOV MRS BIC ORR MSR STMFD STR LDMIA BIC MSR STMIB R13, (R0-R3) R0, SPSR R1, R12 R2, R13 R3, R14 R12, CPSR R12, R12, #0x1F R12, R12, #0x13 CPSR_c, R12 R13!, (R1,R3) R0, [R13,#-20]! R2, {R0-R3} R12, R12, #0x80 CPSR_c, R12 R13, {R0-R3} ; Put R0-R3 into temporary storage ; Move banked SPSR and R12-R14 into ; unbanked registers
; Use read/modify/write sequence ; on CPSR to switch to Supervisor ; mode ; ; ; ; ; ; ; Push original {R12, R14_irq}, then SPSR_irq with a gap for R0-R3 Reload R0-R3 from temporary storage Modify and write CPSR again to re-enable IRQs Store R0-R3 in the gap left on the stack for them
In ARMv6 and above, it is recommended that the OS designer should decide how many exception-handling stacks are required in the system, and select a suitable processor mode in which to handle the exceptions that use each stack. For example, one exception-handling stack might be required to be locked into real memory and be used for aborts and high-priority interrupts, while another could use virtual memory and be used for SWIs, Undefined instructions and low-priority interrupts. Suitable processor modes in this example might be Abort mode and Supervisor mode respectively. The banked version of R13 for each of the selected modes is then initialized to point to the corresponding stack, and the other banked versions of R13 are normally not used. Each exception handler starts with an SRS instruction to store the exception return information to the appropriate stack, followed (if necessary) by a CPS instruction to switch to the appropriate mode and possibly
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-7
Programmers Model
re-enable interrupts, after which other registers can be saved on that stack. So in the above example, an Undefined Instruction handler that wants to re-enable interrupts immediately would start with the following two instructions:
SRSFD CPSIE #svc_mode! i, #svc_mode
The handler can then operate entirely in Supervisor mode, using the virtual memory stack pointed to by R13_svc. Register R14 (also known as the Link Register or LR) has two special functions in the architecture: In each mode, the mode's own version of R14 is used to hold subroutine return addresses. When a subroutine call is performed by a BL or BLX instruction, R14 is set to the subroutine return address. The subroutine return is performed by copying R14 back to the program counter. This is typically done in one of the two following ways: Execute a BX LR instruction.
Note
An MOV PC,LR instruction will perform the same function as BX LR if the code to which it returns uses the current instruction set, but will not return correctly from an ARM subroutine called by Thumb code, or from a Thumb subroutine called by ARM code. The use of MOV PC,LR instructions for subroutine return is therefore deprecated.
On subroutine entry, store R14 to the stack with an instruction of the form:
STMFD SP!,{<registers>,LR}
and use a matching instruction to return:
LDMFD SP!,{<registers>,PC}
When an exception occurs, the appropriate exception mode's version of R14 is set to the exception return address (offset by a small constant for some exceptions). The exception return is performed in a similar way to a subroutine return, but using slightly different instructions to ensure full restoration of the state of the program that was being executed when the exception occurred. See Exceptions on page A2-16 for more details.
Register R14 can be treated as a general-purpose register at all other times.
Note
When nested exceptions are possible, the two special-purpose uses might conflict. For example, if an IRQ interrupt occurs when a program is being executed in User mode, none of the User mode registers are necessarily corrupted. But if an interrupt handler running in IRQ mode re-enables IRQ interrupts and a nested IRQ interrupt occurs, any value the outer interrupt handler is holding in R14_irq at the time is overwritten by the return address of the nested interrupt. System programmers need to be careful about such interactions. The usual way to deal with them is to ensure that the appropriate version of R14 does not hold anything significant at times when nested exceptions can occur. When this is hard to do in a straightforward way, it is usually best to change to another
A2-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
processor mode during entry to the exception handler, before re-enabling interrupts or otherwise allowing nested exceptions to occur. (In ARMv4 and above, System mode is often the best mode to use for this purpose.)
A2.4.3
Register 15 and the program counter
Register R15 (R15) is often used in place of the other general-purpose registers to produce various special-case effects. These are instruction-specific and so are described in the individual instruction descriptions. There are also many instruction-specific restrictions on the use of R15. these are also noted in the individual instruction descriptions. Usually, the instruction is UNPREDICTABLE if R15 is used in a manner that breaks these restrictions. If an instruction description neither describes a special-case effect when R15 is used nor places restrictions on its use, R15 is used to read or write the Program Counter (PC), as described in: Reading the program counter Writing the program counter on page A2-10.
Reading the program counter
When an instruction reads the PC, the value read depends on which instruction set it comes from: For an ARM instruction, the value read is the address of the instruction plus 8 bytes. Bits [1:0] of this value are always zero, because ARM instructions are always word-aligned. For a Thumb instruction, the value read is the address of the instruction plus 4 bytes. Bit [0] of this value is always zero, because Thumb instructions are always halfword-aligned.
This way of reading the PC is primarily used for quick, position-independent addressing of nearby instructions and data, including position-independent branching within a program. An exception to the above rule occurs when an ARM STR or STM instruction stores R15. Such instructions can store either the address of the instruction plus 8 bytes, like other instructions that read R15, or the address of the instruction plus 12 bytes. Whether the offset of 8 or the offset of 12 is used is IMPLEMENTATION DEFINED. An implementation must use the same offset for all ARM STR and STM instructions that store R15. It cannot use 8 for some of them and 12 for others. Because of this exception, it is usually best to avoid the use of STR and STM instructions that store R15. If this is difficult, use a suitable instruction sequence in the program to ascertain which offset the implementation uses. For example, if R0 points to an available word of memory, then the following instructions put the offset of the implementation in R0:
SUB STR LDR SUB R1, PC, R0, R0, PC, #4 [R0] [R0] R0, R1 ; ; ; ; R1 = address of following STR instruction Store address of STR instruction + offset, then reload it Calculate the offset as the difference
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-9
Programmers Model
Note
The rules about how R15 is read apply only to reads by instructions. In particular, they do not necessarily describe the values placed on a hardware address bus during instruction fetches. Like all other details of hardware interfaces, such values are IMPLEMENTATION DEFINED.
Writing the program counter
When an instruction writes the PC, the normal result is that the value written to the PC is treated as an instruction address and a branch occurs to that address. Since ARM instructions are required to be word-aligned, values they write to the PC are normally expected to have bits[1:0] == 0b00. Similarly, Thumb instructions are required to be halfword-aligned and so values they write to the PC are normally expected to have bit[0] == 0. The precise rules depend on the current instruction set state and the architecture version: In T variants of ARMv4 and above, including all variants of ARMv6 and above, bit[0] of a value written to R15 in Thumb state is ignored unless the instruction description says otherwise. If bit[0] of the PC is implemented (which depends on whether and how the Jazelle Extension is implemented), then zero must be written to it regardless of the value written to bit[0] of R15. In ARMv6 and above, bits[1:0] of a value written to R15 in ARM state are ignored unless the instruction description says otherwise. Bit[1] of the PC must be written as zero regardless of the value written to bit[1] of R15. If bit[0] of the PC is implemented (which depends on how the Jazelle Extension is implemented), then zero must be written to it. In all variants of ARMv4 and ARMv5, bits[1:0] of a value written to R15 in ARM state must be 0b00. If they are not, the results are UNPREDICTABLE.
Several instructions have their own rules for interpreting values written to R15. For example, BX and other instructions designed to transfer between ARM and Thumb states use bit[0] of the value to select whether to execute the code at the destination address in ARM state or Thumb state. Special rules of this type are described on the individual instruction pages, and override the general rules in this section.
A2-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.5
Program status registers
The Current Program Status Register (CPSR) is accessible in all processor modes. It contains condition code flags, interrupt disable bits, the current processor mode, and other status and control information. Each exception mode also has a Saved Program Status Register (SPSR), that is used to preserve the value of the CPSR when the associated exception occurs.
Note
User mode and System mode do not have an SPSR, because they are not exception modes. All instructions that read or write the SPSR are UNPREDICTABLE when executed in User mode or System mode. The format of the CPSR and the SPSRs is shown below.
31 30 29 28 27 26 25 24 23 20 19 16 15
RESERVED
10 9 8 7 6 5 4
0
N Z C V Q Res
J
RESERVED
GE[3:0]
EAI FT
M[4:0]
A2.5.1
Types of PSR bits
PSR bits fall into four categories, depending on the way in which they can be updated: Reserved bits Reserved for future expansion. Implementations must read these bits as 0 and ignore writes to them. For maximum compatibility with future extensions to the architecture, they must be written with values read from the same bits. Can be written from any mode. The N, Z, C, V, Q, GE[3:0], and E bits are user-writable. Can be written from any privileged mode. Writes to privileged bits in User mode are ignored. The A, I, F, and M[4:0] bits are privileged. Can be written from any privileged mode. Writes to execution state bits in User mode are ignored. The J and T bits are execution state bits, and are always zero in ARM state. Privileged MSR instructions that write to the CPSR execution state bits must write zeros to them, in order to avoid changing them. If ones are written to either or both of them, the resulting behavior is UNPREDICTABLE. This restriction applies only to the CPSR execution state bits, not the SPSR execution state bits.
User-writable bits Privileged bits Execution state bits
A2.5.2
The condition code flags
The N, Z, C, and V (Negative, Zero, Carry and oVerflow) bits are collectively known as the condition code flags, often referred to as flags. The condition code flags in the CPSR can be tested by most instructions to determine whether the instruction is to be executed.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-11
Programmers Model
The condition code flags are usually modified by: Execution of a comparison instruction (CMN, CMP, TEQ or TST). Execution of some other arithmetic, logical or move instruction, where the destination register of the instruction is not R15. Most of these instructions have both a flag-preserving and a flag-setting variant, with the latter being selected by adding an S qualifier to the instruction mnemonic. Some of these instructions only have a flag-preserving version. This is noted in the individual instruction descriptions.
In either case, the new condition code flags (after the instruction has been executed) usually mean: N Z C Is set to bit 31 of the result of the instruction. If this result is regarded as a two's complement signed integer, then N = 1 if the result is negative and N = 0 if it is positive or zero. Is set to 1 if the result of the instruction is zero (this often indicates an equal result from a comparison), and to 0 otherwise. Is set in one of four ways: V For an addition, including the comparison instruction CMN, C is set to 1 if the addition produced a carry (that is, an unsigned overflow), and to 0 otherwise. For a subtraction, including the comparison instruction CMP, C is set to 0 if the subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise. For non-addition/subtractions that incorporate a shift operation, C is set to the last bit shifted out of the value by the shifter. For other non-addition/subtractions, C is normally left unchanged (but see the individual instruction descriptions for any special cases).
Is set in one of two ways: For an addition or subtraction, V is set to 1 if signed overflow occurred, regarding the operands and result as two's complement signed integers. For non-addition/subtractions, V is normally left unchanged (but see the individual instruction descriptions for any special cases).
The flags can be modified in these additional ways: Execution of an MSR instruction, as part of its function of writing a new value to the CPSR or SPSR. Execution of MRC instructions with destination register R15. The purpose of such instructions is to transfer coprocessor-generated condition code flag values to the ARM processor. Execution of some variants of the LDM instruction. These variants copy the SPSR to the CPSR, and their main intended use is for returning from exceptions. Execution of an RFE instruction in a privileged mode that loads a new value into the CPSR from memory. Execution of flag-setting variants of arithmetic and logical instructions whose destination register is R15. These also copy the SPSR to the CPSR, and are intended for returning from exceptions.
A2-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.5.3
The Q flag
In E variants of ARMv5 and above, bit[27] of the CPSR is known as the Q flag and is used to indicate whether overflow and/or saturation has occurred in some DSP-oriented instructions. Similarly, bit[27] of each SPSR is a Q flag, and is used to preserve and restore the CPSR Q flag if an exception occurs. See Saturated integer arithmetic on page A2-69 for more information. In architecture versions prior to ARMv5, and in non-E variants of ARMv5, bit[27] of the CPSR and SPSRs must be treated as a reserved bit, as described in Types of PSR bits on page A2-11.
A2.5.4
The GE[3:0] bits
In ARMv6, the SIMD instructions use bits[19:16] as Greater than or Equal (GE) flags for individual bytes or halfwords of the result. You can use these flags to control a later SEL instruction, see SEL on page A4-127 for more details. Instructions that operate on halfwords: set or clear GE[3:2] together, based on the result of the top halfword calculation set or clear GE[1:0] together, based on the result of the bottom halfword calculation. Instructions that operate on bytes: set or clear GE[3] according to the result of the top byte calculation set or clear GE[2] according to the result of the second byte calculation set or clear GE[1] according to the result of the third byte calculation set or clear GE[0] according to the result of the bottom byte calculation. Each bit is set (otherwise cleared) if the results of the corresponding calculation are as follows: for unsigned byte addition, if the result is greater than or equal to 28 for unsigned halfword addition, if the result is greater than or equal to 216 for unsigned subtraction, if the result is greater than or equal to zero for signed arithmetic, if the result is greater than or equal to zero.
In architecture versions prior to ARMv6, bits[19:16] of the CPSR and SPSRs must be treated as a reserved bit, as described in Types of PSR bits on page A2-11.
A2.5.5
The E bit
From ARMv6, bit[9] controls load and store endianness for data handling. See Instructions to change CPSR E bit on page A2-36. This bit is ignored by instruction fetches. In architecture versions prior to ARMv6, bit[9] of the CPSR and SPSRs must be treated as a reserved bit, as described in Types of PSR bits on page A2-11.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-13
Programmers Model
A2.5.6
The interrupt disable bits
A, I, and F are the interrupt disable bits: A bit Disables imprecise data aborts when it is set. This is available only in ARMv6 and above. In earlier versions, bit[8] of CPSR and SPSRs must be treated as a reserved bit, as described in Types of PSR bits on page A2-11. Disables IRQ interrupts when it is set. Disables FIQ interrupts when it is set.
I bit F bit
A2.5.7
The mode bits
M[4:0] are the mode bits. These determine the mode in which the processor operates. Their interpretation is shown in Table A2-2. Table A2-2 The mode bits M[4:0] 0b10000 0b10001 0b10010 0b10011 0b10111 0b11011 0b11111 Mode User FIQ IRQ Supervisor Abort Undefined System Accessible registers PC, R14 to R0, CPSR PC, R14_fiq to R8_fiq, R7 to R0, CPSR, SPSR_fiq PC, R14_irq, R13_irq, R12 to R0, CPSR, SPSR_irq PC, R14_svc, R13_svc, R12 to R0, CPSR, SPSR_svc PC, R14_abt, R13_abt, R12 to R0, CPSR, SPSR_abt PC, R14_und, R13_und, R12 to R0, CPSR, SPSR_und PC, R14 to R0, CPSR (ARMv4 and above)
Not all combinations of the mode bits define a valid processor mode. Only those combinations explicitly described can be used. If any other value is programmed into the mode bits M[4:0], the result is
UNPREDICTABLE.
A2-14
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.5.8
The T and J bits
The T and J bits select the current instruction set, as shown in Table A2-3. Table A2-3 The T and J bits J 0 0 1 1 T 0 1 0 1 Instruction set ARM Thumb Jazelle
RESERVED
The T bit exists on t variants of ARMv4, and on all variants of ARMv5 and above. on non-T variants of ARMv4, the T bit must be treated as a reserved bit, as described in Types of PSR bits on page A2-11. The Thumb instruction set is implemented on T variants of ARMv4 and ARMv5, and on all variants of ARMv6 and above. instructions that switch between ARM and Thumb state execution can be used freely on implementation of these architectures. The Thumb instruction set is not implemented on non-T variants of ARMv5. If the Thumb instruction set is selected by setting T ==1 on these architecture variants, the next instruction executed will cause an Undefined Instruction exception (see Undefined Instruction exception on page A2-19). Instructions that switch between ARM and Thumb state execution can be used on implementation of these architecture variants, but only function correctly as long as the program remains in ARM state. If the program attempts to switch to Thumb state, the first instruction executed after that switch causes an Undefined Instruction exception. Entry into that exception then switches back to ARM state. The exception handler can detect that this was the cause of the exception from the fact that the T bit of SPSR_und is set. The J bit exists on ARMv5TEJ and on all variants of ARMv6 and above. On variants of ARMv4 and ARMv5, other than ARMv5TEJ, the J bit must be treated as a reserved bit, as described in Types of PSR bits on page A2-11. Hardware acceleration for Jazelle opcode execution can be implemented on ARMv5TEJ and on ARMv6 and above. On these architecture variants, the BXJ instruction is used to switch from ARM state into Jazelle state when the hardware accelerator is present and enabled. If the hardware accelerator is disabled, or not present, the BXJ instruction behaves as a BX instruction, and the J bit remains clear. For more details, see The Jazelle Extension on page A2-53.
A2.5.9
Other bits
Other bits in the program status registers are reserved for future expansion. In general, programmers must take care to write code in such a way that these bits are never modified. Failure to do this might result in code that has unexpected side effects on future versions of the architecture. See Types of PSR bits on page A2-11, and the usage notes for the MSR instruction on page A4-76 for more details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-15
Programmers Model
A2.6
Exceptions
Exceptions are generated by internal and external sources to cause the processor to handle an event, such as an externally generated interrupt or an attempt to execute an Undefined instruction. The processor state just before handling the exception is normally preserved so that the original program can be resumed when the exception routine has completed. More than one exception can arise at the same time. The ARM architecture supports seven types of exception. Table A2-4 lists the types of exception and the processor mode that is used to process each type. When an exception occurs, execution is forced from a fixed memory address corresponding to the type of exception. These fixed addresses are called the exception vectors.
Note
The normal vector at address 0x00000014 and the high vector at address 0xFFFF0014 are reserved for future expansion.
Table A2-4 Exception processing modes Exception type Reset Undefined instructions Software interrupt (SWI) Prefetch Abort (instruction fetch memory abort) Data Abort (data access memory abort) IRQ (interrupt) Mode Supervisor Undefined Supervisor Abort Abort IRQ 0 1 FIQ (fast interrupt) FIQ 0 1 VEa Normal address
0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000018
High vector address
0xFFFF0000 0xFFFF0004 0xFFFF0008 0xFFFF000C 0xFFFF0010 0xFFFF0018
IMPLEMENTATION DEFINED
0x0000001C 0xFFFF001C
IMPLEMENTATION DEFINED
a. VE = vectored interrupt enable (CP15 control); RAZ when not implemented.
A2-16
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
When an exception occurs, the banked versions of R14 and the SPSR for the exception mode are used to save state as follows:
R14_<exception_mode> = return link SPSR_<exception_mode> = CPSR CPSR[4:0] = exception mode number CPSR[5] = 0 /* if <exception_mode> == Reset or FIQ then CPSR[6] = 1 /* /* else CPSR[6] is unchanged */ CPSR[7] = 1 /* if <exception_mode> != UNDEF or SWI then CPSR[8] = 1 /* /* else CPSR[8] is unchanged */ CPSR[9] = CP15_reg1_EEbit /* PC = exception vector address
Execute in ARM state */ Disable fast interrupts */ Disable normal interrupts */ Disable imprecise aborts (v6 only) */ Endianness on exception entry */
To return after handling the exception, the SPSR is moved into the CPSR, and R14 is moved to the PC. This can be done atomically in two ways: using a data-processing instruction with the S bit set, and the PC as the destination using the Load Multiple with Restore CPSR instruction, as described in LDM (3) on page A4-40. In addition, in ARMv6, the RFE instruction (see RFE on page A4-113) can be used to load the CPSR and PC from memory, so atomically returning from an exception to a PC and CPSR that was previously saved in memory. Collectively these mechanisms define all of the mechanisms which perform a return from exception. The following sections show what happens automatically when the exception occurs, and also show the recommended data-processing instruction to use to return from each exception. This instruction is always a MOVS or SUBS instruction with the PC as its destination.
Note
When the recommended data-processing instruction is a SUBS and a Load Multiple with Restore CPSR instruction is used to return from the exception handler, the subtraction must still be performed. This is usually done at the start of the exception handler, before the return link is stored to memory. For example, an interrupt handler that wishes to store its return link on the stack might use instructions of the following form at its entry point:
SUB STMFD R14, R14, #4 SP!, {<other_registers>, R14}
and return using the instruction:
LDMFD SP!, {<other_registers>, PC}^
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-17
Programmers Model
A2.6.1
ARMv6 extensions to the exception model
In ARMv6 and above, the exception model is extended as follows: An imprecise data abort mechanism that allows some types of data abort to be treated asynchronously. The resulting exceptions behave like interrupts, except that they use Abort mode and its banked registers. This mechanism includes a mask bit (the A bit) in the PSRs, in order to ensure that imprecise data aborts do not occur while another abort is being handled. The mechanism is described in Imprecise data aborts on page A2-23. Support for vectored interrupts controlled by the VE bit in the system control coprocessor (see Vectored interrupt support on page A2-26). It is IMPLEMENTATION DEFINED whether support for this mechanism is included in earlier versions of the architecture. Support for a low interrupt latency configuration controlled by the FI bit in the system control coprocessor (see Low interrupt latency configuration on page A2-27). It is IMPLEMENTATION DEFINED whether support for this mechanism is included in earlier versions of the architecture. Three new instructions (CPS, SRS, RFE) to improve nested stack handling of different exceptions in a common mode. CPS can also be used to efficiently enable or disable the interrupt and imprecise abort masks, either within a mode, or while transitioning from a privileged mode to any other mode. See New instructions to improve exception handling on page A2-28 for a brief description.
A2.6.2
Reset
When the Reset input is asserted on the processor, the ARM processor immediately stops execution of the current instruction. When Reset is de-asserted, the following actions are performed:
R14_svc = UNPREDICTABLE value SPSR_svc = UNPREDICTABLE value CPSR[4:0] = 0b10011 CPSR[5] =0 CPSR[6] =1 CPSR[7] =1 CPSR[8] =1 CPSR[9] = CP15_reg1_EEbit if high vectors configured then PC = 0xFFFF0000 else PC = 0x00000000
/* /* /* /* /* /*
Enter Supervisor mode */ Execute in ARM state */ Disable fast interrupts */ Disable normal interrupts */ Disable Imprecise Aborts (v6 only) */ Endianness on exception entry */
After Reset, the ARM processor begins execution at address 0x00000000 or 0xFFFF0000 in Supervisor mode with interrupts disabled.
Note
There is no architecturally defined way of returning from a Reset.
A2-18
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.6.3
Undefined Instruction exception
If the ARM processor executes a coprocessor instruction, it waits for any external coprocessor to acknowledge that it can execute the instruction. If no coprocessor responds, an Undefined Instruction exception occurs. If an attempt is made to execute an instruction that is UNDEFINED, an Undefined Instruction exception occurs (see Extending the instruction set on page A3-32). The Undefined Instruction exception can be used for software emulation of a coprocessor in a system that does not have the physical coprocessor (hardware), or for general-purpose instruction set extension by software emulation. When an Undefined Instruction exception occurs, the following actions are performed:
R14_und SPSR_und CPSR[4:0] CPSR[5] address of next instruction after the Undefined instruction CPSR 0b11011 /* Enter Undefined Instruction mode */ 0 /* Execute in ARM state */ /* CPSR[6] is unchanged */ CPSR[7] =1 /* Disable normal interrupts */ /* CPSR[8] is unchanged */ CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */ if high vectors configured then PC = 0xFFFF0004 else PC = 0x00000004 = = = =
To return after emulating the Undefined instruction use:
MOVS PC,R14
This restores the PC (from R14_und) and CPSR (from SPSR_und) and returns to the instruction following the Undefined instruction. In some coprocessor designs, an internal exceptional condition caused by one coprocessor instruction is signaled imprecisely by refusing to respond to a later coprocessor instruction. In these circumstances, the Undefined Instruction handler takes whatever action is necessary to clear the exceptional condition, then returns to the second coprocessor instruction. To do this use:
SUBS PC,R14,#4
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-19
Programmers Model
A2.6.4
Software Interrupt exception
The Software Interrupt instruction (SWI) enters Supervisor mode to request a particular supervisor (operating system) function. When a SWI is executed, the following actions are performed:
R14_svc SPSR_svc CPSR[4:0] CPSR[5] address of next instruction after the SWI instruction CPSR 0b10011 /* Enter Supervisor mode */ 0 /* Execute in ARM state */ /* CPSR[6] is unchanged */ CPSR[7] =1 /* Disable normal interrupts */ /* CPSR[8] is unchanged */ CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */ if high vectors configured then PC = 0xFFFF0008 else PC = 0x00000008 = = = =
To return after performing the SWI operation, use the following instruction to restore the PC (from R14_svc) and CPSR (from SPSR_svc) and return to the instruction following the SWI:
MOVS PC,R14
A2.6.5
Prefetch Abort (instruction fetch memory abort)
A memory abort is signaled by the memory system. Activating an abort in response to an instruction fetch marks the fetched instruction as invalid. A Prefetch Abort exception is generated if the processor tries to execute the invalid instruction. If the instruction is not executed (for example, as a result of a branch being taken while it is in the pipeline), no Prefetch Abort occurs. In ARMv5 and above, a Prefetch Abort exception can also be generated as the result of executing a BKPT instruction. For details, see BKPT on page A4-14 (ARM instruction) and BKPT on page A7-24 (Thumb instruction). When an attempt is made to execute an aborted instruction, the following actions are performed:
R14_abt SPSR_abt CPSR[4:0] CPSR[5] CPSR[7] CPSR[8] CPSR[9] if high PC else PC address of the aborted instruction + 4 CPSR 0b10111 /* Enter Abort mode */ 0 /* Execute in ARM state */ /* CPSR[6] is unchanged */ =1 /* Disable normal interrupts */ =1 /* Disable Imprecise Data Aborts (v6 only) */ = CP15_reg1_EEbit /* Endianness on exception entry */ vectors configured then = 0xFFFF000C = 0x0000000C = = = =
A2-20
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
To return after fixing the reason for the abort, use:
SUBS PC,R14,#4
This restores both the PC (from R14_abt) and CPSR (from SPSR_abt), and returns to the aborted instruction.
A2.6.6
Data Abort (data access memory abort)
A memory abort is signaled by the memory system. Activating an abort in response to a data access (load or store) marks the data as invalid. A Data Abort exception occurs before any following instructions or exceptions have altered the state of the CPU. The following actions are performed:
R14_abt SPSR_abt CPSR[4:0] CPSR[5] CPSR[7] CPSR[8] CPSR[9] if high PC else PC address of the aborted instruction + 8 CPSR 0b10111 /* Enter Abort mode */ 0 /* Execute in ARM state */ /* CPSR[6] is unchanged */ =1 /* Disable normal interrupts */ =1 /* Disable Imprecise Data Aborts (v6 only) */ = CP15_reg1_EEbit /* Endianness on exception entry */ vectors configured then = 0xFFFF0010 = 0x00000010 = = = =
To return after fixing the reason for the abort use:
SUBS PC,R14,#8
This restores both the PC (from R14_abt) and CPSR (from SPSR_abt), and returns to re-execute the aborted instruction. If the aborted instruction does not need to be re-executed use:
SUBS PC,R14,#4
Effects of data-aborted instructions
Instructions that access data memory can modify memory by storing one or more values. If a Data Abort occurs in such an instruction, the value of each memory location that the instruction stores to is: unchanged if the memory system does not permit write access to the memory location UNPREDICTABLE otherwise.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-21
Programmers Model
Instructions that access data memory can modify registers in the following ways: By loading values into one or more of the general-purpose registers, that can include the PC. By specifying base register write-back, in which the base register used in the address calculation has a modified value written to it. All instructions that allow this to be specified have UNPREDICTABLE results if base register write-back is specified and the base register is the PC, so only general-purpose registers other than the PC can legitimately be modified in this way. By loading values into coprocessor registers. By modifying the CPSR.
If a Data Abort occurs, the values left in these registers are determined by the following rules: 1. The PC value on entry to the Data Abort handler is 0x00000010 or 0xFFFF0010, and the R14_abt value is determined from the address of the aborted instruction. Neither is affected in any way by the results of any PC load specified by the instruction. If base register write-back is not specified, the base register value is unchanged. This applies even if the instruction loaded its own base register and the memory access to load the base register occurred earlier than the aborting access. For example, suppose the instruction is:
LDMIA R0,{R0,R1,R2}
2.
and the implementation loads the new R0 value, then the new R1 value and finally the new R2 value. If a Data Abort occurs on any of the accesses, the value in the base register R0 of the instruction is unchanged. This applies even if it was the load of R1 or R2 that aborted, rather than the load of R0. 3. 4. 5. 6. If base register write-back is specified, the value left in the base register is determined by the abort model of the implementation, as described in Abort models on page A2-23. If the instruction only loads one general-purpose register, the value in that register is unchanged. If the instruction loads more than one general-purpose register, UNPREDICTABLE values are left in destination registers that are neither the PC nor the base register of the instruction. If the instruction loads coprocessor registers, UNPREDICTABLE values are left in the destination coprocessor registers, unless otherwise specified in the instruction set description of the specific coprocessor. CPSR bits not defined as updated on exception entry maintain their current value.
7.
A2-22
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Abort models
The abort model used by an ARM implementation is IMPLEMENTATION DEFINED, and is one of the following: Base Restored Abort Model If a precise Data Abort occurs in an instruction that specifies base register write-back, the value in the base register is unchanged. This is the only abort model permitted in ARMv6 and above. Base Updated Abort Model If a precise Data Abort occurs in an instruction that specifies base register write-back, the base register write-back still occurs. This model is prohibited in ARMv6 and above. In either case, the abort model applies uniformly across all instructions. An implementation does not use the Base Restored Abort Model for some instructions and the Base Updated Abort Model for others.
A2.6.7
Imprecise data aborts
An imprecise data abort, caused, for example, by an external error on a write that has been held in a Write Buffer, is asynchronous to the execution of the causing instruction and might in reality occur many cycles after the instruction that caused the memory access has retired. For this reason, the imprecise data abort might occur at a time that the processor is in abort mode because of a precise abort, or might have live state in abort mode, but be handling an interrupt. To avoid the loss of the Abort mode state (R14 and SPSR_abt) in these cases, that would lead to the processor entering an unrecoverable state, the existence of a pending imprecise data abort must be held by the system until such time as the abort mode can safely be entered. From ARMv6, a mask is added into the CPSR (CPSR[8]) to control when an imprecise abort cannot be accepted. This bit is referred to as the A bit. The imprecise data abort causes a Data Abort to be taken when imprecise data aborts are not masked. When imprecise data aborts are masked, the implementation is responsible for holding the presence of a pending imprecise abort until the mask is cleared and the abort is taken. It is IMPLEMENTATION DEFINED whether more than one imprecise abort can be pended. The A bit is set automatically on taking a Prefetch Abort, a Data Abort, an IRQ or FIQ interrupt, and on reset. The A bit can only be changed from a privileged mode.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-23
Programmers Model
A2.6.8
Interrupt request (IRQ) exception
The IRQ exception is generated externally by asserting the IRQ input on the processor. It has a lower priority than FIQ (see Table A2-1 on page A2-25), and is masked out when an FIQ sequence is entered. Interrupts are disabled when the I bit in the CPSR is set. If the I bit is clear, ARM checks for an IRQ at instruction boundaries.
Note
The I bit can only be changed from a privileged mode. When an IRQ is detected, the following actions are performed:
address of next instruction to be executed + 4 CPSR 0b10010 /* Enter IRQ mode */ 0 /* Execute in ARM state */ /* CPSR[6] is unchanged */ CPSR[7] =1 /* Disable normal interrupts */ CPSR[8] =1 /* Disable Imprecise Data Aborts (v6 only) */ CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */ if VE==0 then if high vectors configured then PC = 0xFFFF0018 else PC = 0x00000018 else PC = IMPLEMENTATION DEFINED /* see page A2-26 */ R14_irq SPSR_irq CPSR[4:0] CPSR[5] = = = =
To return after servicing the interrupt, use:
SUBS PC,R14,#4
This restores both the PC (from R14_irq) and CPSR (from SPSR_irq), and resumes execution of the interrupted code.
A2.6.9
Fast interrupt request (FIQ) exception
The FIQ exception is generated externally by asserting the FIQ input on the processor. FIQ is designed to support a data transfer or channel process, and has sufficient private registers to remove the need for register saving in such applications, therefore minimizing the overhead of context switching. Fast interrupts are disabled when the F bit in the CPSR is set. If the F bit is clear, ARM checks for an FIQ at instruction boundaries.
Note
The F bit can only be changed from a privileged mode. When an FIQ is detected, the following actions are performed:
A2-24
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
R14_fiq = address of next instruction to be executed + 4 SPSR_fiq = CPSR CPSR[4:0] = 0b10001 /* Enter FIQ mode */ CPSR[5] =0 /* Execute in ARM state */ CPSR[6] =1 /* Disable fast interrupts */ CPSR[7] =1 /* Disable normal interrupts */ CPSR[8] =1 /* Disable Imprecise Data Aborts (v6 only) */ CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */ if VE==0 then if high vectors configured then PC = 0xFFFF001C else PC = 0x0000001C else PC = IMPLEMENTATION DEFINED /* see page A2-26 */
To return after servicing the interrupt, use:
SUBS PC, R14,#4
This restores both the PC (from R14_fiq) and CPSR (from SPSR_fiq), and resumes execution of the interrupted code. The FIQ vector is deliberately the last vector to allow the FIQ exception-handler software to be placed directly at address 0x0000001C or 0xFFFF001C, without requiring a branch instruction from the vector.
A2.6.10 Exception priorities
Table A2-1 shows the exception priorities: Table A2-1 Exception priorities Priority Highest 1 2 3 4 5 6 Lowest 7 Exception Reset Data Abort (including data TLB miss) FIQ IRQ Imprecise Abort (external abort) - ARMv6 Prefetch Abort (including prefetch TLB miss) Undefined instruction SWI
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-25
Programmers Model
Undefined instruction and software interrupt cannot occur at the same time, because they each correspond to particular (non-overlapping) decodings of the current instruction. Both must be lower priority than Prefetch Abort, because a Prefetch Abort indicates that no valid instruction was fetched. The priority of a Data Abort exception is higher than FIQ, which ensures that the Data Abort handler is entered before the FIQ handler is entered (so that the Data Abort is resolved after the FIQ handler has completed).
A2.6.11 High vectors
High vectors were introduced into some implementations of ARMv4 and are required in ARMv6 implementations. High vectors allow the exception vector locations to be moved from their normal address range 0x00000000-0x0000001C at the bottom of the 32-bit address space, to an alternative address range 0xFFFF0000-0xFFFF001C near the top of the address space. These alternative locations are known as the high vectors. Prior to ARMv6, it is IMPLEMENTATION DEFINED whether the high vectors are supported. When they are, a hardware configuration input selects whether the normal vectors or the high vectors are to be used from reset. The ARM instruction set does not contain any instructions that can directly change whether normal or high vectors are configured. However, if the standard System Control coprocessor is attached to an ARM processor that supports the high vectors, bit[13] of coprocessor 15 register 1 can be used to switch between using the normal vectors and the high vectors (see Register 1: Control registers on page B3-12).
A2.6.12 Vectored interrupt support
Historically, the IRQ and FIQ exception vectors are affected by whether high vectors are enabled, and are otherwise fixed. The result is that interrupt handlers typically have to start with an instruction sequence to determine the cause of the interrupt and branch to a routine to handle it. Support of vectored interrupts allows an interrupt controller to prioritize interrupts, and provide the required interrupt handler address directly to the core. The vectored interrupt behavior is explicitly enabled by the setting of a bit, the VE bit, in the system coprocessor CP15 register 1. See Register 1: Control registers on page B3-12. For backwards compatibility, the vectored interrupt mechanism is disabled on reset. The details of the hardware to support vectored interrupts is IMPLEMENTATION DEFINED. A vectored interrupt controller (VIC) can reduce effective interrupt latency considerably, by eliminating the need for an interrupt handler to identify the source of an interrupt and acknowledge it before re-enabling the interrupts. Furthermore, if the VIC and core implement an appropriate handshake as the interrupt handler routine is entered, the VIC can automatically mask out the interrupt source associated with that handler and any lower priority sources. This allows the interrupts concerned to be re-enabled by the processor core as soon as their return information (that is, R14 and SPSR values) have been saved, reducing the period during which higher priority interrupts are disabled.
A2-26
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.6.13 Low interrupt latency configuration
The FI bit (bit[21]) in the system control register (CP15 register 1) enables the interrupt latency configuration logic in an implementation. See Register 1: Control registers on page B3-12. The purpose of this configuration is to reduce the interrupt latency of the processor. The exact mechanisms that are used to perform this are IMPLEMENTATION DEFINED. In order to ensure that a change between normal and low interrupt latency configurations is synchronized correctly, the FI bit must only be changed in IMPLEMENTATION DEFINED circumstances. It is recommended that software systems should only change the FI bit shortly after reset, while interrupts are disabled. When interrupt latency is reduced, this may result in reduced performance overall. Examples of the mechanisms which may be used are disabling Hit-Under-Miss functionality within a core, and the abandoning of restartable external accesses, allowing the core to react to a pending interrupt faster than would otherwise be the case. Low interrupt latency configuration may have IMPLEMENTATION DEFINED effects in the memory system or elsewhere outside the processor core. It is legal for the interrupt to be seen as being taken before a store to a restartable memory location, but for the memory to have been updated when in low interrupt latency configuration. In low interrupt latency configuration, software must only use multi-word load/store instructions in ways that are fully restartable. This allows (but does not require) implementations to make multi-word instructions interruptible when in low interrupt latency configuration. The multi-access instructions to which this rule currently applies are: ARM Thumb
LDC, all forms of LDM, LDRD, STC, all forms of STM, STRD LDMIA, PUSH, POP, STMIA
Note
If the instruction is interrupted before it is complete, the result may be that one or more of the words are accessed twice. Idempotent memory (multiple reads or writes of the same information exhibit identical system results) is a requirement of system correctness. In ARMv6, memory with the normal attribute is guaranteed to behave this way, however, memory marked as Device or Strongly Ordered is not (for example, a FIFO). It is IMPLEMENTATION DEFINED whether multi-word accesses are supported for Device and Strongly Ordered memory types in the low interrupt latency configuration. A similar situation exists with regard to multi-word load/store instructions that access memory locations that can abort in a recoverable way, since an abort on one of the words accessed may cause a previously-accessed word to be accessed twice once before the abort, and a second time after the abort handler has returned. The requirement in this case is either that all side-effects are idempotent, or that the abort must either occur on the first word accessed or not at all.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-27
Programmers Model
A2.6.14 New instructions to improve exception handling
ARMv6 adds an instruction to simplify changes of processor mode and the disabling and enabling of interrupts. New instructions are also added to reduce the processing cost of handling exceptions in a different mode to the exception entry mode, by removing any need to use the original modes stack. Two examples are: IRQ routines may wish to execute in System or Supervisor mode, so that they can both re-enable IRQs and use BL instructions. This is not possible in IRQ mode, because a nested IRQ could corrupt the BLs return link at any time. Using the new instructions, the system can store the return state (R14 link register and SPSR_irq) to the System/User or Supervisor mode stack, switch to System or Supervisor mode and re-enable IRQs efficiently, without making any use of R13_irq or the IRQ stack. FIQ mode is designed for efficient use by a single owner, using R8_fiq R13_fiq as global variables. In addition, unlike IRQs, FIQs are not disabled by other exceptions (apart from reset), making them the preferred type for real time interrupts, when other exceptions are being used routinely, such as virtual memory or instruction emulation. IRQs may be disabled for unacceptably long periods of time while these needs are being serviced. However, if more than one real-time interrupt source is required, there is a conflict of interest. The new mechanism allows multiple FIQ sources and minimizes the period with FIQs disabled, greatly reducing the interrupt latency penalty. The FIQ mode registers can be allocated to the highest priority FIQ as a single owner.
SRS Store Return State
This instruction stores R14_<current_mode> and SPSR_<current_mode> to sequential addresses, using the banked version of R13 for a specified mode to supply the base address (and to be written back to if base register writeback is specified). This allows an exception handler to store its return state on a stack other than the one automatically selected by its exception entry sequence. The addressing mode used is a version of ARM addressing mode 4 (see Addressing Mode 4 - Load and Store Multiple on page A5-41), modified so as to assume a {R14,SPSR} register list rather than using a list specified by a bit mask in the instruction. This allows the SRS instruction to access stacks in a manner compatible with the normal use of STM instructions for stack accesses. See SRS on page A4-174 for the instruction details.
RFE Return From Exception
This instruction loads the PC and CPSR from sequential addresses. This is used to return from an exception which has had its return state saved using the SRS instruction, and again uses a version of ARM addressing mode 4, modified this time to assume a {PC,CPSR} register list. See RFE on page A4-113 for the instruction details.
A2-28
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
CPS Change Processor State
This instruction provides new values for the CPSR interrupt masks, mode bits, or both, and is designed to shorten and speed up the read/modify/write instruction sequence used in earlier architecture variants to perform such tasks. Together with the SRS instruction, it allows an exception handler to save its return information on the stack of another mode and then switch to that other mode, without modifying the stack belonging to the original mode or any registers other than the stack pointer of the new mode. The instruction also streamlines interrupt mask handling and mode switches in other code, and in particular allows short, efficient, atomic code sequences in a uniprocessor system by disabling interrupts at their start and re-enabling interrupts at their end. See CPS on page A4-29 for the instruction details. A CPS Thumb instruction that allows mask updates within the current mode is also provided, see section CPS on page A7-39.
Note
The Thumb instruction cannot change the mode due to instruction space usage constraints.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-29
Programmers Model
A2.7
Endian support
This section discusses memory and memory-mapped I/O, with regard to the assumptions ARM processor implementations make about endianness. ARMv6 introduces several architectural extensions to support mixed-endian access in hardware: Byte reverse instructions that operate on general-purpose register contents to support word, and signed and unsigned halfword data quantities. Separate instruction and data endianness, with instructions fixed as little-endian format, naturally aligned, but with legacy support for 32-bit word-invariant binary images/ROM. A PSR Endian control flag, the E bit, which dictates the byte order used for the entire load and store instruction space when data is loaded into, and stored back out of the register file. In previous architectures this PSR bit was specified as 0 and is never set in legacy code written to conform to architectures prior to ARMv6. ARM and Thumb instructions to set and clear the E bit explicitly. A byte-invariant addressing scheme to support fine-grain big-endian and little-endian shared data structures, to conform to the IEEE Standard for Shared-Data Formats Optimized for Scalable Coherent Interface (SCI) Processors, IEEE Std 1596.5-1993 (ISBN 1-55937-354-7, IEEE). Bus interface endianness is IMPLEMENTATION DEFINED. However, it must support byte lane controls for unaligned word and halfword data access.
A2.7.1
Address space
The ARM architecture uses a single, flat address space of 232 8-bit bytes. Byte addresses are treated as unsigned numbers, running from 0 to 232 - 1. This address space is regarded as consisting of 230 32-bit words, each of whose addresses is word-aligned, which means that the address is divisible by 4. The word whose word-aligned address is A consists of the four bytes with addresses A, A+1, A+2 and A+3. In ARMv4 and above, the address space is also regarded as consisting of 231 16-bit halfwords, each of whose addresses is halfword-aligned (divisible by 2). The halfword whose halfword-aligned address is A consists of the two bytes with addresses A and A+1. In ARMv5E and above, the address space supports 64-bit doubleword operations. Doubleword operations can be considered as two-word load/store operations, each word addressed as follows: A, A+1, A+2, and A+3 for the first word A+4, A+5, A+6, and A+7 for the second word. Prior to ARMv6, word-aligned doubleword operations are UNPREDICTABLE with doubleword-aligned addresses always supported. ARMv6 mandates support of both modulo4 and modulo8 alignment of doublewords, and introduces support for unaligned word and halfword data accesses, all controlled through the standard System Control coprocessor.
A2-30
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Jazelle state (see The T and J bits on page A2-15) introduced with ARM architecture variant v5J supports byte addressing. Address calculations are normally performed using ordinary integer instructions. This means that they normally wrap around if they overflow or underflow the address space. This means that the result of the calculation is reduced modulo 232. Normal sequential execution of instructions effectively calculates:
(address_of_current_instruction) + 4
after each instruction to determine which instruction to execute next. If this calculation overflows the top of the address space, the result is UNPREDICTABLE. In other words, programs should not rely on sequential execution of the instruction at address 0x00000000 after the instruction at address 0xFFFFFFFC. The above only applies to instructions that are executed, including those which fail their condition code check. Most ARM implementations prefetch instructions ahead of the currently-executing instruction. If this prefetching overflows the top of the address space, it does not cause the implementation's behavior to become UNPREDICTABLE until and unless the prefetched instructions are actually executed.
LDC, LDM, LDRD, POP, PUSH, STC, STRD, and STM instructions access a sequence of words at increasing memory addresses, effectively incrementing a memory address by 4 for each load or store. If this calculation overflows the top of the address space, the result is UNPREDICTABLE. In other words, programs should not use these instructions in such a way that they access the word at address 0x00000000 sequentially after the word at address 0xFFFFFFFC.
Any unaligned load or store whose calculated address is such that it would access the byte at 0xFFFFFFFF and the byte at address 0x00000000 as part of the instruction is UNPREDICTABLE.
A2.7.2
Endianness - an overview
The rules in Address space on page A2-30 require that for a word-aligned address A: the word at address A consists of the bytes at addresses A, A+1, A+2 and A+3 the halfword at address A consists of the bytes at addresses A and A+1 the halfword at address A+2 consists of the bytes at addresses A+2 and A+3. the word at address A therefore consists of the halfwords at addresses A and A+2. However, this does not totally specify the mappings between words, halfwords, and bytes. A memory system uses one of the two following mapping schemes. This choice is known as the endianness of the memory system. In a little-endian memory system: a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address a byte at a halfword-aligned address is the least significant byte within the halfword at that address.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-31
Programmers Model
In a big-endian memory system: a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at that address a byte at a halfword-aligned address is the most significant byte within the halfword at that address.
For a word-aligned address A, Table A2-2 and Table A2-3 show how the word at address A, the halfwords at addresses A and A+2, and the bytes at addresses A, A+1, A+2 and A+3 map on to each other for each endianness. Table A2-2 Big-endian memory system
31 24 23 16 15 87 0
Word at Address A Halfword at Address A Byte at Address A Byte at Address A+1 Halfword at Address A+2 Byte at Address A+2 Byte at Address A+3
Table A2-3 Little-endian memory system
31 24 23 16 15 87 0
Word at Address A Halfword at Address A+2 Byte at Address A+3 Byte at Address A+2 Halfword at Address A Byte at Address A+1 Byte at Address A
On memory systems wider than 32 bits, the ARM architecture has traditionally supported a word-invariant memory model, meaning that a word aligned address will fetch the same data in both big endian and little endian systems. This is illustrated for a 64-bit data path in Table A2-4 and Table A2-5 on page A2-33. Table A2-4 Big-endian word invariant case
63 32 31 0
Word at Address A+4 Halfword at Address A+4 Halfword at Address A+6
Word at Address A Halfword at Address A Halfword at Address A+2
A2-32
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Table A2-5 Little-endian word invariant case
63 32 31 0
Word at Address A+4 Halfword at Address A+6 Halfword at Address A+4
Word at Address A Halfword at Address A+2 Halfword at Address A
New provisions in ARMv6
ARMv6 has introduced new configurations known as mixed endian support. These use a byte-invariant address model, affecting the order that bytes are transferred to and from ARM registers. Byte invariance means that the address of a byte in memory is the same irrespective of whether that byte is being accessed in a big endian or little endian manner. Byte, halfword, and word accesses access the same one, two or four bytes in memory for both big and little endian configuration. Double word and multiple word accesses in the ARM architecture are treated as a series of word accesses from incrementing word addresses, and hence each word also returns the same bytes of information in these cases too.
Note
When an implementation is configured in mixed endian mode, this only affects data accesses and how they are loaded/stored to/from the register file. Instruction fetches always assume a little endian byte order model. When configured for big endian load/store, the lowest address provides the most significant byte of the requested word or halfword. For LDRD/STRD this is the most significant byte of the first word accessed. When configured for little endian load/store, the lowest address provides the least significant byte of the requested word or halfword. For LDRD/STRD this is the least significant byte of the first word accessed.
The convention adopted in this book is to identify the different endian models as follows: the word invariant big endian model is known as BE-32 the byte invariant big endian model is referred to as BE-8 little endian data is identical in both models and referred to as LE.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-33
Programmers Model
A2.7.3
Endian configuration and control
Prior to ARMv6, a single bit (B bit) provides endian control. It is IMPLEMENTATION DEFINED whether implementations of ARMv5 and below support little-endian memory systems, big-endian memory systems, or both. If a standard System Control coprocessor is attached to an ARM implementation supporting the B bit, this configuration input can be changed by writing to bit[7] of register 1 of the System Control coprocessor (see Register 1: Control registers on page B3-12). An implementation may preset the B bit on reset. If an ARM processor configures for little-endian operation on reset, and it is attached to a big-endian memory system, one of the first things the reset handler must do is switch the configured endianness to big-endian, using an instruction sequence like:
MRC ORR MCR p15, 0, r0, c1, c0 r0, r0, #0x80 p15, 0, r0, c1, c0 ; r0 := CP15 register 1 ; Set bit[7] in r0 ; CP15 register 1 := r0
This must be done before there is any possibility of a byte or halfword data access occurring, or instruction execution in Thumb or Jazelle state. ARMv6 supports big-endian, little-endian, and byte-invariant hybrid systems. LE and BE-8 formats must be supported. Support of BE-32 is IMPLEMENTATION DEFINED. Features are provided in the System Control coprocessor and CPSR/SPSR to support hybrid operation. The System Control Coprocessor register (CP15 register 1) and CPSR bits used are: Bit[1] - A bit - used to enable alignment checking. Always reset to zero (alignment checking OFF). Bit[7] - B bit - OPTIONAL, retained for backwards compatibility Bit[22] - the U bit - enables ARMv6 unaligned data support, and used with Bit[1] - the A bit - to determine alignment checking behavior. Bit [25] - the EE bit - Exception Endian bit. CPSR/SPSR[9] - the E bit - load/store endian control.
The behavior of the memory system with respect to the U and A bits is summarized in Table A2-6. Table A2-6 U 0 0 1 1 A 0 1 0 1 Description Legacy (32-bit word invariant only) Modulo 8 alignment checking: LDRD/STRD (8 and 32-bit invariant memory models) Unaligned access support (8-bit byte invariant data accesses only) Modulo 4 alignment checking: LDRD/STRD (8-bit and 32-bit invariant memory models)
A2-34
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
The EE-bit value is used to overwrite the CPSR_E bit on exception entry and for page table lookups. These are asynchronous events with respect to normal control of the CPSR E bit. A 2-bit configuration (CFGEND[1:0]) replaces the BigEndinit configuration pin to provide hardware system configuration on reset. CFGEND[1] maps to the U bit, while CFGEND[0] sets either the B bit or EE bit and CPSR_E on reset. Table A2-7 defines the CFGEND[1:0] encoding and associated configurations. Table A2-7 CFGEND[1:0] Coprocessor 15 System Control Register (register 1) EE bit[25] 00 01a 10 11 0 0 0 1 U bit[22] 0 0 1 1 A bit[1] 0 0 0 0 B bit[7] 0 1 0 0 CPSR/SPSR E bit 0 0 0 1
a. This configuration is RESERVED in implementations which do not support BE-32. In this case, the B bit must read as zero (RAZ).
Where an implementation does not include configuration pins, the U bit and A bit shall clear on reset. The usage model for the U bit and A bit with respect to the B bit and E bit is summarized in Table A2-8. Where BE-32 is not supported, the B bit must read as zero, and all entries indicated by B==1 are RESERVED. Interaction of these control bits with data alignment is discussed in Unaligned access support on page A2-38. Table A2-8 Endian and Alignment Control Bit Usage Summary U 0 0 0 0 0 A 0 0 0 0 1 B 0 0 1 1 0 E 0 1 0 1 0 Instruction Endianness LE BE-32 LE Data Endianness LE BE-32 LE Unaligned Behavior Rotated LDR Rotated LDR Data Abort Description Legacy LE / programmed BE configuration
RESERVED
(no E bit in legacy code)
Legacy BE (32-bit word-invariant)
RESERVED
(no E bit in legacy code)
modulo 8 LDRD/STRD doubleword alignment checking. LE Data
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-35
Programmers Model
Table A2-8 Endian and Alignment Control Bit Usage Summary (continued) U 0 0 0 1 1 1 1 1 1 1 A 1 1 1 0 0 0 1 1 1 1 B 0 1 1 0 0 1 0 0 1 1 E 1 0 1 0 1 x 0 1 0 1 Instruction Endianness LE BE-32 LE LE LE LE BE-32 Data Endianness BE-8 BE-32 LE BE-8 LE BE-8 BE-32 Unaligned Behavior Data Abort Data Abort Unaligned Unaligned Data Abort Data Abort Data Abort Description modulo 8 LDRD/STRD doubleword alignment checking. BE Data modulo 8 LDRD/STRD doubleword alignment checking, legacy BE
RESERVED
LE instructions, LE mixed-endian data, unaligned access permitted LE instructions, BE mixed-endian data, unaligned access permitted
RESERVED
modulo 4 alignment checking, LE Data modulo 4 alignment checking, BE data modulo 4 alignment checking, legacy BE
RESERVED
BE-32 and BE-8 are as defined in Endianness - an overview on page A2-31. Data aborts cause an alignment error to be reported in the Fault Status Register in the system coprocessor.
Note
The U, A and B bits are System Control Coprocessor bits, while the E bit is a CPSR/SPSR flag. The behavior of SETEND instructions (or any other instruction that modifies the CPSR) is UNPREDICTABLE when setting the E bit would result in a RESERVED state.
A2.7.4
Instructions to change CPSR E bit
ARM and Thumb instructions are provided to set and clear the E bit efficiently: SETEND BE Set the CPSR E bit. SETEND LE Reset the CPSR E bit. These are unconditional instructions. See ARM SETEND on page A4-129 and Thumb SETEND on page A7-95.
A2-36
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.7.5
Instructions to reverse bytes in a general-purpose register
When an application or device driver has to interface to memory-mapped peripheral registers or shared-memory DMA structures that are not the same endianness as that of the internal data structures, or the endianness of the Operating System, an efficient way of being able to explicitly transform the endianness of the data is required. ARMv6 ARM and Thumb instruction sets provide this functionality: Reverse word (four bytes) register, for transforming big and little-endian 32-bit representations. See ARM REV on page A4-109 and Thumb REV on page A7-88. Reverse halfword and sign-extend, for transforming signed 16-bit representations. See ARM REVSH on page A4-111 and Thumb REVSH on page A7-90. Reverse packed halfwords in a register for transforming big- and little-endian 16-bit representations. See ARM REV16 on page A4-110 and Thumb REV16 on page A7-89.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-37
Programmers Model
A2.8
Unaligned access support
The ARM architecture traditionally expects all memory accesses to be suitably aligned. In particular, the address used for a halfword access should normally be halfword-aligned, the address used for a word access should normally be word-aligned. Prior to ARMv6, doubleword (LDRD/STRD) accesses to memory, where the address is not doubleword-aligned, are UNPREDICTABLE. Also, data accesses to non-aligned word and halfword data are treated as aligned from the memory interface perspective. That is: the address is treated as truncated, with address bits[1:0] treated as zero for word accesses, and address bit[0] treated as zero for halfword accesses. load single word ARM instructions are architecturally defined to rotate right the word-aligned data transferred by a non word-aligned address one, two or three bytes depending on the value of the two least significant address bits. alignment checking is defined for implementations supporting a System Control coprocessor using the A bit in CP15 register 1. When this bit is set, a Data Abort indicating an alignment fault is reported for unaligned accesses.
ARMv6 introduces unaligned word and halfword load and store data access support. When this is enabled, the processor uses one or more memory accesses to generate the required transfer of adjacent bytes transparently to the programmer, apart from a potential access time penalty where the transaction crosses an IMPLEMENTATION DEFINED cache-line, bus-width or page boundary condition. Doubleword accesses must be word-aligned in this configuration.
A2.8.1
Unaligned instruction fetches
All instruction fetches must be aligned. Specifically they must be: word aligned in ARM state halfword aligned in Thumb state. Writing an unaligned address to R15 is UNPREDICTABLE, except in the specific cases where the instructions are associated with a Thumb to ARM state transition, bit[1] providing a valid address bit on transition to Thumb state, and bit[0] indicating whether a transition needs to occur. The BX instruction in ARM state (see BX on page A4-20) and POP instruction in Thumb state (see POP on page A7-82) are examples of instructions providing state transition support. The general rules for reading and writing the program counter are defined in Register 15 and the program counter on page A2-9.
A2-38
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.8.2
Unaligned data access in ARMv6 systems
ARMv6 uses the U bit (CP15 register 1 bit[22]) and A bit (CP15 register 1 bit[1]), to provide a configuration supporting the following unaligned memory accesses: Unaligned halfword accesses for LDRH, LDRSH and STRH. Unaligned word accesses for LDR, LDRT, STR and STRT.
The U bit and A bit are also used to configure endian support as described in Endian configuration and control on page A2-34. All other multi-byte load and store accesses shall be word aligned. Instructions must always be aligned (and in little endian format): ARM instructions must be word-aligned Thumb instructions must be halfword-aligned. In addition, an ARMv6 system shall reset to the CFGEND[1:0] condition as described in Table A2-7 on page A2-35. For ARMv6, Table A2-10 on page A2-40 defines when an alignment fault must occur for an access, and when the behavior of an access is architecturally UNPREDICTABLE. It also gives details of precisely which memory locations are returned for valid accesses. The access type descriptions used in this section are determined from the load/store instructions as described in Table A2-9: Table A2-9 Access Type Byte Halfword WLoad WStore WSync Two-word Multi-word ARM instructions
LDRB LDRBT LDRSB STRB STRBT SWPB (either access) LDRH LDRSH STRH LDR LDRT SWP (load access, if U == 0) STR STRT SWP (store access, if U == 0) LDREX STREX SWP (either access, if U == 1) LDRD STRD LDC LDM RFE SRS STC STM
Thumb instructions
LDRB LDRSB STRB LDRH LDRSH STRH LDR STR
LDMIA POP PUSH STMIA
The following terminology is used to describe the memory locations accessed: Byte[X] Means the byte whose address is X in the current endianness model. The correspondence between the endianness models is that Byte[A] in the LE endianness model, Byte[A] in the BE-8 endianness model, and Byte[A EOR 3] in the BE-32 endianness model are the same actual byte of memory.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-39
Programmers Model
Halfword[X] Means the halfword consisting of the bytes whose addresses are X and X+1 in the current endianness model, combined to form a halfword in little-endian order in the LE endianness model or in big-endian order in the BE-8 or BE-32 endianness model. Word[X] Means the word consisting of the bytes whose addresses are X, X+1, X+2, and X+3 in the current endianness model, combined to form a word in little-endian order in the LE endianness model or in big-endian order in the BE-8 or BE-32 endianness model.
Note
It is a consequence of these definitions that if X is word-aligned, Word[X] consists of the same four bytes of actual memory in the same order in the LE and BE-32 endianness models.
Align[X]
Means (X AND 0xFFFFFFFC) - that is, X with its least significant two bits forced to zero to make it word-aligned.
Note
There is no difference between Addr and Align(Addr) on lines for which Addr[1:0] == 0b00 anyway. This can be exploited by implementations to simplify the control of when the least significant bits are forced to zero. For the Two-word and Multi-word access types, the Memory accessed column only specifies the lowest word accessed. Subsequent words have addresses constructed by successively incrementing the address of the lowest word by 4, and are constructed using the same endianness model as the lowest word. Table A2-10 Data Access Behavior in ARMv6 Systems U 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 xxx xx0 xx1 xxx xxx x00 Byte Halfword Halfword WLoad WStore WSync Normal Normal
UNPREDICTABLE
Addr[2:0]
Access Types
Behavior
Memory accessed
Notes LEGACY, NO ALIGNMENT FAULTING
Byte[Addr] Halfword[Addr] Word[Align(Addr)] Word[Align(Addr)] Word[Addr]
Loaded data rotated right by 8 * Addr[1:0] bits Operation unaffected by Addr[1:0] -
Normal Normal Normal
A2-40
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Table A2-10 Data Access Behavior in ARMv6 Systems (continued) U 0 0 0 0 1 1 1 1 1 A 0 0 0 0 0 0 0 0 0 xxx xxx xxx x00 Byte Halfword WLoad WStore WSync Multi-word Two-word WSync Multi-word Two-word Normal Normal Normal Normal Byte[Addr] Halfword[Addr] Word[Addr] Word[Addr] Addr[2:0] xx1, x1x xxx 000 xx1, x1x, 1xx Access Types WSync Multi-word Two-word Two-word Behavior
UNPREDICTABLE
Memory accessed Word[Align(Addr)] Word[Addr] -
Notes Operation unaffected by Addr[1:0] NEW ARMv6 UNALIGNED SUPPORT -
Normal Normal
UNPREDICTABLE
1
0
xx1, x1x
Alignment Fault
-
-
x x x x x
1 1 1 1 1 xxx xx0 xx1 x00 Byte Halfword Halfword WLoad WStore WSync Multi-word WLoad WStore WSync Multi-word Normal Normal Alignment Fault Normal Byte[Addr] Halfword[Addr] Word[Addr]
FULL ALIGNMENT FAULTING -
x
1
xx1, x1x
Alignment Fault
-
-
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-41
Programmers Model
Table A2-10 Data Access Behavior in ARMv6 Systems (continued) U x 0 1 x A 1 1 1 1 Addr[2:0] 000 100 100 xx1, x1x Access Types Two-word Two-word Two-word Two-word Behavior Normal Alignment Fault Normal Alignment Fault Memory accessed Word[Addr] Word[Addr] Notes -
Other reasons for unaligned accesses to be UNPREDICTABLE
The following exceptions to the behavior described in Table A2-10 on page A2-40 apply, causing the resultant unaligned accesses to be UNPREDICTABLE: An LDR instruction that loads the PC, has Addr[1:0] != 0b00, and is specified in the table as having Normal behavior instead has UNPREDICTABLE behavior.
Note
The reason this applies only to LDR is that most other load instructions are UNPREDICTABLE regardless of alignment if the PC is specified as their destination register. The exceptions are LDM, RFE and Thumb POP. If Addr[1:0] != 0b00 for these instructions, the effective address of the transfer has its two least significant bits forced to 0 if A == 0 and U ==0, and otherwise the behavior specified in the table is either UNPREDICTABLE or Alignment Fault regardless of the destination register. Any WLoad, WStore, WSync, Two-word or Multi-word instruction that accesses memory with the Strongly Ordered or Device memory attribute, has Addr[1:0] != 0b00, and is specified in the table as having Normal behavior instead has UNPREDICTABLE behavior. Any Halfword instruction that accesses memory with the Strongly Ordered or Device memory attribute, has Addr[0] != 0, and is specified in the table as having Normal behavior instead has UNPREDICTABLE behavior.
If any of these reasons applies, it overrides the behavior specified in the table.
Note
These reasons never cause Alignment Fault behavior to be overridden. ARM implementations are not required to ensure that the low-order address bits that make an access unaligned are cleared from the address they send to memory. They can instead send the address as calculated by the load/store instruction unchanged to memory, and require the memory system to ignore address[0] for a halfword access and address[1:0] for a word access.
A2-42
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
When an instruction ignores the low-order address bits that make an access unaligned, the pseudo-code in the instruction description does not mask them out explicitly. Instead, the Memory[<address>,<size>] function used in the pseudo-code masks them out implicitly.
ARMv6 unaligned data access restrictions
ARMv6 has the following restrictions on unaligned data accesses: Accesses are not guaranteed atomic. They can be synthesized out of a series of aligned operations in a shared memory system without guaranteeing locked transaction cycles. Accesses typically take a number of cycles to complete compared to a naturally aligned transfer. The real-time implications must be carefully analyzed and key data structures might need to have their alignment adjusted for optimum performance. Accesses can abort on either or both halves of an access where this occurs over a page boundary. The Data Abort handler must handle restartable aborts carefully after an Alignment Fault Status Code is signaled.
Therefore shared memory schemes should not rely on seeing monotonic updates of non-aligned data of loads, stores, and swaps for data items greater than byte width. Unaligned access operations should not be used for accessing Device memory-mapped registers. They must also be used with care in shared memory structures that are protected by aligned semaphores or synchronization variables.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-43
Programmers Model
A2.9
Synchronization primitives
Historically, support for shared memory synchronization has been with the read-locked-write operations that swap register contents with memory; the SWP and SWPB instructions described in SWP on page A4-212 and SWPB on page A4-214. These support basic busy/free semaphore mechanisms, but not mechanisms that require calculation to be performed on the semaphore between the read and write phases. ARMv6 provides a new mechanism to support more comprehensive non-blocking shared-memory synchronization primitives that scale for multiple-processor system designs.
Note
The swap and swap byte instructions are deprecated in ARMv6. It is recommended that all software migrates to using the new synchronization primitives. Two instructions are introduced to the ARM instruction set: Load-Exclusive described in LDREX on page A4-52 Store-Exclusive described in STREX on page A4-202. The instructions operate in concert with an address monitor, which provides the state machine and associated system control for memory accesses. Two different monitor models exist, depending on whether the memory has the sharable or non-sharable memory attribute. See Shared attribute on page B2-12. Uniprocessor systems are only required to support the non-shared memory model, allowing them to support synchronization primitives with the minimum amount of hardware overhead. An example minimal system is illustrated in Figure A2-2.
L2 RAM L2 Cache Bridge to L3
Routing matrix
Monitor
CPU 1
Figure A2-2 Example uniprocessor (non-shared) monitor Multi-processor systems are required to implement an address monitor for each processor. It is IMPLEMENTATION DEFINED where the monitors reside in the memory system hierarchy, whether they are implemented as a single entity for each processor visible to all shared accesses, or as a distributed entity. Figure A2-3 on page A2-45 illustrates a single entity approach in which the monitor supports state machines for both the shared and non-shared cases. Only the shared attribute case needs to snoop.
A2-44
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
L2 RAM
L2 Cache
Bridge to L3
Routing matrix
Monitor
Monitor
CPU 1
CPU 2
Figure A2-3 Write snoop monitor approach Figure A2-4 illustrates a distributed model with local monitors residing in the processor blocks, and global monitors distributed across the targets of interest.
Shared L2 RAM Mon 2 Mon 1 Nonshared L2 RAM L2 Cache Mon 2 Mon 1 Bridge to L3 Mon 2 Mon 1
Routing matrix
Local Monitor CPU 1
Local Monitor CPU 2
Figure A2-4 Monitor-at-target approach
A2.9.1
Exclusive access instructions: non-shared memory
For memory regions that do not have the Shared TLB attribute, the exclusive-access instructions rely on the ability to tag the fact that an exclusive load has been executed. Any non-aborted attempt by the processor that executed the exclusive load to modify any address using an exclusive store is guaranteed to clear this tag.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-45
Programmers Model
Note
In non-shared memory, it is UNPREDICTABLE whether a store to a tagged physical address will cause a tag to be cleared when that store is by a processor other than the one that caused the physical address to be tagged. Load-Exclusive performs a load from memory, and causes the executing processor to tag the fact that it has an outstanding tagged physical address to non-sharable memory; the monitor transitions state to Exclusive Access. Store-Exclusive performs a conditional store to memory, the store only taking place if the local monitor of the executing processor is in the Exclusive Access state. A status value of 0b0 is returned to a register, and the executing processor's monitor transitions to the Open Access state. If the store is prevented, a value of 0b1 is returned in the instruction defined register. A write to a physical address not covered by the local monitor by that processor using any instruction other than a Store-Exclusive will not affect the state of the local monitor. It is IMPLEMENTATION DEFINED whether a write (other than with a Store-Exclusive) to the physical address which is covered by the monitor will affect the state of the local monitor. If a processor performs a Store-Exclusive to any address in non-shared memory other than the last one from which it has performed a Load-Exclusive, and the monitor is in the exclusive state, it is IMPLEMENTATION DEFINED whether the store will succeed in this case. This mechanism is used on a context switch (see section Context switch support on page A2-48). It should be treated as a software programming error in all other cases. The state machine for the associated data monitor is illustrated in Figure A2-5.
Tagged_address <= x[31:a] STREX(x), STR(x) Rm <= 1b1; Do not update memory LDREX(x) Tagged_address <= x[31:a] LDREX(x) Exclusive Access STREX(Tagged_address) STR(!Tagged_address) STR(Tagged_address)
Open Access
Rm <= 1b0; update memory
STREX(!Tagged_address) (Rm <= 1b0 AND update memory) OR STR(Tagged_address) (Rm <= 1b1 AND do not update memory)
The arcs in italics show allowable alternative (IMPLEMENTATION DEFINED) options. The Tagged_address value of a is IMPLEMENTATION DEFINED to a value between 2 and 7 inclusive.
Figure A2-5 State diagram - local monitor
A2-46
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Note
The IMPLEMENTATION DEFINED options for the local monitor are consistent with the local monitor being constructed in a manner that it does not hold any physical address, but instead treats all accesses as matching the address of the previous LDREX. The behavior illustrated is for the local address monitor associated with the processor issuing the LDREX, STREX and STR instructions. The transition from Exclusive Access to Open Access is UNPREDICTABLE when the STR or STREX is from a different processor. Transactions from other processors need not be visible to this monitor.
A2.9.2
Exclusive access instructions: shared memory
For memory regions that have the Shared TLB attribute, the exclusive-access instructions rely on the ability of a global monitor to tag a physical address as exclusive-access for a particular processor. This tag will later be used to determine whether an exclusive store to that address should occur. Any non-aborted attempt to modify that address by any processor is guaranteed to clear this tag. A global monitor can reside in a processor block as illustrated in Figure A2-3 on page A2-45, or as a secondary monitor at the memory interface, as shown in Figure A2-4 on page A2-45. The functionality of the global and local monitors can be combined into a single monitor in implementations. Load-Exclusive from shared memory performs a load from memory, and causes the physical address of the access to be tagged as exclusive-access for the requesting processor. This also causes any other physical address that has been tagged by the requesting processor to no longer be tagged as exclusive access; only a single outstanding exclusive access to sharable memory per processor is supported. Store-Exclusive performs a conditional store to memory. The store is only guaranteed to take place if the physical address is tagged as exclusive-access for the requesting processor. If no address is tagged as exclusive-access, the store will not succeed. If a different physical address is tagged as exclusive-access for the requesting processor, it is IMPLEMENTATION DEFINED whether the store will succeed or not. A status value of 0b0 is returned to a register to acknowledge a successful store, otherwise a value of 0b1 is returned. In the case where the physical address is tagged as exclusive-access for the requesting processor, the state of the exclusive monitor transitions to the Open Access state, and if the monitor was originally in the Open Access state, it remains in this state. Otherwise, it is IMPLEMENTATION DEFINED whether the monitor remains in the Exclusive Access state or transitions to the Open Access state. Every processor (or independent DMA agent) in a shared memory system requires its own address monitor. The state machine for the global address monitor associated with a processor (n) in a multiprocessing environment interacts with all the memory accesses visible to it: transactions generated by the associated processor (n) transactions associated with other processors in the shared memory system (!n). The behavior is illustrated in Figure A2-6 on page A2-48.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-47
Programmers Model
Rm <= 1b1; Do not update memory
STREX(x,n), STR(x,n) LDREX(x,!n), STREX(x,!n), STR(x,!n)
Tagged_address <= x[31:a]
Tagged_address <= x[31:a]
(Rm <= 1b1 AND do not update memory) OR Exclusive Open Access (Rm <= 1b0 Access AND update memory) STR(!Tagged_address,n), (Rm <= 1b0 AND update memory) STREX(Tagged_address,!n)*, STR(Tagged_address,n), STR(Tagged_address,!n) STREX(!Tagged_address,n), STREX(Tagged_address,n), STREX(Tagged_address,n), (Rm <= 1b1 AND do not update memory) STREX(!Tagged_address,n), STR(!Tagged_address,!n), OR STR(Tagged_address,n) STREX(!Tagged_address,!n) (Rm <= 1b0 AND update memory) (Rm <= 1b0 AND * STREX(Tagged_Address,!n) only clears monitor if the STREX updates memory update memory) LDREX(x,n) LDREX(x,n) The arcs in italics show allowable alternative (IMPLEMENTATION DEFINED) options. The Tagged_address value of a is IMPLEMENTATION DEFINED to a value between 2 and 7 inclusive.
Figure A2-6 State diagram - global monitor
Note
Whether a STREX successfully updates memory or not is dependent on a tag address match with its associated global monitor, hence the (!n) entries are only shown with respect to how they influence state transitions of the state machine. Similarly, an LDREX can only update the tag of its associated global monitor.
A2.9.3
Context switch support
On a context switch, it is necessary to ensure that the local monitor is in the Open Access state after a context switch. This requires execution of a dummy STREX to an address in memory allocated for this purpose. For reasons of performance, it is recommended that the store-exclusive instruction be within a few instructions of the load-exclusive instruction. This minimizes the opportunity for context switch overhead or multiprocessor access conflicts causing an exclusive store to fail, and requiring the load/store sequence to be replayed.
A2-48
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.9.4
Summary of operation
The following pseudo-functions can be used to describe the exclusive access operations: TLB(<Rm>) Shared(<Rm>) ExecutingProcessor() MarkExclusiveGlobal(<physical_address>,<processor_id>,<size>) MarkExclusiveLocal(<physical address>,<processor_id>,size>) IsExclusiveGlobal(<physical_address>,<processor_id>,<size>) IsExclusiveLocal(<physical_address>,<processor_id>,<size>) ClearExclusiveByAddress(<physical_address>,<processor_id>,<size>) ClearExclusiveLocal(<processor_id>). 1. If CP15 register 1 bit[0] (Mbit) is set, TLB(<Rm>) returns the physical address corresponding to the virtual address in Rm for the executing processor's current process ID and TLB entries. If Mbit is not set, or the system does not implement a virtual to physical translation, it returns the value in Rm. If CP15 register 1 bit[0] (Mbit) is set, Shared(<Rm>) returns the value of the shared memory region attribute corresponding to the virtual address in Rm for the executing processor's current process ID and TLB entries for the VMSA, or the PMSA region descriptors. If Mbit is not set, the value returned is a function of the memory system behavior (see Chapter B4 Virtual Memory System Architecture and Chapter B5 Protected Memory System Architecture). ExecutingProcessor() returns a value distinct amongst all processors in a given system, corresponding to the processor executing the operation. MarkExclusiveGlobal(<physical_address>,<processor_id>,<size>) records the fact that processor <processor_id> has requested exclusive access covering at least <size> bytes from address <physical_address>. The size of region marked as exclusive is IMPLEMENTATION DEFINED, up to a limit of 128 bytes, and no smaller than <size>, and aligned in the address space to the size of the region. It is UNPREDICTABLE whether this causes any previous request for exclusive access to any other address by the same processor to be cleared. MarkExclusiveLocal(<physical_address>,<processor_id>,<size>) records in a local record the fact that processor <processor_id> has requested exclusive access to an address covering at least <size> bytes from address <physical_address>. The size of the region marked as exclusive is IMPLEMENTATION DEFINED, and can at its largest cover the whole of memory, but is no smaller than <size>, and is aligned in the address space to the size of the region. It is IMPLEMENTATION DEFINED whether this also performs a MarkExclusiveGlobal(<physical_address>,<processor_id>,<size>). IsExclusiveGlobal(<physical_address>,<processor_id>,<size>) returns TRUE if the processor <processor_id> has marked in a global record an address range as exclusive access requested which covers at least the <size> bytes from address <physical_address>. It is IMPLEMENTATION DEFINED whether it returns TRUE or FALSE if a global record has marked a different address as exclusive access requested. If no address is marked in a global record as exclusive access, IsExclusiveGlobal(<physical_address>,<processor_id>,<size>) will return FALSE.
2.
3. 4.
5.
6.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-49
Programmers Model
7.
IsExclusiveLocal(<physical_address>,<processor_id>,<size>) returns TRUE if the processor <processor_id> has marked an address range as exclusive access requested which covers at least the <size> bytes from address <physical_address>. It is IMPLEMENTATION DEFINED whether this function returns TRUE or FALSE if the address marked as exclusive access requested does not cover all of the <size> bytes from address <physical_address>. If no address is marked as exclusive access requested, then this function returns FALSE. It is IMPLEMENTATION DEFINED whether this result is ANDed with the result of an IsExclusiveGlobal(<physical_address>,<processor_id>,<size>). ClearExclusiveByAddress(<physical_address>,<processor_id>,<size>) clears the global records of all processors, other than <processor_id>, that an address region including any of the bytes between <physical_address> and (<physical_address>+<size>-1) has had a request for an exclusive access. It is IMPLEMENTATION DEFINED whether the equivalent global record of the processor <processor_id> is also cleared if any of the bytes between <physical_address> and (<physical_address>+<size>-1) have had a request for an exclusive access, or if any other address has had a request for an exclusive access.
8.
9.
ClearExclusiveLocal(<processor_id>) clears the local record of processor <processor_id> that an address has had a request for an exclusive access. It is IMPLEMENTATION DEFINED whether this operation also clears the global record of processor <processor_id> that an address has had a request for an exclusive access.
For the purpose of this definition, a processor is defined as a system component, including virtual system components, which is capable of generating memory transactions. The processor_id is defined as a unique identifier for a processor.
Effects on other store operations
All executed store operations gain the following functional behavior to their pseudo-code operation:
processor_id = ExecutingProcessor() if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,size)
Load and store operation
The exclusive accesses can be described in terms of their register file usage: Rd: the destination register, for data on loads, status on stores Rm: the source data register for stores Rn: the memory address register for loads and stores.
A2-50
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A pseudo-code representation is as follows.
LDREX operation: if ConditionPassed (cond) then processor_id = ExecutingProcessor() Rd = Memory[Rn,4] physical_address = TLB(Rn) if Shared(Rn) == 1 then MarkExclusiveGlobal(physical_address,processor_id,4) MarkExclusiveLocal(physical_address,processor_id,4) STREX operation: if ConditionPassed(cond) then processor_id = ExecutingProcessor() physical_address = TLB(Rn) if IsExclusiveLocal(physical_address,processor_id,4) then if Shared(Rn) == 1 then if IsExclusiveGlobal(physical_address,processor_id,4) then Memory[Rn,4] = Rm Rd = 0 ClearExclusiveByAddress(physical_address,processor_id,4) else Rd = 1 else Memory[Rn,4] =Rm Rd = 0 else Rd = 1 ClearExclusiveLocal(processor_id)
Note
The behavior of STREX in regions of shared memory that do not support exclusives (for example, have no exclusives monitor implemented) is UNPREDICTABLE. For a complete definition of the instruction behavior see LDREX on page A4-52 and STREX on page A4-202.
Usage restrictions
The LDREX and STREX instructions are designed to work in tandem. In order to support a number of different implementations of these functions, the following notes and restrictions must be followed: 1. The exclusives are designed to support a single outstanding exclusive access for each processor thread that is executed. The architecture makes use of this by not mandating an address or size check as part of the IsExclusiveLocal() function. If the target address of an STREX is different from the preceding LDREX within the same execution thread, it can lead to UNPREDICTABLE behavior. As a result, an LDREX/STREX pair can only be relied upon to eventually succeed if they are executed with the same address. Where a context switch or exception might result in a change of execution thread, a
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-51
Programmers Model
dummy STREX instruction, as described in Context switch support on page A2-48 should be executed to avoid unwanted effects. This is the only occasion where an STREX is expected to be programmed with a different address from the previously executed LDREX. 2. An explicit store to memory can cause the clearing of exclusive monitors associated with other processors, therefore, performing a store between the LDREX and the STREX can result in livelock situations. As a result, code should avoid placing an explicit store between an LDREX and an STREX within a single code sequence. Two STREX instructions executed without an intervening LDREX will also result in the second STREX returning FALSE. As a result, it is expected that each STREX should have a preceding LDREX associated with it within a given thread of execution, but it is not necessary that each LDREX must have a subsequent STREX. Implementations can cause apparently spurious clearing of the exclusive monitor between the LDREX and the STREX, as a result of, for example, cache evictions. Code designed to run on such implementations should avoid having any explicit memory transactions or cache maintenance operations between the LDREX and STREX instructions. Implementations can benefit from keeping the LDREX and STREX operations close together in a single code sequence. This reduces the likelihood of spurious clearing of the exclusive monitor state occurring, and as a result, a limit of 128 bytes between LDREX and STREX instructions in a single code sequence is strongly recommended for best performance. Implementations which implement coherent protocols, or have only a single master, may combine the local and global monitors for a given processor. The IMPLEMENTATION DEFINED and UNPREDICTABLE parts of the definitions in Summary of operation on page A2-49. are designed to cover this behavior. The architecture sets an upper limit of 128 bytes on the regions that may be marked as exclusive. Therefore, for performance reasons, software is recommended to separate objects that will be accessed by exclusive accesses by at least 128 bytes. This is a performance guideline rather than a functional requirement
LDREX and STREX operations shall only be performed on memory supporting the Normal memory
3.
4.
5.
6.
7.
8. 9.
attribute. The effect of data aborts are UNPREDICTABLE on the state of monitors. It is recommended that abort handling code performs a dummy STREX instruction to clear down the monitor state.
A2-52
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.10 The Jazelle Extension
The Jazelle Extension was first introduced in ARMv5TEJ, a variant of ARMv5, and is a mandated feature in ARMv6. The Jazelle Extension enables architectural support for hardware acceleration of opcode execution by Java Virtual Machines (JVMs). It is designed in such a way that JVMs can be written to automatically take advantage of any accelerated opcode execution supplied by the processor, without relying upon it being present. In the simplest implementations, the processor does not accelerate the execution of any opcodes, and all opcodes are executed by software routines. This is known as a trivial implementation of the Jazelle Extension, and has minimal costs compared with not implementing the Jazelle Extension at all. Non-trivial implementations of the Jazelle Extension will typically implement a subset of the opcodes in hardware, choosing opcodes that can have simple hardware implementations and that account for a large percentage of Jazelle execution time. The required features of a non-trivial implementation are: provision of an additional state bit (the J bit) in the CPSR and each SPSR a new instruction to enter Jazelle state (BXJ) extension of the PC to support full 32-bit byte addressing changes to the exception model mechanisms to allow a JVM to configure the Jazelle Extension hardware to its specific needs mechanisms to allow OSes to regulate use of the Jazelle Extension hardware. The required features of a trivial implementation are: Only ARM and Thumb execution states shall exist. The J bit may always read and write as zero. Should the J bit update to one, execution of the following instruction is UNDEFINED. The BXJ instruction shall behave as a BX instruction. Configuration support that maintains the interface as permanently disabled.
A JVM that has been written to automatically take advantage of hardware-accelerated opcode execution is known as an Enabled JVM (EJVM).
A2.10.1 Subarchitectures
ARM implementations that include the Jazelle Extension expect the ARM processors general-purpose registers and other resources to obey a calling convention when Jazelle state execution is entered and exited. For example, a specific general-purpose register may be reserved for use as the pointer to the current opcode. In order for an EJVM or associated debug support to function correctly, it must be written to comply with the calling convention expected by the acceleration hardware at Jazelle state execution entry and exit points. The calling convention is relied upon by an EJVM, but not in general by other system software. This limits the cost of changing the convention to the point that it can be considered worthwhile to change it if a sufficient technical advantage is obtained by doing so, such as a significant performance improvement in opcode execution.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-53
Programmers Model
Multiple conventions are known collectively as the subarchitecture of the implementation. They are not described in this document, and must only be relied upon by EJVM implementations and debug/similar software as described above. All other software must only rely upon the general architectural definition of the Jazelle Extension described in this section. A particular subarchitecture is identified by reading the Jazelle ID register described in Jazelle ID register on page A2-62.
A2.10.2 Jazelle state
The Jazelle Extension makes use of an extra state bit (J) in the processor status registers (the CPSR and the banked SPSRs). This is bit[24] of the registers concerned:
31 30 29 28 27 26 25 24 23 20 19 16 15
RESERVED
10 9 8
7654
0
N Z C V Q Rsrvd J
RESERVED
GE[3:0]
EAI FT
Mode
The other bit fields are described in Program status registers on page A2-11.
Note
The placement of the J bit in the flags byte was to avoid any usage of the status or extension bytes in code run on ARMv5TE or earlier processors. This ensures that OS code written using the deprecated CPSR, SPSR, CPSR_all or, SPSR_all syntax for the destination of an MSR instruction only ceases to work when features introduced in ARMv6 are used, namely the E, A and GE bit fields. In addition, J is always 0 at times that an MSR instruction is executed. This ensures there are no unexpected side-effects of existing instructions such as MSR CPSR_f,#0xF0000000, that are used to put the flags into a known state. The J bit is used in conjunction with the T bit to determine the execution state of the processor, as shown in Table A2-11. Table A2-11 J 0 0 1 1 T 0 1 0 1 Execution state ARM state, executing 32-bit ARM instructions Thumb state, executing 16-bit Thumb instructions Jazelle state, executing variable-length Jazelle opcodes
UNDEFINED,
and reserved for future expansion
The J bit is treated similarly to the T bit in the following respects: On exception entry, both bits are copied from the CPSR to the exception modes SPSR, and then cleared in the CPSR to put the processor into the ARM state.
A2-54
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Data processing instructions with Rd = R15 and the S bit set cause these bits to be copied from the SPSR to the CPSR and execution to resume in the resulting state. This ensures that these instructions have their normal exception return functionality. Such exception returns are expected to use the SPSR and R14 values generated by a processor exception entry and to use the appropriate return instruction for the exception concerned, as described in Exceptions on page A2-16. If return values are used with J == 1 and T == 0 in the SPSR value, then the results are SUBARCHITECTURE DEFINED.
Similarly, LDM instructions with the PC in the register list and ^ specified (that is, LDM (3) instructions, as described in LDM (3) on page A4-40) cause both bits to be copied from the SPSR to the CPSR and execution to resume in the resulting state. These instructions are also used for exception returns, and the considerations in the previous bullet point also apply to them. In privileged modes, execution of an MSR instruction that attempts to set the J or T bit of the CPSR to 1 has UNPREDICTABLE results. In unprivileged (User) mode, execution of an MSR instruction that attempts to set the J or T bit of the CPSR to 1 will not modify the bit. Setting J == 1 and T == 1 causes similar effects to setting T == 1 on a non Thumb-aware processor. That is, the next instruction executed will cause entry to the Undefined Instruction exception. Entry to the exception handler will cause the processor to re-enter ARM state, and the handler can detect that this was the cause of the exception because J and T are both set in SPSR_und.
While in Jazelle state, the processor executes opcode programs. An opcode program is defined to be an executable object comprising one or more class files, as defined in Lindholm and Yellin, The Java Virtual Machine Specification 2nd Edition, or derived from and functionally equivalent to one or more class files. While in Jazelle state, the PC acts as a program counter which identifies the next JVM opcode to be executed, where JVM opcodes are the opcodes defined in Lindholm and Yellin, or a functionally equivalent transformed version of them. Native methods, as described in Lindholm and Yellin, for the Jazelle Extension must use only the ARM and/or Thumb instruction sets to specify their functionality. An implementation of the Jazelle Extension must not be documented or promoted as performing any task while it is in Jazelle state other than the acceleration of opcode programs in accordance with this section and Lindholm and Yellin.
Extension of the PC to 32 bits
In order to allow the PC to point to an arbitrary opcode, all 32 bits of the PC are defined in non-trivial implementations. Bit[0] of the PC always reads as zero when in ARM or Thumb state. Bit[1] reflects the word-alignment, or halfword-alignment of ARM and Thumb instructions respectively. The existence of bit[0] in the PC is only visible in ARM or Thumb state due to an exception occurring in Jazelle state, and the exception return address is odd-byte aligned. The main architectural implication of this is that exception handlers must ensure that they restore all 32 bits of R15. The recommended ways to handle exception returns behave correctly.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-55
Programmers Model
A2.10.3
New Jazelle state entry instruction (BXJ)
An ARM instruction similar to BX is added. The BXJ instruction has a single register operand that specifies a target execution state (ARM or Thumb) and branch target address for use if entry to Jazelle state is not available. See BXJ on page A4-21 for more details. Compliant Java execution involves the EJVM using the BXJ instruction, the usage model of the standard ARM registers, and the Jazelle Extension Control and Configuration registers described in Configuration and control on page A2-62.
Executing BXJ with Jazelle Extension enabled
Executing a BXJ instruction when the JE bit is 1 gives the Jazelle Extension hardware an opportunity to enter Jazelle state and start executing opcodes directly. The circumstances in which Jazelle state execution is entered are IMPLEMENTATION DEFINED. If Jazelle state execution is not entered, the instruction is executed in the same way as a BX instruction to a SUBARCHITECTURE DEFINED register usage model. This is required to ensure the Jazelle Extension hardware and the EJVM software communicate effectively with each other. Similarly, various registers will contain SUBARCHITECTURE DEFINED values when Jazelle state execution is terminated and ARM or Thumb state execution is resumed. The precise set of registers affected by these requirements is a SUBARCHITECTURE DEFINED subset of the process registers, which are defined to be: the ARM general-purpose registers R0-R14 the PC the CPSR the VFP general-purpose registers S0-S31 and D0-D15, subject to the VFP architectures restrictions on their use and subject to the VFP architecture being present the FPSCR, subject to the VFP architecture being present. All processor state that can be modified by Jazelle state execution must be kept in process registers, in order to ensure that it is preserved and restored correctly when processor exceptions and process swaps occur. Configuration state (that is, state that affects Jazelle state execution but is not modified by it) can be kept either in process registers or in configuration registers. EJVM implementations should only set JE == 1 after determining that the processors Jazelle Extension subarchitecture is compatible with their usage of the process registers. Otherwise, they should leave JE == 0 and execute without hardware acceleration.
Executing BXJ with Jazelle Extension disabled
If a BXJ instruction is executed when the JE bit is 0, it is executed identically to a BX instruction with the same register operand.
BXJ instructions can therefore be freely executed when the JE bit is 0. In particular, if an EJVM determines
that it is executing on a processor whose Jazelle Extension implementation is trivial or uses an incompatible subarchitecture, it can set JE == 0 and execute correctly, without the benefit of any Jazelle hardware acceleration that may be present.
A2-56
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Jazelle state exit
The processor exits Jazelle state in IMPLEMENTATION DEFINED circumstances. This is typically due to attempted execution of an opcode that the implementation cannot handle in hardware, or that generates a Jazelle exception (such as a Null-Pointer exception). When this occurs, various processor registers will contain SUBARCHITECTURE DEFINED values, allowing the EJVM to resume software execution of the opcode program correctly. The processor also exits Jazelle state when a processor exception occurs. The CPSR is copied to the exception modes banked SPSR as normal, so the banked SPSR contains J == 1 and T == 0, and Jazelle state is restored on return from the exception when the SPSR is copied back into the CPSR. Coupled with the restriction that only process registers can be modified by Jazelle state execution, this ensures that all registers are correctly preserved and restored by processor exception handlers. Configuration and control registers may be modified in the exception handler itself as described in Configuration and control on page A2-62. Considerations specific to execution of opcodes apply to processor exceptions. For details of these, see Jazelle Extension exception handling on page A2-58. It is IMPLEMENTATION DEFINED whether Jazelle Extension hardware contains state that is modified during Jazelle state execution, and is held outside the process registers during Jazelle state execution. If such state exists, the implementation shall: Initialize the state from one or more of the process registers whenever Jazelle state is entered, either as a result of execution of a BXJ instruction or of returning from a processor exception. Write the state into one or more of the process registers whenever Jazelle state is exited, either as a result of taking a processor exception or of IMPLEMENTATION DEFINED circumstances. Ensure that the ways in which it is written into process registers on taking a processor exception, and initialized from process registers on returning from that exception, result in it being correctly preserved and restored over the exception.
Additional Jazelle state restrictions
The Jazelle Extension hardware shall obey the following restrictions: It must not change processor mode other than by taking one of the standard ARM processor exceptions. It must not access banked versions of registers other than the ones belonging to the processor mode in which it is entered. It must not do anything that is illegal for an UNPREDICTABLE instruction. That is, it must not generate a security loophole, nor halt or hang the processor or any other part of the system.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-57
Programmers Model
As a result of these requirements, Jazelle state can be entered from User mode without risking a breach of OS security. In addition: Entering Jazelle state from FIQ mode has UNPREDICTABLE results. Jazelle Extension subarchitectures and implementations must not make use of otherwise-unallocated CPSR and SPSR bits. All such bits are reserved for future expansion of the ARM and Thumb architectures.
A2.10.4 Jazelle Extension exception handling
All exceptions copy the J bit from the CPSR to the SPSR, and all instructions that have the side-effect of copying the SPSR to the CPSR must copy the J bit along with all the other bits. When an exception occurs in Jazelle state, the R14 register for the exception mode is calculated as follows: IRQ/FIQ Address of opcode to be executed on return from interrupt + 4.
Prefetch Abort Address of the opcode causing the abort + 4. Data Abort Address of the opcode causing the abort + 8.
Undefined instruction Must not occur. See Undefined Instruction exceptions on page A2-60. SWI Must not occur. See SWI exceptions on page A2-60.
Interrupts (IRQ and FIQ)
In order for the standard mechanism for handling interrupts to work correctly, Jazelle Exception hardware implementations must take care that whenever an interrupt is allowed to occur during Jazelle state execution, one of the following occurs: Execution has reached an opcode instruction boundary. That is, all operations required to implement one opcode have completed, and none of the operations required to implement the next opcode have completed. The R14 value on entry to the interrupt handler must be the address of the next opcode, plus 4. The sequence of operations performed from the start of the current opcodes execution up to any point where an interrupt can occur is idempotent: that is, it can be repeated from its start without changing the overall result of executing the opcode. The R14 value on entry to the interrupt handler must be the address of the current opcode, plus 4. If an interrupt does occur during an opcodes execution, corrective action is taken either directly by the Jazelle Extension hardware or indirectly by it calling a SUBARCHITECTURE DEFINED handler in the EJVM, and that corrective action re-creates a situation in which the opcode can be re-executed from its start. The R14 value on entry to the interrupt handler must be the address of the opcode, plus 4.
A2-58
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
Data aborts
The value saved in R14_abt on a data abort shall ensure that a virtual memory data abort handler can read the system coprocessor (CP15) Fault Status and Fault Address registers, fix the reason for the abort and return using SUBS PC,R14,#8 or its equivalent, without looking at the instruction that caused the abort or which state it was executed in.
Note
This assumes that the intention is to return to and retry the opcode that caused the data abort. If the intention is instead to return to the opcode after the one that caused the abort, then the return address will need to be modified by the length of the opcode that caused the abort. In order for the standard mechanism for handling data aborts to work correctly, Jazelle Exception hardware implementations must ensure that one of the following applies where an opcode might generate a data abort: The sequence of operations performed from the start of the opcodes execution up to the point where the data abort occurs is idempotent. That is, it can be repeated from its start without changing the overall result of executing the opcode. If the data abort occurs during opcode execution, corrective action is taken either directly by the Jazelle Extension hardware or indirectly by it calling a SUBARCHITECTURE DEFINED handler in the EJVM, and that corrective action re-creates a situation in which the opcode can be re-executed from its start.
Note
In ARMv6, the Base Updated Abort Model is no longer allowed (see Abort models on page A2-23). This removes one potential obstacle to the first of these solutions.
Prefetch aborts
The value saved in R14_abt on a prefetch abort shall ensure that a virtual memory prefetch abort handler can locate the start of the instruction that caused the abort simply and without looking at the state in which its execution was attempted. It is always at address (R14_abt 4). However, a multi-byte opcode may cross a page boundary, in which case the ARM processors prefetch abort handler cannot determine directly which of the two pages caused the abort. It is SUBARCHITECTURE DEFINED how this situation is handled, subject to the requirement that if it is handled by calling the ARM processors prefetch abort handler, (R14_abt 4) must point to the first byte of the opcode concerned. In order to ensure subarchitecture-independence, OS designers should write prefetch abort handlers in such a way that they can handle a prefetch abort generated in either of the two pages spanned by such a opcode. A suggested simple technique is:
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-59
Programmers Model
IF the page pointed to by (R14_abt 4) is not mapped THEN map the page ELSE map the page following the page including (R14_abt 4) ENDIF retry the instruction
SWI exceptions
SWI exceptions must not occur during Jazelle state execution, for the following reasons: ARM and Thumb state SWIs are supported in the ARM architecture. Opcode SWIs are not supported, due to the additional complexity they would introduce in the SWI usage model. Jazelle Extension subarchitectures and implementations need to have a mechanism to return to ARM or Thumb state handlers in order to execute the more complex opcode. If a opcode needs to make an OS call, it can make use of this mechanism to cause an ARM or Thumb SWI instruction to be executed, with a small overhead in percentage terms compared with the cost of the OS call itself. SWI calling conventions are highly OS-dependent, and would potentially require the subarchitecture to be OS aware.
Undefined Instruction exceptions
Undefined Instruction exceptions must not occur during Jazelle state execution. When the Jazelle Extension hardware synthesizes a coprocessor instruction and passes it to a hardware coprocessor (most likely, a VFP coprocessor), and the coprocessor rejects the instruction, there are considerable complications involved if this was allowed to result in the ARM processors Undefined Instruction trap. These include: The coprocessor instruction is not available to be loaded from memory (something that is relied upon by most Undefined Instruction handlers). The coprocessor instruction cannot typically be determined from the opcode that is loadable from memory without considerable knowledge of implementation and subarchitecture details of the Jazelle Extension hardware. The coprocessor-generated Undefined Instruction exceptions (and VFP-generated ones in particular) can typically be either precise (that is, caused by the instruction at (R14_und 4)) or imprecise (that is, caused by a pending exceptional condition generated by some earlier instruction and nothing to do with the instruction at (R14_und 4)). Precise Undefined Instruction exceptions typically must be handled by emulating the instruction at (R14_und 4), followed by returning to the instruction that follows it. Imprecise Undefined Instruction exceptions typically need to be handled by getting details of the exceptional condition and/or the earlier instruction from the coprocessor, fixing things up in some way, and then returning to the instruction at (R14_und 4). This means that there are two different possible return addresses, not necessarily at a fixed offset from each other as they are when dealing with coprocessor instructions in memory, making it difficult to define the value R14_und should have on entry to the Undefined Instruction handler.
A2-60
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
The return address for the Undefined Instruction handler places idempotency requirements and/or completion requirements (that is, that once the coprocessor operation has been completed, everything necessary for execution of the opcode has been done) on the sequences of operations performed by the Jazelle Extension hardware. The restrictions require cooperation and limit the design freedom for both the Jazelle acceleration and coprocessor designers.
To avoid the need for undefined exceptions, the following coprocessor interworking model for Jazelle Extension hardware applies.
Coprocessor Interworking
If while executing in Jazelle state, the Jazelle Extension hardware synthesizes a coprocessor instruction and passes it to a hardware coprocessor for execution, then it must be prepared for the coprocessor to reject the instruction. If a coprocessor rejects an instruction issued by Jazelle Extension hardware, the Jazelle Extension hardware and coprocessor must cooperate to: Prevent the Undefined Instruction exception that would occur if the coprocessor had rejected a coprocessor instruction in ARM state from occurring. Take suitable SUBARCHITECTURE DEFINED corrective action, probably involving exiting Jazelle state, and executing a suitable ARM code handler that contains further coprocessor instructions.
To ensure that this is a practical technique and does not result in inadequate or excessive handling of coprocessor instruction rejections, coprocessors designed for use with the Jazelle Extension must: When there is an exceptional condition generated by an earlier instruction, the coprocessor shall keep track of that exceptional condition and keep trying to cause an imprecise Undefined Instruction exception whenever an attempt is made to execute one of its coprocessor instructions until the exceptional condition is cleared by its Undefined Instruction handler. When it tries to cause a precise Undefined Instruction exception, for reasons to do with the coprocessor instruction it is currently being asked to execute, the coprocessor shall act in a memoryless way. That is, if it is subsequently asked to execute a different coprocessor instruction, it must ignore the instruction it first tried to reject precisely and instead determine whether the new instruction needs to be rejected precisely.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-61
Programmers Model
A2.10.5 Configuration and control
All registers associated with the Jazelle Extension are implemented in coprocessor space as part of coprocessor fourteen (CP14). The registers are accessed using the MCR (MCR on page A4-62) and MRC (MRC on page A4-70) instructions. The general instruction formats for Jazelle Extension control and configuration are as follows:
MCR{<cond>} p14, 7, <Rd>, CRn, CRm{, MRC{<cond>} p14, 7, <Rd>, CRn, CRm{, opcode_2}* opcode_2}*
*opcode_2 can be omitted if opcode_2 == 0 The following rules apply to the Jazelle Extension control and configuration registers: All SUBARCHITECTURE DEFINED configuration registers are accessed by coprocessor 14 MRC and MCR instructions with <opcode_1> set to 7. The values contained by configuration registers are only changed by the execution of MCR instructions, and in particular are not changed by Jazelle state execution of opcodes. The access policy for the required registers is fully defined in their descriptions. All MCR accesses to the Jazelle ID register, and MRC or MCR accesses which are restricted to privileged modes only are UNDEFINED if executed in User mode. The access policy of other configuration registers is SUBARCHITECTURE DEFINED. When a configuration register is readable, the result of reading it will be the last value written to it, with no side-effects. When a configuration register is not readable, the result of attempting to read it is UNPREDICTABLE. When a configuration register can be written, the effect must be idempotent. That is, the overall effect of writing the value more than once must not differ from the effect of writing it once.
A minimum of three registers are required in a non-trivial implementation. Additional registers may be provided and are SUBARCHITECTURE DEFINED.
Jazelle ID register
The Jazelle Identity register allows EJVMs to determine the architecture and subarchitecture under which they are running. This is a coprocessor 14 read-only register, accessed by the MRC instruction:
MRC{<cond>} p14, 7, <Rd>, c0, c0 {, 0} ;<Rd>:= Jazelle Identity register
The Jazelle ID register is normally accessible from both privileged and User modes. See Operating System (OS) control register on page A2-64 for User mode access restrictions.
A2-62
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
The format of the Jazelle Identity register is:
31 28 27 20 19 12 11 0
SUBARCHITECTURE DEFINED
Architecture
Implementor
Subarchitecture
Bits[31:28] Bits[27:20]
Contain an architecture code. This uses the same architecture code that appears in the Main ID register in coprocessor 15 Contain the implementor code of the designer of the subarchitecture. This uses the same implementor code that appears in the Main ID register in coprocessor 15, as documented in Main ID register on page B3-7. As a special case, if the trivial implementation of the Jazelle Extension is used, this implementor code is 0x00.
Bits[19:12]
Contain the subarchitecture code. The following subarchitecture code is defined: 0x00 = Jazelle V1 subarchitecture, or trivial implementation of Jazelle Extension if implementor code is 0x00.
Bits[11:0]
Contain further SUBARCHITECTURE DEFINED information.
Main configuration register
A Main Configuration register is added to control the Jazelle Extension. This is a coprocessor 14 register, accessed by MRC and MCR instructions as follows:
MRC{<cond>} MCR{<cond>} p14, 7, <Rd>, c2, c0 {, 0} p14, 7, <Rd>, c2, c0 {, 0} ; ; ; ; <Rd> := Main Configuration register Main Configuration register := <Rd>
This register is normally write-only from User mode. See Operating System (OS) control register on page A2-64 for additional User mode access restrictions. The format of the Main Configuration register is:
31
SUBARCHITECTURE DEFINED
10
JE
Bit[31:1] Bit[0]
SUBARCHITECTURE DEFINED
information.
The Jazelle Enable (JE) bit, which is cleared to 0 on reset. When the JE bit is 0, the Jazelle Extension is disabled and the BXJ instruction does not cause Jazelle state execution instead, BXJ behaves exactly as a BX instruction. See BXJ on page A4-21. When the JE bit is 1, the Jazelle Extension is enabled.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-63
Programmers Model
Operating System (OS) control register
The Jazelle OS Control register provides the operating system with process usage control of the Jazelle Extension. This is a coprocessor 14 register, accessed by MRC and MCR instructions as follows:
MRC{<cond>} MCR{<cond>} p14, 7, <Rd>, c1, c0 {, 0} p14, 7, <Rd>, c1, c0 {, 0} ; ; ; ; <Rd> := Jazelle OS Control register Jazelle OS Control register := <Rd>
This register can only be accessed from privileged modes; these instructions are UNDEFINED when executed in User mode. EJVMs will normally never access the Jazelle OS Control register, and EJVMs that are intended to run in User mode cannot do so. The purpose of the Jazelle OS Control register is primarily to allow operating systems to control access to the Jazelle Extension hardware in a subarchitecture-independent fashion. It is expected to be used in conjunction with the JE bit of the Main Configuration register. The format of the Jazelle OS Control register is:
31
RESERVED
2
10
(RAZ)
CC VD
Bits[31:2]
Reserved for future expansion. Prior to such expansion, they must read as zero. To maximize future compatibility, software should preserve their contents, using a read modify write method to update the other control bits. The Configuration Valid bit, which can be used by an operating system to signal to an EJVM that it needs to re-write its configuration to the configuration registers. When CV == 0, re-writing of the configuration registers is required before an opcode is next executed. When CV == 1, no re-writing of the configuration registers is required, other than re-writing that is certain to occur before an opcode is next executed. The Configuration Disabled bit, which can be used by an operating system to monitor and/or control User mode access to the configuration registers and the Jazelle Identity register. When CD == 0, MCR instructions that write to configuration registers and MRC instructions that read the Jazelle Identity register execute normally. When CD == 1, all of these instructions only behave normally when executed in a privileged mode, and are UNDEFINED when executed in User mode.
CV Bit[1]
CD Bit[0]
When the JE bit of the Main Configuration register is 0, the Jazelle OS Control register has no effect on how
BXJ instructions are executed. They always execute as a BX instruction.
When the JE bit of the Main Configuration register is 1, the CV bit affects BXJ instructions as follows: If CV == 1, the Jazelle Extension hardware configuration is considered enabled and valid, allowing the processor to enter Jazelle state and execute opcodes as described in Executing BXJ with Jazelle Extension enabled on page A2-56.
A2-64
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
If CV == 0, then in all of the IMPLEMENTATION DEFINED circumstances in which the Jazelle Extension hardware would have entered Jazelle state if CV had been 1, it instead enters a configuration invalid handler and sets CV to 1. A configuration invalid handler is a sequence of ARM instructions that includes MCR instructions to write the configuration required by the EJVM, ending with a BXJ instruction to re-attempt execution of the opcode concerned. The method by which the configuration invalid handlers address is determined and its entry and exit conditions are all SUBARCHITECTURE
DEFINED.
In circumstances in which the Jazelle Extension hardware would not have entered Jazelle state if CV had been 1, it is IMPLEMENTATION DEFINED whether the configuration invalid handler is entered as described in the last paragraph, or the BXJ instruction is treated as a BX instruction with possible SUBARCHITECTURE DEFINED restrictions. The intended use of the CV bit is that when a process swap occurs, the operating system sets CV to 0. The result is that before the new process can execute an opcode in the Jazelle Extension hardware, it must execute its configuration invalid handler. This ensures that the Jazelle Extension hardwares configuration registers are correctly for the EJVM concerned. The CV bit is set to 1 on entry to the configuration invalid handler, allowing the opcode to be executed in hardware when the invalid configuration handler re-attempts its execution.
Note
It may seem counterintuitive that the CV bit is set to 1 on entry to the configuration invalid handler, rather than after it has completed writing the configuration registers. This is correct, otherwise, the configuration invalid handler may partially configure the hardware before a process swap occurs, causing another EJVM-using process to write its configuration to the hardware. When the original process is resumed, CV will have been cleared (CV == 0) by the operating system. If the handler writes its configuration to the hardware and then sets CV to 1 in this example, the opcode will be executed with the hardware configured for a hybrid of the two configurations. By setting CV to 1 on entry to the configuration invalid handler, this means that CV is 0 when execution of the opcode is re-attempted, and the configuration invalid handler will execute again (and if necessary, recursively) until it finally completes execution without a process swap occurring. The CD bit has multiple possible uses for monitoring and controlling User mode access to the Jazelle Extension hardware. Among them are: By setting CD == 1 and JE == 0, an OS can prevent all User mode access to the Jazelle Extension hardware: any attempt to use the BXJ instruction will produce the same result as a BX instruction, and any attempt to configure the hardware (including setting the JE bit) will result in an Undefined Instruction exception. To provide User mode access to the Jazelle Extension hardware in a simple manner, while protecting EJVMs from conflicting use of the hardware by other processes, the OS should set CD == 0 and should preserve and restore the Main Configuration register on process swaps, initializing its value to 0 for new processes. In addition, it should set the CV bit to 0 on every process swap, to ensure that EJVMs reconfigure the Jazelle Extension hardware to match their requirements when necessary.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-65
Programmers Model
The technique described in the previous bullet point may result in large numbers of unnecessary reconfigurations of the Jazelle Extension hardware if only a few processes are using the hardware. This can be improved by the OS keeping track of which User mode processes are known to be using an EJVM. The OS should set CD == 1 and JE == 0 for any new processes or on a context switch to an existing process that is not using an EJVM. Any User mode instruction that attempts to access a configuration register will take an UNDEFINED exception. The Undefined Instruction handler can then identify the EJVM need, mark the process as using an EJVM, then return to retry the instruction with CD == 0. A further refinement is to clear the CV bit to 0 only if the context switch is to an EJVM-using process that is different from the last EVJM-using process which ran. This avoids redundant reconfiguration of the hardware. That is, the operating system maintains a process currently owning the Jazelle Extension hardware variable, that gets updated with a process_ID when swapping to an EJVM-using process. The context switch software sets CV to 0 if the process_ID update results in a change to the saved variable. Context switch software implementing the CV-bit scheme should also save and restore the Main Configuration register (in its entirety) on a process swap where the EJVM-using process changes. This ensures that the restored EJVM can use the JE bit reliably for its own purpose.
Note
This technique will not identify privileged EJVM-using processes. However, it is assumed that operating systems are aware of the needs of their privileged processes.
The OS can impose a single Jazelle Extension configuration on all User mode code by writing that configuration to the hardware, then setting CD == 1 and JE == 1.
The CV and CD bits are both set to 0 on reset. This ensures that subject to some conditions, an EJVM can operate correctly under an OS that does not support the Jazelle Extension. The main such condition is that a process swap never swaps between two EJVM-using processes that require different settings of the configuration registers. This would occur in either of the following two cases, for example: if there is only ever one EJVM-using process in the system. if all of the EJVM-using processes in the system use the same static settings of the configuration registers.
A2-66
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.10.6 EJVM operation
This section summarizes how EJVMs should operate in order to meet the architecture requirements.
Initialization
During initialization, the EJVM should first check which subarchitecture is present, using the implementor and subarchitecture codes in the value read from the Jazelle Identity register. If the EJVM is incompatible with the subarchitecture, it should either write a value with JE == 0 to the Main Configuration register, or (if unaccelerated opcode execution is unacceptable) generate an error. If the EJVM is compatible with the subarchitecture, it should write its desired configuration to the Main Configuration register and any other configuration registers. The EJVM should not skip this step on the assumption that the CV bit of the Jazelle OS Control register will be 0; an assumption that CV == 0 triggering the configuration invalid handler before any opcode is executed by the Jazelle Extension hardware should not be relied on.
Opcode execution
The EJVM should contain a handler for each opcode and for each exception condition specified by the subarchitecture it is designed for (the exception conditions always include configuration invalid). It should initiate opcode execution by executing a BXJ instruction with the register operand specifying the target address of the opcode handler for the first opcode of the program, and the process registers set up in accordance with the SUBARCHITECTURE DEFINED register usage model. The opcode handler performs the data-processing operations required by the opcode concerned, determines the address of the next opcode to be executed, determines the address of the handler for that opcode, and performs a BXJ to that handler address with the registers again set up to the SUBARCHITECTURE DEFINED register usage model. The register usage model on entry to exception condition handlers are SUBARCHITECTURE DEFINED, and may differ from the register usage model defined for BXJ instruction execution. The handlers then resolve the exception condition. For example, in the case of the configuration invalid handler, the handler rewrites the desired configuration to the Main Configuration register and any other configuration registers).
Further considerations
To ensure application execution and correct interaction with an operating system, EJVMs should only perform operations that are allowed in User mode. In particular, they should only ever read the Jazelle ID register, write to the configuration registers, and should not attempt to access the Jazelle OS Control register.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-67
Programmers Model
A2.10.7 Trivial implementations
This section summarizes what needs to be implemented in trivial implementations of the Jazelle Extension. Implement the Jazelle Identity register with the implementor and subarchitecture fields set to zero; the whole register may RAZ (read as zero). Implement the Main Configuration register to read as zero and ignore writes. Implement the Jazelle OS control register such that it can be read and written, but its effects are ignored. The register may be implemented as RAZ/DNM - read as zero, do not modify on writes. This allows operating systems supporting an EJVM to execute correctly. Implement the BXJ instruction to behave identically to the BX instruction in all circumstances, as implied by the fact that the JE bit is always zero. In particular, this means that Jazelle state will never be entered normally on a trivial implementation. In ARMv6, a trivial implementation can implement the J bit in the CPSR/SPSRs as RAZ/DNM; read as zero, do not modify on writes. This is allowed because there is no legitimate way to set the J bit and enter Jazelle state, hence any return routine that tries to do so is issuing an UNPREDICTABLE instruction. Otherwise, implement J bits in the CPSR and each SPSR, and ensure that they are read, written and copied correctly when exceptions are entered and when MSR, MRS and exception return instructions are executed. In all cases when J == 1 in the CPSR it is IMPLEMENTATION DEFINED whether the next instruction is fetched and, could result in a prefetch abort, or it is assumed to be UNDEFINED.
Note
The PC does not need to be extended to 32 bits in the trivial implementation, since the only way that bit[0] of the PC is visible in ARM or Thumb state is as a result of a processor exception occurring during Jazelle state execution, and Jazelle state execution does not occur on a trivial implementation.
A2-68
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Programmers Model
A2.11 Saturated integer arithmetic
When viewed as a signed number, the value of a general-purpose register lies in the range from 231 (or 0x80000000) to +231 1 (or 0x7FFFFFFF). If an addition or subtraction is performed on such numbers and the correct mathematical result lies outside this range, it would require more than 32 bits to represent. In these circumstances, the surplus bits are normally discarded, which has the effect that the result obtained is equal to the correct mathematical result reduced modulo 232. For example, 0x60000000 could be used to represent +3 229 as a signed integer. If you add this number to itself, you get +3 230, which lies outside the representable range, but could be represented as the 33-bit signed number 0x0C0000000. The actual result obtained will be the right-most 32 bits of this, which are 0xC0000000. This represents 230, which is smaller than the correct mathematical result by 232, and does not even have the same sign as the correct result. This kind of inaccuracy is unacceptable in many DSP applications. For example, if it occurred while processing an audio signal, the abrupt change of sign would be likely to result in a loud click. To avoid this sort of effect, many DSP algorithms use saturated signed arithmetic. This modifies the way normal integer arithmetic behaves as follows: If the correct mathematical result lies within the available range from 231 to +231 1, the result of the operation is equal to the correct mathematical result. If the correct mathematical result is greater than +231 1 and so overflows the upper end of the representable range, the result of the operation is equal to +231 1. If the correct mathematical result is less than 231 and so overflows the lower end of the representable range, the result of the operation is equal to 231.
Put another way, the result of a saturated arithmetic operation is the closest representable number to the correct mathematical result of the operation. Instructions that support saturated signed 32-bit integer additions and subtractions (Q prefix), use the QADD and QSUB instructions. Variants of these instructions (QDADD and QDSUB) perform a saturated doubling of one of the operands before the saturated addition or subtraction. Saturated integer multiplications are not supported, because the product of two values of widths A and B bits never overflows an (A+B)-bit destination.
A2.11.1
Saturated Q15 and Q31 arithmetic
A 32-bit signed value can be treated as having a binary point immediately after its sign bit. This is equivalent to dividing its signed integer value by 231, so that it can now represent numbers from 1 to +1 231. When a 32-bit value is used to represent a fractional number in this fashion, it is known as a Q31 number. Saturated additions, subtractions, and doublings can be performed on Q31 numbers using the same instructions as are used for saturated integer arithmetic, since everything is simply scaled down by a factor of 231.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A2-69
Programmers Model
Similarly, a 16-bit value can be treated as having a binary point immediately after its sign bit, which effectively divides its signed integer value by 215. When a 16-bit value is used in this fashion, it can represent numbers from 1 to +1 215 and is known as a Q15 number. If two Q15 numbers are multiplied together as integers, the resulting integer needs to be scaled down by a factor of 215 215 == 230. For example, multiplying the Q15 number 0x8000 (representing 1) by itself using an integer multiplication instruction yields the value 0x40000000, which is 230 times the desired result of +1. This means that the result of the integer multiplication instruction is not quite in Q31 form. To get it into Q31 form, it must be doubled, so that the required scaling factor becomes 231. Furthermore, it is possible that the doubling will cause integer overflow, so the result should in fact be doubled with saturation. In particular, the result 0x40000000 from the multiplication of 0x8000 by itself should be doubled with saturation to produce 0x7FFFFFFF (the closest possible Q31 number to the correct mathematical result of 1 1 == +1). If it were doubled without saturation, it would instead produce 0x80000000, which is the Q31 representation of 1. To implement a saturated Q15 Q15 Q31 multiplication, therefore, an integer multiply instruction should be followed by a saturated integer doubling. The latter can be performed by a QADD instruction adding the multiply result to itself. Similarly, a saturated Q15 Q15 + Q31 Q31 multiply-accumulate can be performed using an integer multiply instruction followed by the use of a QDADD instruction. Some other examples of arithmetic on Q15 and Q31 numbers are described in the Usage sections for the individual instructions.
A2-70
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Chapter A3 The ARM Instruction Set
This chapter describes the ARM instruction set and contains the following sections: Instruction set encoding on page A3-2 The condition field on page A3-3 Branch instructions on page A3-5 Data-processing instructions on page A3-7 Multiply instructions on page A3-10 Parallel addition and subtraction instructions on page A3-14 Extend instructions on page A3-16 Miscellaneous arithmetic instructions on page A3-17 Other miscellaneous instructions on page A3-18 Status register access instructions on page A3-19 Load and store instructions on page A3-21 Load and Store Multiple instructions on page A3-26 Semaphore instructions on page A3-28 Exception-generating instructions on page A3-29 Coprocessor instructions on page A3-30 Extending the instruction set on page A3-32.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-1
The ARM Instruction Set
A3.1
Instruction set encoding
Figure A3-1 shows the ARM instruction set encoding. All other bit patterns are UNPREDICTABLE or UNDEFINED. See Extending the instruction set on page A3-32 for a description of the cases where instructions are UNDEFINED. An entry in square brackets, for example [1], indicates that more information is given after the figure.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data processing immediate shift Miscellaneous instructions: See Figure A3-4 Data processing register shift [2] Miscellaneous instructions: See Figure A3-4 Multiplies: See Figure A3-3 Extra load/stores: See Figure A3-5 Data processing immediate [2] Undefined instruction Move immediate to status register Load/store immediate offset Load/store register offset Media instructions [4]: See Figure A3-2 Architecturally undefined Load/store multiple Branch and branch with link Coprocessor load/store and double register transfers Coprocessor data processing Coprocessor register transfers Software interrupt Unconditional instructions: See Figure A3-6
cond [1] cond [1] cond [1] cond [1] cond [1] cond [1] cond [1] cond [1] cond [1] cond [1] cond [1] cond [1] cond [1] cond [1] cond [3] cond [3] cond [3] cond [1]
000
opcode
S
Rn
Rd
shift amount
shift
0
Rm xxxx Rm xxxx xxxx
00010 xx0 000 opcode S
xxxxxxxxxxxxxxx0 Rn Rd Rs 0 shift 1
00010 xx0 000xx 001 xxx S
xxxxxxxxxxxx0xx1 xxxxxxxxxxxx1xx1 Rn Rd rotate
opcode
immediate xxxx
00110x00 00110R10 0 1 0 PU BWL 0 1 1 PU BWL 011xx
xxxxxxxxxxxxxxxx Mask Rn Rn SBO Rd Rd rotate
immediate immediate
shift amount
shift
0
Rm
xxxxxxxxxxxxxxxxxx1xxxx xxxxxxxx Rn 24-bit offset Rn CRn CRn CRd CRd Rd cp_num cp_num cp_num 8-bit offset opcode2 0 opcode2 1 CRm CRm x xxx1111xxxx register list
01111111 1 0 0 PU SW L 101L 1 1 0 PUNWL 1110 opcode1
1 1 1 0 opcode1 L 1111
swi number xxxxxxxxxxxxxxxxxxxxxxx
1111xxxxx
1. 2. 3. 4.
Figure A3-1 ARM instruction set summary The cond field is not allowed to be 1111 in this line. Other lines deal with the cases where bits[31:28] of the instruction are 1111. If the opcode field is of the form 10xx and the S field is 0, one of the following lines applies instead. If the cond field is 1111, this instruction is UNPREDICTABLE prior to ARMv5. The architecturally Undefined instruction uses a small number of these instruction encodings.
A3-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.2
The condition field
Most ARM instructions can be conditionally executed, which means that they only have their normal effect on the programmers model state, memory and coprocessors if the N, Z, C and V flags in the CPSR satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP: that is, execution advances to the next instruction as normal, including any relevant checks for interrupts and Prefetch Aborts, but has no other effect. Prior to ARMv5, all ARM instructions could be conditionally executed. A few instructions have been introduced subsequently which can only be executed unconditionally. See Unconditional instruction extension space on page A3-41 for details. Every instruction contains a 4-bit condition code field in bits 31 to 28:
31 28 27 0
cond
This field contains one of the 16 values described in Table A3-1 on page A3-4. Most instruction mnemonics can be extended with the letters defined in the mnemonic extension field. If the always (AL) condition is specified, the instruction is executed irrespective of the value of the condition code flags. The absence of a condition code on an instruction mnemonic implies the AL condition code.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-3
The ARM Instruction Set
A3.2.1
Condition code 0b1111
If the condition field is 0b1111, the behavior depends on the architecture version: In ARMv4, any instruction with a condition field of 0b1111 is UNPREDICTABLE. In ARMv5 and above, a condition field of 0b1111 is used to encode various additional instructions which can only be executed unconditionally (see Unconditional instruction extension space on page A3-41). All instruction encoding diagrams which show bits[31:28] as cond only match instructions in which these bits are not equal to 0b1111. Table A3-1 Condition codes
Opcode [31:28] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
Mnemonic extension EQ NE CS/HS CC/LO MI PL VS VC HI LS GE
Meaning Equal Not equal Carry set/unsigned higher or same Carry clear/unsigned lower Minus/negative Plus/positive or zero Overflow No overflow Unsigned higher Unsigned lower or same Signed greater than or equal
Condition flag state Z set Z clear C set C clear N set N clear V set V clear C set and Z clear C clear or Z set N set and V set, or N clear and V clear (N == V) N set and V clear, or N clear and V set (N != V) Z clear, and either N set and V set, or N clear and V clear (Z == 0,N == V) Z set, or N set and V clear, or N clear and V set (Z == 1 or N != V) -
1011
LT
Signed less than
1100 1101
GT LE
Signed greater than Signed less than or equal
1110 1111
AL -
Always (unconditional) See Condition code 0b1111
A3-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.3
Branch instructions
All ARM processors support a branch instruction that allows a conditional branch forwards or backwards up to 32MB. As the PC is one of the general-purpose registers (R15), a branch or jump can also be generated by writing a value to R15. A subroutine call can be performed by a variant of the standard branch instruction. As well as allowing a branch forward or backward up to 32MB, the Branch with Link (BL) instruction preserves the address of the instruction after the branch (the return address) in the LR (R14). In T variants of ARMv4 and above, the Branch and Exchange (BX) instruction copies the contents of a general-purpose register Rm to the PC (like a MOV PC,Rm instruction), with the additional functionality that if bit[0] of the transferred value is 1, the processor shifts to Thumb state. Together with the corresponding Thumb instructions, this allows interworking branches between ARM and Thumb code. Interworking subroutine calls can be generated by combining BX with an instruction to write a suitable return address to the LR, such as an immediately preceding MOV LR,PC instruction. In ARMv5 and above, there are also two types of Branch with Link and Exchange (BLX) instruction: One type takes a register operand Rm, like a BX instruction. This instruction behaves like a BX instruction, and additionally writes the address of the next instruction into the LR. This provides a more efficient interworking subroutine call than a sequence of MOV LR,PC followed by BX Rm. The other type behaves like a BL instruction, branching backwards or forwards by up to 32MB and writing a return link to the LR, but shifts to Thumb state rather than staying in ARM state as BL does. This provides a more efficient alternative to loading the subroutine address into Rm followed by a BLX Rm instruction when it is known that a Thumb subroutine is being called and that the subroutine lies within the 32MB range.
A load instruction provides a way to branch anywhere in the 4GB address space (known as a long branch). A 32-bit value is loaded directly from memory into the PC, causing a branch. A long branch can be preceded by MOV LR,PC or another instruction that writes the LR to generate a long subroutine call. In ARMv5 and above, bit[0] of the value loaded by a long branch controls whether the subroutine is executed in ARM state or Thumb state, just like bit[0] of the value moved to the PC by a BX instruction. Prior to ARMv5, bits[1:0] of the value loaded into the PC are ignored, and a load into the PC can only be used to call a subroutine in ARM state. In non-T variants of ARMv5, the instructions described above can cause an entry into Thumb state despite the fact that the Thumb instruction set is not present. This causes the instruction at the branch target to enter the Undefined Instruction exception. See The interrupt disable bits on page A2-14 for more details. In ARMv6 and above, and in J variants of ARMv5, there is an additional Branch and Exchange Jazelle instruction, see BXJ on page A4-21.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-5
The ARM Instruction Set
A3.3.1
Examples
B BCC BEQ MOV BL label label label PC, #0 func ; branch unconditionally to label ; branch to label if carry flag is clear ; branch to label if zero flag is set ; R15 = 0, branch to location zero ; subroutine call to function
func . . MOV MOV LDR
PC, LR LR, PC PC, =func
; ; ; ;
R15=R14, return to instruction after the BL store the address of the instruction after the next one into R14 ready to return load a 32-bit value into the program counter
A3.3.2
List of branch instructions
B, BL BLX BX BXJ
Branch, and Branch with Link. See B, BL on page A4-10. Branch with Link and Exchange. See BLX (1) on page A4-16 and BLX (2) on page A4-18. Branch and Exchange Instruction Set. See BX on page A4-20. Branch and change to Jazelle state. See BXJ on page A4-21.
A3-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.4
Data-processing instructions
ARM has 16 data-processing instructions, shown in Table A3-2. Table A3-2 Data-processing instructions
Opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Mnemonic AND EOR SUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN
Operation Logical AND Logical Exclusive OR Subtract Reverse Subtract Add Add with Carry Subtract with Carry Reverse Subtract with Carry Test Test Equivalence Compare Compare Negated Logical (inclusive) OR Move Bit Clear Move Not
Action Rd := Rn AND shifter_operand Rd := Rn EOR shifter_operand Rd := Rn - shifter_operand Rd := shifter_operand - Rn Rd := Rn + shifter_operand Rd := Rn + shifter_operand + Carry Flag Rd := Rn - shifter_operand - NOT(Carry Flag) Rd := shifter_operand - Rn - NOT(Carry Flag) Update flags after Rn AND shifter_operand Update flags after Rn EOR shifter_operand Update flags after Rn - shifter_operand Update flags after Rn + shifter_operand Rd := Rn OR shifter_operand Rd := shifter_operand (no first operand) Rd := Rn AND NOT(shifter_operand) Rd := NOT shifter_operand (no first operand)
Most data-processing instructions take two source operands, though Move and Move Not take only one. The compare and test instructions only update the condition flags. Other data-processing instructions store a result to a register and optionally update the condition flags as well. Of the two source operands, one is always a register. The other is called a shifter operand and is either an immediate value or a register. If the second operand is a register value, it can have a shift applied to it.
CMP, CMN, TST and TEQ always update the condition code flags. The assembler automatically sets the S bit in the instruction for them, and the corresponding instruction with the S bit clear is not a data-processing instruction, but instead lies in one of the instruction extension spaces (see Extending the instruction set on page A3-32). The remaining instructions update the flags if an S is appended to the instruction mnemonic (which sets the S bit in the instruction). See The condition code flags on page A2-11 for more details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-7
The ARM Instruction Set
A3.4.1
Instruction encoding
<opcode1>{<cond>}{S} <Rd>, <shifter_operand> <opcode1> := MOV | MVN <opcode2>{<cond>} <Rn>, <shifter_operand> <opcode2> := CMP | CMN | TST | TEQ <opcode3>{<cond>}{S} <Rd>, <Rn>, <shifter_operand> <opcode3> := ADD | SUB | RSB | ADC | SBC | RSC | AND | BIC | EOR | ORR
31
28 27 26 25 24
21 20 19
16 15
12 11
0
cond
00I
opcode
S
Rn
Rd
shifter_operand
I bit S bit Rn Rd shifter_operand
Distinguishes between the immediate and register forms of <shifter_operand>. Signifies that the instruction updates the condition codes. Specifies the first source operand register. Specifies the destination register. Specifies the second source operand. See Addressing Mode 1 - Data-processing operands on page A5-2 for details of the shifter operands.
A3-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.4.2
List of data-processing instructions
ADC ADD AND BIC CMN CMP EOR MOV MVN ORR RSB RSC SBC SUB TEQ TST
Add with Carry. See ADC on page A4-4. Add. See ADD on page A4-6. Logical AND. See AND on page A4-8. Logical Bit Clear. See BIC on page A4-12. Compare Negative. See CMN on page A4-26. Compare. See CMP on page A4-28. Logical EOR. See EOR on page A4-32. Move. See MOV on page A4-68. Move Not. See MVN on page A4-82. Logical OR. See ORR on page A4-84. Reverse Subtract. See RSB on page A4-115. Reverse Subtract with Carry. See RSC on page A4-117. Subtract with Carry. See SBC on page A4-125. Subtract. See SUB on page A4-208. Test Equivalence. See TEQ on page A4-228. Test. See TST on page A4-230.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-9
The ARM Instruction Set
A3.5
Multiply instructions
ARM has several classes of Multiply instruction: Normal Long Halfword Word halfword Most significant word 32-bit x 32-bit, top 32-bit result Dual halfword dual 16-bit x 16-bit, 32-bit result. 32-bit x 32-bit, bottom 32-bit result 32-bit x 32-bit, 64-bit result 16-bit x 16-bit, 32-bit result 32-bit x 16-bit, top 32-bit result
All Multiply instructions take two register operands as the input to the multiplier. The ARM processor does not directly support a multiply-by-constant instruction because of the efficiency of shift and add, or shift and reverse subtract instructions.
A3.5.1
Normal multiply
There are two 32-bit x 32-bit Multiply instructions that produce bottom 32-bit results: MUL Multiplies the values of two registers together, truncates the result to 32 bits, and stores the result in a third register. MLA Multiplies the values of two registers together, adds the value of a third register, truncates the result to 32 bits, and stores the result in a fourth register. This can be used to perform multiply-accumulate operations. Both Normal Multiply instructions can optionally set the N (Negative) and Z (Zero) condition code flags. No distinction is made between signed and unsigned variants. Only the least significant 32 bits of the result are stored in the destination register, and the sign of the operands does not affect this value.
A3.5.2
Long multiply
There are five 32-bit x 32-bit Multiply instructions that produce 64-bit results. Two of the variants multiply the values of two registers together and store the 64-bit result in third and fourth registers. There are signed (SMULL) and unsigned (UMULL) variants. The signed variants produce a different result in the most significant 32 bits if either or both of the source operands is negative. Two variants multiply the values of two registers together, add the 64-bit value from the third and fourth registers, and store the 64-bit result back into those registers (third and fourth). There are signed (SMLAL) and unsigned (UMLAL) variants. These instructions perform a long multiply and accumulate.
UMAAL multiplies the unsigned values of two registers together, adds the two unsigned 32-bit values from the
third and fourth registers, and stores the 64-bit unsigned result back into those registers (third and fourth).
A3-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
All the Long Multiply instructions except UMAAL can optionally set the N (Negative) and Z (Zero) condition code flags. UMAAL does not affect any flags.
UMAAL is available in ARMv6 and above.
A3.5.3
Halfword multiply
There are three signed 16-bit x 16-bit Multiply instructions that produce 32-bit results:
SMULxy
Multiplies the 16-bit values of two half-registers together, and stores the signed 32-bit result in a third register. Multiplies the 16-bit values of two half-registers together, adds the 32-bit value from a third register, and stores the signed 32-bit result in a fourth register. Multiplies the 16-bit values of two half-registers together, adds the 64-bit value from a third and fourth register, and stores the 64-bit result back into those registers (third and fourth).
SMLAxy
SMLALxy
SMULxy and SMLALxy do not affect any flags. SMLAxy can set the Q flag if overflow occurs in the multiplication. The x and y designators indicate whether the top (T) or bottom (B) bits of the register is used as the operand.
They are available in ARMv5TE and above.
A3.5.4
Word halfword multiply
There are two signed Multiply instructions that produce top 32-bit results:
SMULWy
Multiplies the 32-bit value of one register with the 16-bit value of either halfword of a second register, and stores the top 32 bits of the signed 48-bit result in a third register. Multiplies the 32-bit value of one register with the 16-bit value of either halfword of a second register, extracts the top 32 bits, adds the 32-bit value from a third register, and stores the signed 32-bit result in a fourth register.
SMLAWy
SMLAWy sets the Q flag if overflow occurs in the multiplication. SMULWy does not affect any flags.
These instructions are available in ARMv5TE and above.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-11
The ARM Instruction Set
A3.5.5
Most significant word multiply
There are three signed 32-bit x 32-bit Multiply instructions that produce top 32-bit results:
SMMUL
Multiplies the 32-bit values of two registers together, and stores the top 32 bits of the signed 64-bit result in a third register. Multiplies the 32-bit values of two registers together, extracts the top 32 bits, adds the 32-bit value from a third register, and stores the signed 32-bit result in a fourth register. Multiplies the 32-bit value of two registers together, extracts the top 32 bits, subtracts this from a 32-bit value from a third register, and stores the signed 32-bit result in a fourth register.
SMMLA
SMMLS
These instructions do not affect any flags. They are available in ARMv6 and above.
A3.5.6
Dual halfword multiply
There are six dual, signed 16-bit x 16-bit Multiply instructions:
SMUAD
Multiplies the values of the top halfwords of two registers together, multiplies the values of the bottom halfwords of the same two registers together, adds the products, and stores the 32-bit result in a third register. Multiplies the values of the top halfwords of two registers together, multiplies the values of the bottom halfwords of the same two registers together, subtracts one product from the other, and stores the 32-bit result in a third register. Multiplies the 32-bit value of two registers together, extracts the top 32 bits, subtracts this from a 32-bit value from a third register, and stores the signed 32-bit result in a fourth register. Multiplies the 32-bit values of two registers together, extracts the top 32 bits, adds the 32-bit value from a third register, and stores the signed 32-bit result in a fourth register. Multiplies the 32-bit value of two registers together, extracts the top 32 bits, subtracts this from a 32-bit value from a third register, and stores the signed 32-bit result in a fourth register. Multiplies the 32-bit value of two registers together, extracts the top 32 bits, subtracts this from a 32-bit value from a third register, and stores the signed 32-bit result in a fourth register.
SMUSD
SMLAD
SMLSD
SMLALD
SMLSLD
SMUAD, SMLAD, and SMLSLD can set the Q flag if overflow occurs in the operation. All other instructions do not affect any flags.
They are available in ARMv6 and above.
A3-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.5.7
Examples
MUL MULS MLA SMULL UMULL UMLAL R4, R4, R7, R4, R2, R2, R8, R8, R1 R1 R9, R3 R2, R3 ; ; ; ; ; ; ; Set R4 to value of R2 multiplied by R1 R4 = R2 x R1, set N and Z flags R7 = R8 x R9 + R3 R4 = bits 0 to 31 of R2 x R3 R8 = bits 32 to 63 of R2 x R3 R8, R6 = R0 x R1 R8, R5 = R0 x R1 + R8, R5
R6, R8, R0, R1 R5, R8, R0, R1
A3.5.8
List of multiply instructions
MLA MUL SMLA<x><y> SMLAD SMLAL SMLAL<x><y> SMLALD SMLAW<y> SMLSD SMLSLD SMMLA SMMLS SMMUL SMUAD SMUL<x><y> SMULL SMULW<y> SMUSD UMAAL UMLAL UMULL
Multiply Accumulate. See MLA on page A4-66. Multiply. See MUL on page A4-80. Signed halfword Multiply Accumulate. See SMLA<x><y> on page A4-141. Signed halfword Multiply Accumulate, Dual. See SMLAD on page A4-144. Signed Multiply Accumulate Long. See SMLAL on page A4-146. Signed halfword Multiply Accumulate Long. See SMLAL<x><y> on page A4-148. Signed halfword Multiply Accumulate Long, Dual. See SMLALD on page A4-150. Signed halfword by word Multiply Accumulate. See SMLAW<y> on page A4-152. Signed halfword Multiply Subtract, Dual. See SMLAD on page A4-144. Signed halfword Multiply Subtract Long Dual. See SMLALD on page A4-150. Signed Most significant word Multiply Accumulate. See SMMLA on page A4-158. Signed Most significant word Multiply Subtract. See SMMLA on page A4-158. Signed Most significant word Multiply. See SMMUL on page A4-162. Signed halfword Multiply, Add, Dual. See SMUAD on page A4-164. Signed halfword Multiply. See SMUL<x><y> on page A4-166. Signed Multiply Long. See SMULL on page A4-168. Signed halfword by word Multiply. See SMULW<y> on page A4-170. Signed halfword Multiply, Subtract, Dual. See SMUSD on page A4-172. Unsigned Multiply Accumulate significant Long. See UMAAL on page A4-247. Unsigned Multiply Accumulate Long. See UMLAL on page A4-249. Unsigned Multiply Long. See UMULL on page A4-251.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-13
The ARM Instruction Set
A3.6
Parallel addition and subtraction instructions
In addition to the normal data-processing and multiply instructions, ARMv6 introduces a set of parallel addition and subtraction instructions. There are six basic instructions:
ADD16
Adds the top halfwords of two registers to form the top halfword of the result. Adds the bottom halfwords of the same two registers to form the bottom halfword of the result.
ADDSUBX
Does the following: 1. Exchanges halfwords of the second operand register. 2. Adds top halfwords and subtracts bottom halfwords. Does the following: 1. Exchanges halfwords of the second operand register. 2. Subtracts top halfwords and adds bottom halfwords. Subtracts the top halfword of the first operand register from the top halfword of the second operand register to form the top halfword of the result. Subtracts the bottom halfword of the second operand registers from the bottom halfword of the first operand register to form the bottom halfword of the result.
SUBADDX
SUB16
ADD8
Adds each byte of the second operand register to the corresponding byte of the first operand register to form the corresponding byte of the result. Subtracts each byte of the second operand register from the corresponding byte of the first operand register to form the corresponding byte of the result.
SUB8
Each of the six instructions is available in the following variations, indicated by the prefixes shown:
S
Signed arithmetic modulo 28 or 216. Sets the CPSR GE bits (see The GE[3:0] bits on page A2-13). Signed saturating arithmetic. Signed arithmetic, halving the results to avoid overflow. Unsigned arithmetic modulo 28 or 216. Sets the CPSR GE bits (see The GE[3:0] bits on page A2-13). Unsigned saturating arithmetic. Unsigned arithmetic, halving the results to avoid overflow.
Q SH U
UQ UH
A3-14
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.6.1
List of parallel arithmetic instructions
QADD16 QADD8 QADDSUBX QSUB16 QSUB8 QSUBADDX SADD16 SADD8 SADDSUBX SSUB16 SSUB8 SSUBADDX SHADD16 SHADD8 SHADDSUBX SHSUB16 SHSUB8 SHSUBADDX UADD16 UADD8 UADDSUBX USUB16 USUB8 USUBADDX UHADD16 UHADD8 UHADDSUBX UHSUB16 UHSUB8 UHSUBADDX UQADD16 UQADD8 UQADDSUBX UQSUB16 UQSUB8 UQSUBADDX
Dual 16-bit signed saturating addition. See QADD16 on page A4-94. Quad 8-bit signed saturating addition. See QADD8 on page A4-95. 16-bit exchange, signed saturating addition, subtraction. See QADDSUBX on page A4-97. Dual 16-bit signed saturating subtraction. See QSUB16 on page A4-104. Quad 8-bit signed saturating subtraction. See QSUB8 on page A4-105. 16-bit exchange, signed saturating subtraction, addition. See QSUBADDX on page A4-107. Dual 16-bit signed addition. See SADD16 on page A4-119. Quad 8-bit signed addition. See SADD8 on page A4-121. 16-bit exchange, signed addition, subtraction. See SADDSUBX on page A4-123. Dual 16-bit signed subtraction. See SSUB16 on page A4-180. Quad 8-bit signed subtraction. See SSUB8 on page A4-182. 16-bit exchange, signed subtraction, addition. See SSUBADDX on page A4-184. Dual 16-bit signed half addition. See SHADD16 on page A4-130. Quad 8-bit signed half addition. See SHADD8 on page A4-131. 16-bit exchange, signed half addition, subtraction. See SHADDSUBX on page A4-133. Dual 16-bit signed half subtraction. See SHSUB16 on page A4-135. Quad 8-bit signed half subtraction. See SHSUB8 on page A4-137. 16-bit exchange, signed half subtraction, addition. See SHSUBADDX on page A4-139. Dual 16-bit unsigned addition. See UADD16 on page A4-232. Quad 8-bit unsigned addition. See UADD8 on page A4-233. 16-bit exchange, unsigned addition, subtraction. See UADDSUBX on page A4-235. Dual 16-bit unsigned subtraction. See USUB16 on page A4-269. Quad 8-bit unsigned subtraction. See USUB8 on page A4-270. 16-bit exchange, unsigned subtraction, addition. See USUBADDX on page A4-272. Dual 16-bit unsigned half addition. See UHADD16 on page A4-237. Quad 8-bit unsigned half addition. See UHADD8 on page A4-238. 16-bit exchange, unsigned half addition, subtraction. See UHADDSUBX on page A4-240. Dual 16-bit unsigned half subtraction. See UHSUB16 on page A4-242. Quad 8-bit unsigned half subtraction. See UHSUB16 on page A4-242. 16-bit exchange, unsigned half subtraction, addition. See UHSUBADDX on page A4-245. Dual 16-bit unsigned saturating addition. See UQADD16 on page A4-253. Quad 8-bit unsigned saturating addition. See UQADD8 on page A4-254. 16-bit exchange, unsigned saturating addition, subtraction. See UQADDSUBX on page A4-255. Dual 16-bit unsigned saturating subtraction. See UQSUB16 on page A4-257. Quad 8-bit unsigned saturating subtraction. See UQSUB8 on page A4-258. 16-bit exchange, unsigned saturating subtraction, addition. See UQSUBADDX on page A4-259.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-15
The ARM Instruction Set
A3.7
Extend instructions
ARMv6 and above provide several instructions for unpacking data by sign or zero extending bytes to halfwords or words, and halfwords to words. You can optionally add the result to the contents of another register. You can rotate the operand register by any multiple of 8 bits before extending. There are six basic instructions:
XTAB16
Extend bits[23:16] and bits[7:0] of one register to 16 bits, and add corresponding halfwords to the values in another register. Extend bits[7:0] of one register to 32 bits, and add to the value in another register. Extend bits[15:0] of one register to 32 bits, and add to the value in another register. Extend bits[23:16] and bits[7:0] to 16 bits each. Extend bits[7:0] to 32 bits. Extend bits[15:0] to 32 bits.
XTAB XTAH XTB16 XTB XTH
Each of the six instructions is available in the following variations, indicated by the prefixes shown:
S U
Sign extension, with or without addition modulo 216 or 232. Zero (unsigned) extension, with or without addition modulo 216 or 232.
A3.7.1
List of sign/zero extend and add instructions
SXTAB16 SXTAB SXTAH SXTB16 SXTB SXTH UXTAB16 UXTAB UXTAH UXTB16 UXTB UXTH
Sign extend bytes to halfwords, add halfwords. See SXTAB16 on page A4-218. Sign extend byte to word, add. See SXTAB on page A4-216. Sign extend halfword to word, add. See SXTAH on page A4-220. Sign extend bytes to halfwords. See SXTB16 on page A4-224. Sign extend byte to word. See SXTB on page A4-222. Sign extend halfword to word. See SXTH on page A4-226. Zero extend bytes to halfwords, add halfwords. See UXTAB16 on page A4-276. Zero extend byte to word, add. See UXTAB on page A4-274. Zero extend halfword to word, add. See UXTAH on page A4-278. Zero extend bytes to halfwords. See UXTB16 on page A4-282. Zero extend byte to word. See UXTB on page A4-280. Zero extend halfword to word. See UXTH on page A4-284.
A3-16
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.8
Miscellaneous arithmetic instructions
ARMv5 and above include several miscellaneous arithmetic instructions.
A3.8.1
Count leading zeros
ARMv5 and above include a Count Leading Zeros (CLZ) instruction. This instruction returns the number of 0 bits at the most significant end of its operand before the first 1 bit is encountered (or 32 if its operand is 0). Two typical applications for this are: To determine how many bits the operand should be shifted left to normalize it, so that its most significant bit is 1. (This can be used in integer division routines.) To locate the highest priority bit in a bit mask.
For details see CLZ on page A4-25.
A3.8.2
Unsigned sum of absolute differences
ARMv6 introduces an Unsigned Sum of Absolute Differences (USAD8) instruction, and an Unsigned Sum of Absolute Differences and Accumulate (USADA8) instruction. These instructions do the following: 1. Take corresponding bytes from two registers. 2. Find the absolute differences between the unsigned values of each pair of bytes. 3. Sum the four absolute values. 4. Optionally, accumulate the sum of the absolute differences with the value in a third register. For details see USAD8 on page A4-261 and USADA8 on page A4-263.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-17
The ARM Instruction Set
A3.9
Other miscellaneous instructions
ARMv6 and above provide several other miscellaneous instructions:
PKHBT
(Pack Halfword Bottom Top) combines the bottom, least significant, halfword of its first operand with the top (most significant) halfword of its shifted second operand. The shift is a left shift, by any amount from 0 to 31. See PKHBT on page A4-86.
PKHTB
(Pack Halfword Top Bottom) combines the top, most significant, halfword of its first operand with the bottom (least significant) halfword of its shifted second operand. The shift is an arithmetic right shift, by any amount from 1 to 32. See PKHTB on page A4-88.
REV
(Byte-Reverse Word) reverses the byte order in a 32-bit register. See REV on page A4-109.
REV16
(Byte-Reverse Packed Halfword) reverses the byte order in each 16-bit halfword of a 32-bit register. See REV16 on page A4-110.
REVSH
(Byte-Reverse Signed Halfword) reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign extends the result to 32-bits. See REVSH on page A4-111.
SEL
(Select) selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. The GE flags record the results of parallel additions or subtractions, see Parallel addition and subtraction instructions on page A3-14. See SEL on page A4-127.
SSAT
(Signed Saturate) saturates a signed value to a signed range. You can choose the bit position at which saturation occurs. You can apply a shift to the value before the saturation occurs. See SSAT on page A4-176.
SSAT16
Saturates two 16-bit signed values to a signed range. You can choose the bit position at which saturation occurs. See SSAT16 on page A4-178.
USAT
(Unsigned Saturate) saturates a signed value to an unsigned range. You can choose the bit position at which saturation occurs. You can apply a shift to the value before the saturation occurs. See USAT on page A4-265.
USAT16
Saturates two signed 16-bit values to an unsigned range. You can choose the bit position at which saturation occurs. See USAT16 on page A4-267.
A3-18
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.10 Status register access instructions
There are two instructions for moving the contents of a program status register to or from a general-purpose register. Both the CPSR and SPSR can be accessed. In addition, in ARMv6, there are several instructions that can write directly to specific bits, or groups of bits, in the CPSR. Each status register is traditionally split into four 8-bit fields that can be individually written: Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0] The flags field. The status field. The extension field. The control field.
From ARMv6, the ARM architecture uses the status and extension fields. The usage model of the bit fields no longer reflects the byte-wide definitions. The revised categories are defined in Types of PSR bits on page A2-11.
A3.10.1 CPSR value
Altering the value of the CPSR has five uses: sets the value of the condition code flags (and of the Q flag when it exists) to a known value enables or disable interrupts changes processor mode (for instance, to initialize stack pointers) changes the endianness of load and store operations changes the processor state (J and T bits).
Note
The T and J bits must not be changed directly by writing to the CPSR, but only via the BX, BLX, or BXJ instructions, and in the implicit SPSR to CPSR moves in instructions designed for exception return. Attempts to enter or leave Thumb or Jazelle state by directly altering the T or J bits have UNPREDICTABLE consequences.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-19
The ARM Instruction Set
A3.10.2 Examples
These examples assume that the ARM processor is already in a privileged mode. If the ARM processor starts in User mode, only the flag update has any effect.
MRS BIC MSR R0, CPSR R0, R0, #0xF0000000 CPSR_f, R0 ; ; ; ; ; ; ; ; ; ; ; ; ; Read the CPSR Clear the N, Z, C and V bits Update the flag bits in the CPSR N, Z, C and V flags now all clear Read the CPSR Set the interrupt disable bit Update the control bits in the CPSR interrupts (IRQ) now disabled Read the CPSR Clear the mode bits Set the mode bits to FIQ mode Update the control bits in the CPSR now in FIQ mode
MRS ORR MSR
R0, CPSR R0, R0, #0x80 CPSR_c, R0
MRS BIC ORR MSR
R0, CPSR R0, R0, #0x1F R0, R0, #0x11 CPSR_c, R0
A3.10.3 List of status register access instructions
MRS MSR CPS
Move PSR to General-purpose Register. See MRS on page A4-74. Move General-purpose Register to PSR. See MSR on page A4-76. Change Processor State. Changes one or more of the processor mode and interrupt enable bits of the CPSR, without changing the other CPSR bits. See CPS on page A4-29. Modifies the CPSR endianness, E, bit, without changing any other bits in the CPSR. See SETEND on page A4-129.
SETEND
The processor state bits can also be updated by a variety of branch, load and return instructions which update the PC. Changes occur when they are used for Jazelle state entry/exit and Thumb interworking.
A3-20
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.11 Load and store instructions
The ARM architecture supports two broad types of instruction which load or store the value of a single register, or a pair of registers, from or to memory: The first type can load or store a 32-bit word or an 8-bit unsigned byte. The second type can load or store a 16-bit unsigned halfword, and can load and sign extend a 16-bit halfword or an 8-bit byte. In ARMv5TE and above, it can also load or store a pair of 32-bit words.
A3.11.1 Addressing modes
In both types of instruction, the addressing mode is formed from two parts: the base register the offset. The base register can be any one of the general-purpose registers (including the PC, which allows PC-relative addressing for position-independent code). The offset takes one of three formats: Immediate The offset is an unsigned number that can be added to or subtracted from the base register. Immediate offset addressing is useful for accessing data elements that are a fixed distance from the start of the data object, such as structure fields, stack offsets and input/output registers. For the word and unsigned byte instructions, the immediate offset is a 12-bit number. For the halfword and signed byte instructions, it is an 8-bit number. Register The offset is a general-purpose register (not the PC), that can be added to or subtracted from the base register. Register offsets are useful for accessing arrays or blocks of data. The offset is a general-purpose register (not the PC) shifted by an immediate value, then added to or subtracted from the base register. The same shift operations used for data-processing instructions can be used (Logical Shift Left, Logical Shift Right, Arithmetic Shift Right and Rotate Right), but Logical Shift Left is the most useful as it allows an array indexed to be scaled by the size of each array element. Scaled register offsets are only available for the word and unsigned byte instructions.
Scaled register
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-21
The ARM Instruction Set
As well as the three types of offset, the offset and base register are used in three different ways to form the memory address. The addressing modes are described as follows: Offset Pre-indexed The base register and offset are added or subtracted to form the memory address. The base register and offset are added or subtracted to form the memory address. The base register is then updated with this new address, to allow automatic indexing through an array or memory block. The value of the base register alone is used as the memory address. The base register and offset are added or subtracted and this value is stored back in the base register, to allow automatic indexing through an array or memory block.
Post-indexed
A3.11.2 Load and store word or unsigned byte instructions
Load instructions load a single value from memory and write it to a general-purpose register. Store instructions read a value from a general-purpose register and store it to memory. These instructions have a single instruction format:
LDR|STR{<cond>}{B}{T} Rd, <addressing_mode>
31
28 27 26 25 24 23 22 21 20 19
16 15
12 11
0
cond
0 1 I P UBWL
Rn
Rd
addressing_mode_specific
I, P, U, W L bit B bit Rn Rd
Are bits that distinguish between different types of <addressing_mode>. See Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18 Distinguishes between a Load (L==1) and a Store instruction (L==0). Distinguishes between an unsigned byte (B==1) and a word (B==0) access. Specifies the base register used by <addressing_mode>. Specifies the register whose contents are to be loaded or stored.
A3-22
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.11.3 Load and store halfword or doubleword, and load signed byte instructions
Load instructions load a single value from memory and write it to a general-purpose register, or to a pair of general-purpose registers. Store instructions read a value from a general-purpose register, or from a pair of general-purpose registers, and store it to memory. These instructions have a single instruction format:
LDR|STR{<cond>}D|H|SH|SB Rd, <addressing_mode>
31
28 27 26 25 24 23 22 21 20 19
16 15
12 11
87654
3
0
cond
0 0 0 PU IWL
Rn
Rd
addr_mode 1 S H 1 addr_mode
addr_mode I, P, U, W L, S, H
Are addressing-mode-specific bits. Are bits that specify the type of addressing mode (see Addressing Mode 3 - Miscellaneous Loads and Stores on page A5-33). These bits combine to specify signed or unsigned loads or stores, and doubleword, halfword, or byte accesses. See Addressing Mode 3 - Miscellaneous Loads and Stores on page A5-33 for details. Specifies the base register used by the addressing mode. Specifies the register whose contents are to be loaded or stored.
Rn Rd
A3.11.4 Examples
LDR LDR LDR STR LDRB LDRB STRB LDR STRB LDR LDR STRB R1, [R0] R8, [R3, #4] R12, [R13, #-4] R2, [R1, #0x100] R5, [R9] R3, [R8, #3] R4, [R10, #0x200] R11, [R1, R2] R10, [R7, -R4] R11, [R3, R5, LSL #2] R1, [R0, #4]! R7, [R6, #-1]! ; ; ; ; Load R1 from the address in R0 Load R8 from the address in R3 + 4 Load R12 from R13 - 4 Store R2 to the address in R1 + 0x100
; Load byte into R5 from R9 ; (zero top 3 bytes) ; Load byte to R3 from R8 + 3 ; (zero top 3 bytes) ; Store byte from R4 to R10 + 0x200 ; Load R11 from the address in R1 + R2 ; Store byte from R10 to addr in R7 - R4 ; Load R11 from R3 + (R5 x 4) ; Load R1 from R0 + 4, then R0 = R0 + 4 ; Store byte from R7 to R6 - 1, ; then R6 = R6 - 1 ; Load R3 from R9, then R9 = R9 + 4 ; Store R2 to R5, then R5 = R5 + 8
LDR STR
R3, [R9], #4 R2, [R5], #8
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-23
The ARM Instruction Set
LDR LDR LDRH LDRH LDRH STRH LDRSH LDRSB LDRSB LDRH STRH LDRSH
R0, [PC, #40] R0, [R1], R2 R1, [R0] R8, [R3, #2] R12, [R13, #-6] R2, [R1, #0x80] R5, [R9] R3, [R8, #3] R4, [R10, #0xC1] R11, [R1, R2] R10, [R7, -R4] R1, [R0, #2]!
; Load R0 from PC + 0x40 (= address of ; the LDR instruction + 8 + 0x40) ; Load R0 from R1, then R1 = R1 + R2 ; ; ; ; ; Load halfword to R1 from R0 (zero top 2 bytes) Load halfword into R8 from R3 + 2 Load halfword into R12 from R13 - 6 Store halfword from R2 to R1 + 0x80
; Load signed halfword to R5 from R9 ; Load signed byte to R3 from R8 + 3 ; Load signed byte to R4 from R10 + 0xC1 ; Load halfword into R11 from address ; in R1 + R2 ; Store halfword from R10 to R7 - R4 ; Load signed halfword R1 from R0 + 2, ; then R0 = R0 + 2 ; ; ; ; ; ; ; ; ; ; ; ; ; ; Load signed byte to R7 from R6 - 1, then R6 = R6 - 1 Load halfword to R3 from R9, then R9 = R9 + 2 Store halfword from R2 to R5, then R5 = R5 + 8 Load word into R4 from the address in R9 Load word into R5 from the address in R9 + 4 Store R8 at the address in R2 + 0x2C Store R9 at the address in R2 + 0x2C+4
LDRSB LDRH STRH LDRD
R7, [R6, #-1]! R3, [R9], #2 R2, [R5], #8 R4, [R9]
STRD
R8, [R2, #0x2C]
A3-24
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.11.5 List of load and store instructions
LDR LDRB LDRBT LDRD LDREX LDRH LDRSB LDRSH LDRT STR STRB STRBT STRD STREX STRH STRT
Load Word. See LDR on page A4-43. Load Byte. See LDRB on page A4-46. Load Byte with User Mode Privilege. See LDRBT on page A4-48. Load Doubleword. See LDRD on page A4-50. Load Exclusive. See LDREX on page A4-52. Load Unsigned Halfword. See LDRH on page A4-54. Load Signed Byte. See LDRSB on page A4-56. Load Signed Halfword. See LDRSH on page A4-58. Load Word with User Mode Privilege. See LDRT on page A4-60. Store Word. See STR on page A4-193. Store Byte. See STRB on page A4-195. Store Byte with User Mode Privilege. See STRBT on page A4-197. Store Doubleword. See STRD on page A4-199. Store Exclusive. See STREX on page A4-202. Store Halfword. See STRH on page A4-204. Store Word with User Mode Privilege. See STRT on page A4-206.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-25
The ARM Instruction Set
A3.12 Load and Store Multiple instructions
Load Multiple instructions load a subset, or possibly all, of the general-purpose registers from memory. Store Multiple instructions store a subset, or possibly all, of the general-purpose registers to memory. Load and Store Multiple instructions have a single instruction format:
LDM{<cond>}<addressing_mode> STM{<cond>}<addressing_mode> Rn{!}, <registers>{^} Rn{!}, <registers>{^}
where:
<addressing_mode> = IA | IB | DA | DB | FD | FA | ED | EA
31
28 27 26 25 24 23 22 21 20 19
16 15
0
cond
1 0 0 PUSWL
Rn
register list
register list
The list of <registers> has one bit for each general-purpose register. Bit 0 is for R0, and bit 15 is for R15 (the PC). The register syntax list is an opening bracket, followed by a comma-separated list of registers, followed by a closing bracket. A sequence of consecutive registers can be specified by separating the first and last registers in the range with a minus sign.
P, U, and W bits S bit
These distinguish between the different types of addressing mode (see Addressing Mode 4 - Load and Store Multiple on page A5-41). For LDMs that load the PC, the S bit indicates that the CPSR is loaded from the SPSR after all the registers have been loaded. For all STMs, and LDMs that do not load the PC, it indicates that when the processor is in a privileged mode, the User mode banked registers are transferred and not the registers of the current mode. This distinguishes between a Load (L==1) and a Store (L==0) instruction. This specifies the base register used by the addressing mode.
L bit Rn
A3.12.1 Examples
STMFD LDMFD LDMIA STMDA R13!, {R0 R13!, {R0 R0, {R5 R1!, {R2, - R12, LR} - R12, PC} R8} R5, R7 - R9, R11}
A3-26
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.12.2 List of Load and Store Multiple instructions
LDM LDM LDM STM STM
Load Multiple. See LDM (1) on page A4-36. User Registers Load Multiple. See LDM (2) on page A4-38. Load Multiple with Restore CPSR. See LDM (3) on page A4-40. Store Multiple. See STM (1) on page A4-189. User Registers Store Multiple. See STM (2) on page A4-191.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-27
The ARM Instruction Set
A3.13 Semaphore instructions
The ARM instruction set has two semaphore instructions: Swap (SWP) Swap Byte (SWPB). These instructions are provided for process synchronization. Both instructions generate an atomic load and store operation, allowing a memory semaphore to be loaded and altered without interruption.
SWP and SWPB have a single addressing mode, whose address is the contents of a register. Separate registers are used to specify the value to store and the destination of the load. If the same register is specified for both of these, SWP exchanges the value in the register and the value in memory.
The semaphore instructions do not provide a compare and conditional write facility. If wanted, this must be done explicitly.
Note
The swap and swap byte instructions are deprecated in ARMv6. It is recommended that all software migrates to using the new LDREX and STREX synchronization primitives listed in List of load and store instructions on page A3-25.
A3.13.1 Examples
SWP R12, R10, [R9] ; load R12 from address R9 and ; store R10 to address R9 ; load byte to R3 from address R8 and ; store byte from R4 to address R8 ; Exchange value in R1 and address in R2
SWPB
R3, R4, [R8]
SWP
R1, R1, [R2]
A3.13.2 List of semaphore instructions
SWP SWPB
Swap. See SWP on page A4-212. Swap Byte. See SWPB on page A4-214.
A3-28
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.14 Exception-generating instructions
The ARM instruction set provides two types of instruction whose main purpose is to cause a processor exception to occur: The Software Interrupt (SWI) instruction is used to cause a SWI exception to occur (see Software Interrupt exception on page A2-20). This is the main mechanism in the ARM instruction set by which User mode code can make calls to privileged Operating System code. The Breakpoint (BKPT) instruction is used for software breakpoints in ARMv5 and above. Its default behavior is to cause a Prefetch Abort exception to occur (see Prefetch Abort (instruction fetch memory abort) on page A2-20). A debug monitor program which has previously been installed on the Prefetch Abort vector can handle this exception. If debug hardware is present in the system, it is allowed to override this default behavior. Details of whether and how this happens are IMPLEMENTATION DEFINED.
A3.14.1 Instruction encodings
SWI{<cond>} <immed_24>
31
28 27 26 25 24 23
0
cond
1111
immed_24
BKPT
<immediate>
31
28 27 26 25 24 23 22 21 20 19
87
4
3
0
111000010010
immed
0111
immed
In both SWI and BKPT, the immediate fields of the instruction are ignored by the ARM processor. The SWI or Prefetch Abort handler can optionally be written to load the instruction that caused the exception and extract these fields. This allows them to be used to communicate extra information about the Operating System call or breakpoint to the handler.
A3.14.2 List of exception-generating instructions
BKPT SWI
Breakpoint. See BKPT on page A4-14. Software Interrupt. See SWI on page A4-210.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-29
The ARM Instruction Set
A3.15 Coprocessor instructions
The ARM instruction set provides three types of instruction for communicating with coprocessors. These allow: the ARM processor to initiate a coprocessor data processing operation ARM registers to be transferred to and from coprocessor registers the ARM processor to generate addresses for the coprocessor Load and Store instructions. The instruction set distinguishes up to 16 coprocessors with a 4-bit field in each coprocessor instruction, so each coprocessor is assigned a particular number.
Note
One coprocessor can use more than one of the 16 numbers if a large coprocessor instruction set is required. Coprocessors execute the same instruction stream as ARM, ignoring ARM instructions and coprocessor instructions for other coprocessors. Coprocessor instructions that cannot be executed by coprocessor hardware cause an Undefined Instruction exception, allowing software emulation of coprocessor hardware. A coprocessor can partially execute an instruction and then cause an exception. This is useful for handling run-time-generated exceptions, like divide-by-zero or overflow. However, the partial execution is internal to the coprocessor and is not visible to the ARM processor. As far as the ARM processor is concerned, the instruction is held at the start of its execution and completes without exception if allowed to begin execution. Any decision on whether to execute the instruction or cause an exception is taken within the coprocessor before the ARM processor is allowed to start executing the instruction. Not all fields in coprocessor instructions are used by the ARM processor. Coprocessor register specifiers and opcodes are defined by individual coprocessors. Therefore, only generic instruction mnemonics are provided for coprocessor instructions. Assembler macros can be used to transform custom coprocessor mnemonics into these generic mnemonics, or to regenerate the opcodes manually.
A3.15.1 Examples
CDP p5, 2, c12, c10, c3, 4 ; ; ; ; ; ; ; ; ; ; ; ; Coproc 5 data operation opcode 1 = 2, opcode 2 = 4 destination register is 12 source registers are 10 and 3 Coproc 15 transfer to ARM register opcode 1 = 5, opcode 2 = 3 ARM destination register = R4 coproc source registers are 0 and 2 ARM register transfer to Coproc 14 opcode 1 = 1, opcode 2 = 6 ARM source register = R7 coproc dest registers are 7 and 12
MRC
p15, 5, R4, c0, c2, 3
MCR
p14, 1, R7, c7, c12, 6
LDC
p6, CR1, [R4]
; Load from memory to coprocessor 6
A3-30
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
; ARM register 4 contains the address ; Load to CP reg 1 LDC p6, CR4, [R2, #4] ; Load from memory to coprocessor 6 ; ARM register R2 + 4 is the address ; Load to CP reg 4 ; ; ; ; ; ; ; ; Store from coprocessor 8 to memory ARM register R2 + 4 is the address after the transfer R2 = R2 + 4 Store from CP reg 8 Store from coprocessor 8 to memory ARM register R2 holds the address after the transfer R2 = R2 - 16 Store from CP reg 9
STC
p8, CR8, [R2, #4]!
STC
p8, CR9, [R2], #-16
A3.15.2 List of coprocessor instructions
CDP LDC MCR MCRR MRC MRRC STC
Coprocessor Data Operations. See CDP on page A4-23. Load Coprocessor Register. See LDC on page A4-34. Move to Coprocessor from ARM Register. See MCR on page A4-62. Move to Coprocessor from two ARM Registers. See MCRR on page A4-64. Move to ARM Register from Coprocessor. See MRC on page A4-70. Move to two ARM Registers from Coprocessor. See MRRC on page A4-72. Store Coprocessor Register. See STC on page A4-186.
Note
MCRR and MRRC are only available in ARMv5TE and above.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-31
The ARM Instruction Set
A3.16 Extending the instruction set
Successive versions of the ARM architecture have extended the instruction set in a number of areas. This section describes the six areas where extensions have occurred, and where further extensions can occur in the future: Media instruction space on page A3-33 Multiply instruction extension space on page A3-35 Control and DSP instruction extension space on page A3-36 Load/store instruction extension space on page A3-38 Architecturally Undefined Instruction space on page A3-39 Coprocessor instruction extension space on page A3-40 Unconditional instruction extension space on page A3-41.
UNPREDICTABLE.
Instructions in these areas which have not yet been allocated a meaning are either UNDEFINED or To determine which, use the following rules: The decode bits of an instruction are defined to be bits[27:20] and bits[7:4]. In ARMv5 and above, the result of ANDing bits[31:28] together is also a decode bit. This bit determines whether the condition field is 0b1111, which is used in ARMv5 and above to encode various instructions which can only be executed unconditionally. See Condition code 0b1111 on page A3-4 and Unconditional instruction extension space on page A3-41 for more information.
1.
2.
If the decode bits of an instruction are equal to those of a defined instruction, but the whole instruction is not a defined instruction, then the instruction is UNPREDICTABLE. For example, suppose an instruction has: bits[31:28] not equal to 0b1111 bits[27:20] equal to 0b00010000 bits[7:4] equal to 0b0000 but where: bit[11] of the instruction is 1. Here, the instruction is in the control instruction extension space and has the same decode bits as an MRS instruction, but is not a valid MRS instruction because bit[11] of an MRS instruction should be zero. Using the above rule, this instruction is UNPREDICTABLE.
3.
If the decode bits of an instruction are not equal to those of any defined instruction, then the instruction is UNDEFINED.
Rules 2 and 3 above apply separately to each ARM architecture version. As a result, the status of an instruction might differ between architecture versions. Usually, this happens because an instruction which was UNPREDICTABLE or UNDEFINED in an earlier architecture version becomes a defined instruction in a later version. For the purposes of this section, all coprocessor instructions described in Chapter A4 ARM Instructions as appearing in a version of the architecture have been allocated. The definitions of any coprocessors using the coprocessor instructions determine the function of the instructions. Such coprocessors can define UNPREDICTABLE and UNDEFINED behaviours.
A3-32 Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100I
The ARM Instruction Set
A3.16.1 Media instruction space
Instructions with the following opcodes are defined as residing in the media instruction space:
opcode[27:25] = 0b011 opcode[4] = 1
31
28 27 26 25 24
54
3
0
cond
011
op
xxxxxxxxxxxxxxxxxx1xxxx
The meaning of unallocated instructions in the media instruction space is UNDEFINED on all versions of the ARM architecture. Table A3-3 summarizes the instructions that have already been allocated in this area. Table A3-3 Media instruction space Instructions Parallel additions, subtractions, and addition with subtractions. See Parallel addition and subtraction instructions on page A3-14.
PKH, SSAT, SSAT16, USAT, USAT16, SEL
Architecture versions ARMv6 and above ARMv6 and above
Also sign/zero extend and add instructions. See Extend instructions on page A3-16.
SMLAD, SMLSD, SMLALD, SMUAD, SMUSD USAD8, USADA8 REV, REV16, REVSH
ARMv6 and above ARMv6 and above ARMv6 and above
Figure A3-2 on page A3-34 provides details of these instructions.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-33
The ARM Instruction Set
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Parallel add/subtract Halfword pack Word saturate Parallel halfword saturate Byte reverse word Byte reverse packed halfword Byte reverse signed halfword Select bytes Sign/zero extend (add) Multiplies (type 3) Unsigned sum of absolute differences Unsigned sum of absolute differences, acc
cond cond cond cond cond cond cond cond cond cond cond cond
01100
opc1
Rn Rn sat_imm sat_imm SBO SBO SBO Rn Rn Rd/RdHi Rd Rd
Rd Rd Rd Rd Rd Rd Rd Rd Rd Rn/RdLo Rn* 1111
SBO shift_imm shift_imm SBO SBO SBO SBO SBO
opc2
1
Rm Rm Rm Rm Rm Rm Rm Rm Rm Rm Rm Rm
01101000 01101U1 01101U10 01101011 01101011 01101111 01101000 01101 01110 op opc1
op 0 1 sh 0 1 0011 0011 1011 1011 1011
rotate SBZ 0 1 1 1 Rs Rs Rs opc2 1
01111000 01111000
0001 0001
Figure A3-2 Media instructions Rn* Rn != R15.
A3-34
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.16.2 Multiply instruction extension space
Instructions with the following opcodes are the multiply instruction extension space:
opcode[27:24] opcode[7:4] opcode[31:28] == 0b0000 == 0b1001 != 0b1111
/* Only required for version 5 and above */
The field names given are guidelines suggested to simplify implementation.
31 28 27 26 25 24 23 20 19 16 15 12 11 87654 3 0
cond
0000
op1
Rn
Rd
Rs
1001
Rm
Table A3-4 summarizes the instructions that have already been allocated in this area. Table A3-4 Multiply instruction extension space Instructions
MUL, MULS, MLA, MLAS UMULL, UMULLS, UMLAL, UMLALS, SMULL, SMULLS, SMLAL, SMLALS UMAAL
Architecture versions All All ARMv6 and above
Figure A3-3 provides details of these instructions.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Multiply (acc) Unsigned multiply acc acc long Multiply (acc) long
cond cond cond
00 00 00
0000 0001
AS 00
Rd RdHi RdHi
Rn RdLo RdLo
Rs Rs Rs
100 100 100
1 1 1
Rm Rm Rm
0 0 1 Un A S
Figure A3-3 Multiply instructions A Un S Accumulate 1 = Unsigned, 0 = Signed Status register update (SPSR => CPSR)
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-35
The ARM Instruction Set
A3.16.3 Control and DSP instruction extension space
Instructions with the following opcodes are the control instruction space.
opcode[27:26] opcode[24:23] opcode[20] opcode[31:28] == == == != 0b00 0b10 0 0b1111
/* Only required for version 5 and above */
and not:
opcode[25] == 0 opcode[7] == 1 opcode[4] == 1
The field names given are guidelines suggested to simplify implementation.
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond cond cond
0 0 0 1 0 op1 0 0 0 0 1 0 op1 0 00110R10
Rn Rn Rn
Rd Rd Rd
Rs Rs rotate_imm
op2
0
Rm Rm
0 op2 1 immed_8
Table A3-5 summarizes the instructions that have already been allocated in this area. Table A3-5 Control and DSP extension space instructions Instruction
MRS MSR (register form) BX
Architecture versions All All ARMv5 and above, plus T variants of ARMv4 ARMv5 and above ARMv5EJ and above ARMv5 and above E variants of ARMv5 and above E variants of ARMv5 and above E variants of ARMv5 and above
CLZ BXJ BLX (register form) QADD QSUB QDADD
A3-36
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
Table A3-5 Control and DSP extension space instructions (continued) Instruction
QDSUB BKPT SMLA<x><y> SMLAW<y> SMULW<y> SMLAL<x><y> SMUL<x><y> MSR (immediate form)
Architecture versions E variants of ARMv5 and above ARMv5 and above E variants of ARMv5 and above E variants of ARMv5 and above E variants of ARMv5 and above E variants of ARMv5 and above E variants of ARMv5 and above All
Figure A3-4 provides details of these instructions.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Move status register to register Move register to status register Move immediate to status register Branch/exchange instruction set Thumb Branch/exchange instruction set Java Count leading zeros Branch and link/exchange instruction set Thumb Saturating add/subtract Software breakpoint Signed multiplies (type 2)
cond cond cond cond cond cond cond cond cond cond
00010R00 00010R10 00110R10 00010010 00010010 00010110 00010010 00010 op 0
SBO mask mask SBO SBO SBO SBO Rn
Rd SBO SBO SBO SBO Rd SBO Rd immed
SBZ SBZ rot_imm SBO SBO SBO SBO SBZ
0000 0000 immed 0001 0 0 10 0001 0011 0101 0111
SBZ Rm
Rm Rm Rm Rm Rm immed Rm
00 0100 1 0 00010 op 0 Rd
Rn
Rs
1yx0
Figure A3-4 Miscellaneous instructions
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-37
The ARM Instruction Set
A3.16.4 Load/store instruction extension space
Instructions with the following opcodes are the load/store instruction extension space:
opcode[27:25] opcode[7] opcode[4] opcode[31:28] == == == != 0b000 1 1 0b1111 /* Only required for version 5 and above */
and not:
opcode[24] == 0 opcode[6:5] == 0
The field names given are guidelines suggested to simplify implementation.
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0 0 0 P UBWL
Rn
Rd
Rs
1 op1 1
Rm
Table A3-6 summarizes the instructions that have already been allocated in this area. Table A3-6 Load/store instructions Instruction
SWP/SWPB LDREX STREX STRH LDRD
Architecture versions All (deprecated in ARMv6) ARMv6 and above ARMv6 and above All E variants of ARMv5 and above, except ARMv5TExP E variants of ARMv5 and above, except ARMv5TExP All All All
STRD
LDRH LDRSB LDRSH
Figure A3-5 on page A3-39 provides details of these extra load/store instructions.
A3-38
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Swap/swap byte Load/store register exclusive Load/store halfword register offset Load/store halfword immediate offset Load signed halfword/byte immediate offset Load signed halfword/byte register offset Load/store doubleword register offset Load/store doubleword immediate offset
cond cond cond cond cond cond cond cond
0 0 0 1 0 B0 0 00011 00L 0 0 0 PU 0W L 0 0 0 PU 1W L 0 0 0 PU 1 W1 0 0 0 PU 0W 1 0 0 0 PU 0 W0 0 0 0 PU 1W0
Rn Rn Rn Rn Rn Rn Rn Rn
Rd Rd Rd Rd Rd Rd Rd Rd
SBZ SBO SBZ HiOffset HiOffset SBZ SBZ HiOffset
1001 1001 1011 1011 1 1H1 11H1 1 1 St 1 1 1 St 1
Rm SBO Rm LoOffset LoOffset Rm Rm LoOffset
B P, U, I, W L H St
Figure A3-5 Extra Load/store instructions 1 = Byte, 0 = Word Pre/post indexing or offset, Up/down, Immediate/register offset, and address Write-back fields for the address mode. See Chapter A5 ARM Addressing Modes for more details. 1 = Load, 0 = Store 1= Halfword, 0 = Byte 1 = Store, 0 = Load
A3.16.5 Architecturally Undefined Instruction space
In general, Undefined instructions might be used to extend the ARM instruction set in the future. However, it is intended that instructions with the following encoding will not be used for this:
31 28 27 26 25 24 23 22 21 20 19 87654 3210
cond
01111111xxxxxxxxxxxx1111xxxx
If a programmer wants to use an Undefined instruction for software purposes, with minimal risk that future hardware will treat it as a defined instruction, one of the instructions with this encoding must be used.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-39
The ARM Instruction Set
A3.16.6 Coprocessor instruction extension space
Instructions with the following opcodes are the coprocessor instruction extension space:
opcode[27:23] opcode[21] == 0b11000 == 0
The field names given are guidelines suggested to simplify implementation.
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 0
cond
11000x0x
Rn
CRd
cp_num
offset
In all variants of ARMv4, and in non-E variants of ARMv5, all instructions in the coprocessor instruction extension space are UNDEFINED. It is IMPLEMENTATION DEFINED how an ARM processor achieves this. The options are: The ARM processor might take the Undefined Instruction exception directly. The ARM processor might require attached coprocessors not to respond to such instructions. This causes the Undefined Instruction exception to be taken (see Undefined Instruction exception on page A2-19).
From E variants of ARMv5, instructions in the coprocessor instruction extension space are treated as follows: Instructions with bit[22] == 0 are UNDEFINED and are handled in precisely the same way as described above for non-E variants. Instructions with bit[22] ==1 are the MCRR and MRRC instructions, see MCRR on page A4-64 and MRRC on page A4-72.
A3-40
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The ARM Instruction Set
A3.16.7 Unconditional instruction extension space
In ARMv5 and above, instructions with the following opcode are the unconditional instruction space:
opcode[31:28] == 0b1111
31 30 29 28 27
20 19
87
4
3
0
1111
opcode1
xxxxxxxxxxxx
opcode2
xxxx
Table A3-7 summarizes the instructions that have already been allocated in this area. Table A3-7 Unconditional instruction extension space Instruction
CPS/SETEND
Architecture versions ARMv6 and above E variants of ARMv5 and above, except ARMv5TExP ARMv6 ARMv6 ARMv5 and above ARMv6 and above ARMv6 and above ARMv5 and above ARMv5 and above ARMv5 and above ARMv5 and above ARMv5 and above
PLD
RFE SRS BLX
(address form)
MCRR2 MRRC2 STC2 LDC2 CDP2 MCR2 MRC2
Figure A3-6 on page A3-42 provides details of the unconditional instructions.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A3-41
The ARM Instruction Set
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Change Processor State Set Endianness Cache Preload Save Return State Return From Exception Branch with Link and change to Thumb Additional coprocessor double register transfer Additional coprocessor register transfer Undefined instruction
1 1 1 1 0 0 0 1 0 0 0 0 imod M 0 1111000100000001 111101X1U101 1 1 1 1 1 0 0PU 1W0 1 1 1 1 1 0 0 PU 0W1 1111101H 11111100010L 11111110 opc1 L Rn CRn Rn 1101 Rn
SBZ SBZ 1111 SBZ SBZ
AIF0 S EB0000 Z addr_mode 0101 1010 SBZ SBZ
mode SBZ
mode
24-bit offset Rd Rd cp_num cp_num opcode opc2 1 CRm CRm
11111111xxxxxxxxxxxxxxxxxxxxxxxx
Figure A3-6 Unconditional instructions M X mmod In addressing mode 2, X=0 implies an immediate offset/index, and X=1 a register based offset/index.
A3-42
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Chapter A4 ARM Instructions
This chapter describes the syntax and usage of every ARM instruction, in the sections: Alphabetical list of ARM instructions on page A4-2 ARM instructions and architecture versions on page A4-286.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-1
ARM Instructions
A4.1
Alphabetical list of ARM instructions
Every ARM instruction is listed on the following pages. Each instruction description shows: the instruction encoding the instruction syntax the version of the ARM architecture where the instruction is valid any exceptions that apply an example in pseudo-code of how the instruction operates notes on usage and special cases.
A4.1.1
General notes
These notes explain the types of information and abbreviations used on the instruction pages.
Addressing modes
Many instructions refer to one of the addressing modes described in Chapter A5 ARM Addressing Modes. The description of the referenced addressing mode should be considered an intrinsic part of the instruction description. In particular: The addressing modes encoding diagram and assembler syntax provide additional details over and above the instructions encoding diagram and assembler syntax. The addressing modes Operation pseudo-code calculates values used in the instructions pseudo-code, and in some cases specify additional effects of the instruction. All usage notes, operand restrictions, and other notes about the addressing mode apply to the instruction.
Syntax abbreviations
The following abbreviations are used in the instruction pages:
immed_n
This is an immediate value, where n is the number of bits. For example, an 8-bit immediate value is represented by:
immed_8
offset_n
This is an offset value, where n is the number of bits. For example, an 8-bit offset value is represented by:
offset_8
The same construction is used for signed offsets. For example, an 8-bit signed offset is represented by:
signed_offset_8
A4-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Encoding diagram and assembler syntax
For the conventions used, see Assembler syntax descriptions on page xxii.
Architecture versions
This gives details of architecture versions where the instruction is valid. For further information on architecture versions, see Architecture versions and variants on page xiii.
Exceptions
This gives details of which exceptions can occur during the execution of the instruction. Prefetch Abort is not listed in general, both because it can occur for any instruction and because if an abort occurred during instruction fetch, the instruction bit pattern is not known. (Prefetch Abort is however listed for BKPT, since it can generate a Prefetch Abort exception without these considerations applying.)
Operation
This gives a pseudo-code description of what the instruction does. For details of conventions used in this pseudo-code, see Pseudo-code descriptions of instructions on page xxi.
Information on usage
Usage sections are included where appropriate to supply suggestions and other information about how to use the instruction effectively.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-3
ARM Instructions
A4.1.2
ADC
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I0101S
Rn
Rd
shifter_operand
ADC (Add with Carry) adds two values and the Carry flag. The first value comes from a register. The second
value can be either an immediate value or a value from a register, and can be shifted before the addition.
ADC can optionally update the condition code flags, based on the result.
Syntax
ADC{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the addition, and the C and V flags are set according to whether the addition generated a carry (unsigned overflow) and a signed overflow, respectively. The rest of the CPSR is unchanged. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the first operand.
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not ADC. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
A4-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = Rn + shifter_operand + C Flag if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = CarryFrom(Rn + shifter_operand + C Flag) V Flag = OverflowFrom(Rn + shifter_operand + C Flag)
Usage
Use ADC to synthesize multi-word addition. If register pairs R0, R1 and R2, R3 hold 64-bit values (where R0 and R2 hold the least significant words) the following instructions leave the 64-bit sum in R4, R5:
ADDS R4,R0,R2 ADC R5,R1,R3
If the second instruction is changed from:
ADC R5,R1,R3
to:
ADCS R5,R1,R3
the resulting values of the flags indicate:
N C V Z
The 64-bit addition produced a negative result. An unsigned overflow occurred. A signed overflow occurred. The most significant 32 bits are all zero.
The following instruction produces a single-bit Rotate Left with Extend operation (33-bit rotate through the Carry flag) on R0:
ADCS R0,R0,R0
See Data-processing operands - Rotate right with extend on page A5-17 for information on how to perform a similar rotation to the right.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-5
ARM Instructions
A4.1.3
ADD
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I0100S
Rn
Rd
shifter operand
ADD adds two values. The first value comes from a register. The second value can be either an immediate
value or a value from a register, and can be shifted before the addition.
ADD can optionally update the condition code flags, based on the result.
Syntax
ADD{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the addition, and the C and V flags are set according to whether the addition generated a carry (unsigned overflow) and a signed overflow, respectively. The rest of the CPSR is unchanged. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the first operand.
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not ADD. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
A4-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = Rn + shifter_operand if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = CarryFrom(Rn + shifter_operand) V Flag = OverflowFrom(Rn + shifter_operand)
Usage
Use ADD to add two values together. To increment a register value in Rx use:
ADD Rx, Rx, #1
You can perform constant multiplication of Rx by 2n+1 into Rd with:
ADD Rd, Rx, Rx, LSL #n
To form a PC-relative address use:
ADD Rd, PC, #offset
where the offset must be the difference between the required address and the address held in the PC, where the PC is the address of the ADD instruction itself plus 8 bytes.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-7
ARM Instructions
A4.1.4
AND
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I0000S
Rn
Rd
shifter_operand
AND performs a bitwise AND of two values. The first value comes from a register. The second value can be
either an immediate value or a value from a register, and can be shifted before the AND operation.
AND can optionally update the condition code flags, based on the result.
Syntax
AND{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the operation, and the C flag is set to the carry output bit generated by the shifter (see Addressing Mode 1 - Data-processing operands on page A5-2). The V flag and the rest of the CPSR are unaffected. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the first operand.
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not AND. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
A4-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = Rn AND shifter_operand if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = shifter_carry_out V Flag = unaffected
Usage
AND is most useful for extracting a field from a register, by ANDing the register with a mask value that has
1s in the field to be extracted, and 0s elsewhere.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-9
ARM Instructions
A4.1.5
B, BL
31 28 27 26 25 24 23 0
cond
101L
signed_immed_24
B (Branch) and BL (Branch and Link) cause a branch to a target address, and provide both conditional and unconditional changes to program flow. BL also stores a return address in the link register, R14 (also known as LR).
Syntax
B{L}{<cond>} <target_address>
where:
L
Causes the L bit (bit 24) in the instruction to be set to 1. The resulting instruction stores a return address in the link register (R14). If L is omitted, the L bit is 0 and the instruction simply branches without storing a return address. Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used.
<cond>
<target_address>
Specifies the address to branch to. The branch target address is calculated by: 1. 2. 3. Sign-extending the 24-bit signed (two's complement) immediate to 30 bits. Shifting the result left two bits to form a 32-bit value. Adding this to the contents of the PC, which contains the address of the branch instruction plus 8 bytes.
The instruction can therefore specify a branch of approximately 32MB (see Usage on page A4-11 for precise range).
Architecture version
All.
Exceptions
None.
A4-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if L == 1 then LR = address of the instruction after the branch instruction PC = PC + (SignExtend_30(signed_immed_24) << 2)
Usage
Use BL to perform a subroutine call. The return from subroutine is achieved by copying R14 to the PC. Typically, this is done by one of the following methods: Executing a BX R14 instruction, on architecture versions that support that instruction. Executing a MOV PC,R14 instruction. Storing a group of registers and R14 to the stack on subroutine entry, using an instruction of the form:
STMFD R13!,{<registers>,R14}
and then restoring the register values and returning with an instruction of the form:
LDMFD R13!,{<registers>,PC}
To calculate the correct value of signed_immed_24, the assembler (or other toolkit component) must: 1. 2. 3. 4. Form the base address for this branch instruction. This is the address of the instruction, plus 8. In other words, this base address is equal to the PC value used by the instruction. Subtract the base address from the target address to form a byte offset. This offset is always a multiple of four, because all ARM instructions are word-aligned. If the byte offset is outside the range 33554432 to [phone], use an alternative code-generation strategy or produce an error as appropriate. Otherwise, set the signed_immed_24 field of the instruction to bits{25:2] of the byte offset.
Notes
Memory bounds Branching backwards past location zero and forwards over the end of the 32-bit address space is UNPREDICTABLE.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-11
ARM Instructions
A4.1.6
BIC
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I1110S
Rn
Rd
shifter_operand
BIC (Bit Clear) performs a bitwise AND of one value with the complement of a second value. The first value
comes from a register. The second value can be either an immediate value or a value from a register, and can be shifted before the BIC operation.
BIC can optionally update the condition code flags, based on the result.
Syntax
BIC{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit, bit[20], in the instruction to be set to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the operation, and the C flag is set to the carry output bit generated by the shifter (see Addressing Mode 1 - Data-processing operands on page A5-2). The V flag and the rest of the CPSR are unaffected. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the first operand.
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not BIC. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
A4-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = Rn AND NOT shifter_operand if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = shifter_carry_out V Flag = unaffected
Usage
Use BIC to clear selected bits in a register. For each bit, BIC with 1 clears the bit, and BIC with 0 leaves it unchanged.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-13
ARM Instructions
A4.1.7
BKPT
31 28 27 26 25 24 23 22 21 20 19 8 7 43 0
111000010010
immed
0111
immed
BKPT (Breakpoint) causes a software breakpoint to occur. This breakpoint can be handled by an exception handler installed on the Prefetch Abort vector. In implementations that also include debug hardware, the hardware can optionally override this behavior and handle the breakpoint itself. When this occurs, the Prefetch Abort exception context is presented to the debugger.
Syntax
BKPT <immed_16>
where:
<immed_16>
Is a 16-bit immediate value. The top 12 bits of <immed_16> are placed in bits[19:8] of the instruction, and the bottom 4 bits are placed in bits[3:0] of the instruction. This value is ignored by the ARM hardware, but can be used by a debugger to store additional information about the breakpoint.
Architecture version
Version 5 and above.
Exceptions
Prefetch Abort.
Operation
if (not overridden by debug hardware) R14_abt = address of BKPT instruction + 4 SPSR_abt = CPSR CPSR[4:0] = 0b10111 /* Enter Abort mode */ CPSR[5] =0 /* Execute in ARM state */ /* CPSR[6] is unchanged */ CPSR[7] =1 /* Disable normal interrupts */ CPSR[8] =1 /* Disable imprecise aborts - v6 only */ CPSR[9] = CP15_reg1_EEbit if high vectors configured then PC = 0xFFFF000C else PC = 0x0000000C
A4-14
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
The exact usage of BKPT depends on the debug system being used. A debug system can use the BKPT instruction in two ways: Monitor debug-mode. Debug hardware, (optional prior to ARMv6), does not override the normal behavior of the BKPT instruction, and so the Prefetch Abort vector is entered. The IFSR is updated to indicate a debug event, allowing software to distinguish debug events due to BKPT instruction execution from other system Prefetch Aborts. When used in this manner, the BKPT instruction must be avoided within abort handlers, as it corrupts R14_abt and SPSR_abt. For the same reason, it must also be avoided within FIQ handlers, since an FIQ interrupt can occur within an abort handler. Halting debug-mode. Debug hardware does override the normal behavior of the BKPT instruction and handles the software breakpoint itself. When finished, it typically either resumes execution at the instruction following the BKPT, or replaces the BKPT in memory with another instruction and resumes execution at that instruction. When BKPT is used in this manner, R14_abt and SPSR_abt are not corrupted, and so the above restrictions about its use in abort and FIQ handlers do not apply.
Notes
Condition field Hardware override
BKPT is unconditional. If bits[31:28] of the instruction encode a valid condition other than the AL (always) condition, the instruction is UNPREDICTABLE.
Debug hardware in an implementation is specifically permitted to override the normal behavior of the BKPT instruction. Because of this, software must not use this instruction for purposes other than those documented by the debug system being used (if any). In particular, software cannot rely on the Prefetch Abort exception occurring, unless either there is guaranteed to be no debug hardware in the system or the debug system specifies that it occurs. For more information, consult the documentation for the debug system being used.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-15
ARM Instructions
A4.1.8
BLX (1)
31 30 29 28 27 26 25 24 23 0
1111101H
signed_immed_24
BLX (1) (Branch with Link and Exchange) calls a Thumb subroutine from the ARM instruction set at an
address specified in the instruction. This form of BLX is unconditional (always causing a change in program flow) and preserves the address of the instruction following the branch in the link register (R14). Execution of Thumb instructions begins at the target address.
Syntax
BLX <target_addr>
where:
<target_addr>
Specifies the address of the Thumb instruction to branch to. The branch target address is calculated by: 1. Sign-extending the 24-bit signed (two's complement) immediate to 30 bits 2. Shifting the result left two bits to form a 32-bit value 3. Setting bit[1] of the result of step 2 to the H bit 4. Adding the result of step 3 to the contents of the PC, which contains the address of the branch instruction plus 8. The instruction can therefore specify a branch of approximately 32MB (see Usage on page A4-17 for precise range).
Architecture version
Version 5 and above. See The T and J bits on page A2-15 for further details of operation on non-T variants.
Exceptions
None.
Operation
LR = address of the instruction after the BLX instruction CPSR T bit = 1 PC = PC + (SignExtend(signed_immed_24) << 2) + (H << 1)
A4-16
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
To return from a Thumb subroutine called via BLX to the ARM caller, use the Thumb instruction:
BX R14
as described in BX on page A7-32, or use this instruction on subroutine entry:
PUSH {<registers>,R14}
and this instruction to return:
POP {<registers>,PC}
To calculate the correct value of signed_immed_24, the assembler (or other toolkit component) must: 1. 2. 3. 4. Form the base address for this branch instruction. This is the address of the instruction, plus 8. In other words, this base address is equal to the PC value used by the instruction. Subtract the base address from the target address to form a byte offset. This offset is always even, because all ARM instructions are word-aligned and all Thumb instructions are halfword-aligned. If the byte offset is outside the range 33554432 to [phone], use an alternative code-generation strategy or produce an error as appropriate. Otherwise, set the signed_immed_24 field of the instruction to bits[25:2] of the byte offset, and the H bit of the instruction to bit[1] of the byte offset.
Notes
Condition Bit[24] Unlike most other ARM instructions, this instruction cannot be executed conditionally. This bit is used as bit[1] of the target address.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-17
ARM Instructions
A4.1.9
BLX (2)
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00010010
SBO
SBO
SBO
0011
Rm
BLX (2) calls an ARM or Thumb subroutine from the ARM instruction set, at an address specified in a
register. It sets the CPSR T bit to bit[0] of Rm. This selects the instruction set to be used in the subroutine. The branch target address is the value of register Rm, with its bit[0] forced to zero. It sets R14 to a return address. To return from the subroutine, use a BX R14 instruction, or store R14 on the stack and reload the stored value into the PC.
Syntax
BLX{<cond>} <Rm>
where:
<cond> <Rm>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Is the register containing the address of the target instruction. Bit[0] of Rm is 0 to select a target ARM instruction, or 1 to select a target Thumb instruction. If R15 is specified for <Rm>, the results are UNPREDICTABLE.
Architecture version
Version 5 and above. See The T and J bits on page A2-15 for further details of operation on non-T variants.
Exceptions
None.
Operation
if ConditionPassed(cond) then target = Rm LR = address of instruction after the BLX instruction CPSR T bit = target[0] PC = target AND 0xFFFFFFFE
A4-18
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Notes
ARM/Thumb state transfers If Rm[1:0] == 0b10, the result is UNPREDICTABLE, as branches to non word-aligned addresses are impossible in ARM state.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-19
ARM Instructions
A4.1.10 BX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00010010
SBO
SBO
SBO
0001
Rm
BX (Branch and Exchange) branches to an address, with an optional switch to Thumb state.
Syntax
BX{<cond>} <Rm>
where:
<cond> <Rm>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Holds the value of the branch target address. Bit[0] of Rm is 0 to select a target ARM instruction, or 1 to select a target Thumb instruction.
Architecture version
Version 5 and above, and T variants of version 4. See The T and J bits on page A2-15 for further details of operation on non-T variants of version 5.
Exceptions
None.
Operation
if ConditionPassed(cond) then CPSR T bit = Rm[0] PC = Rm AND 0xFFFFFFFE
Notes
ARM/Thumb state transfers If Rm[1:0] == 0b10, the result is UNPREDICTABLE, as branches to non word-aligned addresses are impossible in ARM state. Use of R15 Register 15 can be specified for <Rm>, but doing so is discouraged. In a BX R15 instruction, R15 is read as normal for ARM code, that is, it is the address of the BX instruction itself plus 8. The result is to branch to the second following word, executing in ARM state. This is precisely the same effect that would have been obtained if a B instruction with an offset field of 0 had been executed, or an ADD PC,PC,#0 or MOV PC,PC instruction. In new code, use these instructions in preference to the more complex BX PC instruction.
A4-20
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.11 BXJ
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
00010010
SBO
SBO
SBO
0010
Rm
BXJ (Branch and change to Jazelle state) enters Jazelle state if Jazelle is available and enabled. Otherwise BXJ behaves exactly as BX (see BX on page A4-20).
Syntax
BXJ{<cond>} <Rm>
where:
<cond> <Rm>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Holds the value of the branch target address for use if Jazelle state is not available. Bit[0] of Rm is 0 to select a target ARM instruction, or 1 to select a target Thumb instruction.
Architecture version
Version 6 and above, plus ARMv5TEJ.
Exceptions
None.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-21
ARM Instructions
Operation
if ConditionPassed(cond) then if (JE bit of Main Configuration register) == 0 then T Flag = Rm[0] PC = Rm AND 0xFFFFFFFE else jpc = SUB-ARCHITECTURE DEFINED value invalidhandler = SUB-ARCHITECTURE DEFINED value if (Jazelle Extension accepts opcode at jpc) then if (CV bit of Jazelle OS Control register) == 0 then PC = invalidhandler else J Flag = 1 Start opcode execution at jpc else if ((CV bit of Jazelle OS Control register) == 0) AND (IMPLEMENTATION DEFINED CONDITION) then PC = invalidhandler else /* Subject to SUB-ARCHITECTURE DEFINED restrictions on Rm: */ T Flag = Rm[0] PC = Rm AND 0xFFFFFFFE
Usage
This instruction must only be used if one of the following conditions is true: The JE bit of the Main Configuration Register is 0. The Enabled Java Virtual Machine in use conforms to all the SUB-ARCHITECTURE DEFINED restrictions of the Jazelle Extension hardware being used.
Notes
ARM/Thumb state transfers
IF (JE bit of Main Configuration register) == 0 AND Rm[1:0] == 0b10, the result is UNPREDICTABLE, as branches to non word-aligned
addresses are impossible in ARM state. Use of R15 If register 15 is specified for <Rm>, the result is UNPREDICTABLE.
Jazelle opcode address The Jazelle opcode address is determined in a SUB-ARCHITECTURE DEFINED manner, typically from the contents of a specific general-purpose register, the Jazelle Program Counter (jpc).
A4-22
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.12 CDP
31 28 27 26 25 24 23 20 19 16 15 12 11 87 54 3 0
cond
1110
opcode_1
CRn
CRd
cp_num
opcode_2 0
CRm
CDP (Coprocessor Data Processing) tells the coprocessor whose number is cp_num to perform an operation
that is independent of ARM registers and memory. If no coprocessors indicate that they can execute the instruction, an Undefined Instruction exception is generated.
Syntax
CDP{<cond>} CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2> <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the condition field of the instruction to be set to 0b1111. This provides additional opcode space for coprocessor designers. The resulting instructions can only be executed unconditionally. Specifies the name of the coprocessor, and causes the corresponding coprocessor number to be placed in the cp_num field of the instruction. The standard generic coprocessor names are p0, p1, ..., p15. Specifies (in a coprocessor-specific manner) which coprocessor operation is to be performed. Specifies the destination coprocessor register for the instruction. Specifies the coprocessor register that contains the first operand. Specifies the coprocessor register that contains the second operand. Specifies (in a coprocessor-specific manner) which coprocessor operation is to be performed.
CDP2
<coproc>
<opcode_1>
<CRd> <CRn> <CRm> <opcode_2>
Architecture version
CDP is in all versions. CDP2 is in version 5 and above.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-23
ARM Instructions
Exceptions
Undefined Instruction.
Operation
if ConditionPassed(cond) then Coprocessor[cp_num]-dependent operation
Usage
Use CDP to initiate coprocessor instructions that do not operate on values in ARM registers or in main memory. An example is a floating-point multiply instruction for a floating-point coprocessor.
Notes
Coprocessor fields Only instruction bits[31:24], bits[11:8], and bit[4] are architecturally defined. The remaining fields are recommendations, for compatibility with ARM Development Systems.
Unimplemented coprocessor instructions Hardware coprocessor support is optional for coprocessors 0-13, regardless of the architecture version, and is optional for coprocessors 14 and 15 before ARMv6. An implementation can choose to implement a subset of the coprocessor instructions, or no coprocessor instructions at all. Any coprocessor instructions that are not implemented instead cause an Undefined Instruction exception.
A4-24
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.13 CLZ
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
00010110
SBO
Rd
SBO
0001
Rm
CLZ (Count Leading Zeros) returns the number of binary zero bits before the first binary one bit in a value. CLZ does not update the condition code flags.
Syntax
CLZ{<cond>} <Rd>, <Rm>
where:
<cond> <Rd> <Rm>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the operation. If R15 is specified for <Rd>, the result is
UNPREDICTABLE.
Specifies the source register for this operation. If R15 is specified for <Rm>, the result is
UNPREDICTABLE.
Architecture version
Version 5 and above.
Exceptions
None.
Operation
if Rm == 0 Rd = 32 else Rd = 31 - (bit position of most significant'1' in Rm)
Usage
Use CLZ followed by a left shift of Rm by the resulting Rd value to normalize the value of register Rm. This shifts Rm so that its most significant 1 bit is in bit[31]. Using MOVS rather than MOV sets the Z flag in the special case that Rm is zero and so does not have a most significant 1 bit:
CLZ MOVS Rd, Rm Rm, Rm, LSL Rd
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-25
ARM Instructions
A4.1.14 CMN
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I10111
Rn
SBZ
shifter_operand
CMN (Compare Negative) compares one value with the twos complement of a second value. The first value
comes from a register. The second value can be either an immediate value or a value from a register, and can be shifted before the comparison.
CMN updates the condition flags, based on the result of adding the two values.
Syntax
CMN{<cond>} <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the register that contains the first operand.
<Rn>
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not CMN. Instead, see Multiply instruction extension space on page A3-35 to determine which instruction it is.
Architecture version
All.
Exceptions
None.
Operation
if ConditionPassed(cond) then alu_out = Rn + shifter_operand N Flag = alu_out[31] Z Flag = if alu_out == 0 then 1 else 0 C Flag = CarryFrom(Rn + shifter_operand) V Flag = OverflowFrom(Rn + shifter_operand)
A4-26
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
CMN performs a comparison by adding the value of <shifter_operand> to the value of register <Rn>, and updates the condition code flags (based on the result). This is almost equivalent to subtracting the negative of the second operand from the first operand, and setting the flags on the result.
The difference is that the flag values generated can differ when the second operand is 0 or 0x80000000. For example, this instruction always leaves the C flag = 1:
CMP Rn, #0
and this instruction always leaves the C flag = 0:
CMN Rn, #0
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-27
ARM Instructions
A4.1.15 CMP
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I10101
Rn
SBZ
shifter_operand
CMP (Compare) compares two values. The first value comes from a register. The second value can be either
an immediate value or a value from a register, and can be shifted before the comparison.
CMP updates the condition flags, based on the result of subtracting the second value from the first.
Syntax
CMP{<cond>} <Rn>, <shifter_operand>
where:
<cond> <Rn>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the register that contains the first operand. Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not CMP. Instead, see Multiply instruction extension space on page A3-35 to determine which instruction it is.
<shifter_operand>
Architecture version
All.
Exceptions
None.
Operation
if ConditionPassed(cond) then alu_out = Rn - shifter_operand N Flag = alu_out[31] Z Flag = if alu_out == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rn - shifter_operand) V Flag = OverflowFrom(Rn - shifter_operand)
A4-28
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.16 CPS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 9876 54 0
1 1 1 1 0 0 0 1 0 0 0 0 imod mmod 0
SBZ
AIF0
mode
CPS (Change Processor State) changes one or more of the mode, A, I, and F bits of the CPSR, without
changing the other CPSR bits.
Syntax
CPS<effect> <iflags> {, #<mode>} CPS #<mode>
where:
<effect>
Specifies what effect is wanted on the interrupt disable bits A, I, and F in the CPSR. This is one of:
IE ID
Interrupt Enable, encoded by imod == 0b10. This sets the specified bits to 0. Interrupt Disable, encoded by imod == 0b11. This sets the specified bits to 1.
If <effect> is specified, the bits to be affected are specified by <iflags>. These are encoded in the A, I, and F bits of the instruction. The mode can optionally be changed by specifying a mode number as <mode>. If <effect> is not specified, then: <iflags> is not specified and the A, I, and F mask settings are not changed the A, I, and F bits of the instruction are zero imod = 0b00 mmod = 0b1 <mode> specifies the new mode number.
<iflags>
Is a sequence of one or more of the following, specifying which interrupt disable flags are affected:
a i f
Sets the A bit in the instruction, causing the specified effect on the CPSR A (imprecise data abort) bit. Sets the I bit in the instruction, causing the specified effect on the CPSR I (IRQ interrupt) bit. Sets the F bit in the instruction, causing the specified effect on the CPSR F (FIQ interrupt) bit.
<mode>
Specifies the number of the mode to change to. If it is present, then mmod == 1 and the mode number is encoded in the mode field of the instruction. If it is omitted, then mmod == 0 and the mode field of the instruction is zero. See The mode bits on page A2-14 for details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-29
ARM Instructions
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if InAPrivilegedMode() then if imod[1] == 1 then if A == 1 then CPSR[8] = imod[0] if I == 1 then CPSR[7] = imod[0] if F == 1 then CPSR[6] = imod[0] /* else no change to the mask */ if mmod == 1 then CPSR[4:0] = mode
Notes
User mode
CPS has no effect in User mode.
Meaningless bit combinations The following combinations of imod and mmod are meaningless: imod == 0b00, mmod == 0 imod == 0b01, mmod == 0 imod == 0b01, mmod == 1 An assembler must not generate them. The effects are UNPREDICTABLE on execution. Condition Unlike most other ARM instructions, CPS cannot be executed conditionally.
Reserved modes An attempt to change mode to a reserved value is UNPREDICTABLE
Examples
CPSIE CPSID CPS a,#31 if #16 ; enable imprecise data aborts, change to System mode ; disable interrupts and fast interrupts ; change to User mode
A4-30
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.17 CPY
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 5 4 3 0
cond
00011010
SBZ
Rd
00000000
Rm
CPY (Copy) copies a value from one register to another. It is a synonym for MOV, with no flag setting and no
shift. See MOV on page A4-68.
Syntax
CPY{<cond>} <Rd>, <Rm>
where:
<cond> <Rd> <Rm>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the source register.
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-31
ARM Instructions
A4.1.18 EOR
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I0001S
Rn
Rd
shifter_operand
EOR (Exclusive OR) performs a bitwise Exclusive-OR of two values. The first value comes from a register.
The second value can be either an immediate value or a value from a register, and can be shifted before the exclusive OR operation.
EOR can optionally update the condition code flags, based on the result.
Syntax
EOR{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Sets the S bit (bit[20]) in the instruction to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the operation, and the C flag is set to the carry output bit generated by the shifter (see Addressing Mode 1 - Data-processing operands on page A5-2). The V flag and the rest of the CPSR are unaffected. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the first operand.
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not EOR. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
A4-32
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = Rn EOR shifter_operand if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = shifter_carry_out V Flag = unaffected
Usage
Use EOR to invert selected bits in a register. For each bit, EOR with 1 inverts that bit, and EOR with 0 leaves it unchanged.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-33
ARM Instructions
A4.1.19 LDC
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 0
cond
1 1 0 P UNW1
Rn
CRd
cp_num
8_bit_word_offset
LDC (Load Coprocessor) loads memory data from a sequence of consecutive memory addresses to a
coprocessor. If no coprocessors indicate that they can execute the instruction, an Undefined Instruction exception is generated.
Syntax
LDC{<cond>}{L} LDC2{L} <coproc>, <CRd>, <addressing_mode> <coproc>, <CRd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the condition field of the instruction to be set to 0b1111. This provides additional opcode space for coprocessor designers. The resulting instructions can only be executed unconditionally. Sets the N bit (bit[22]) in the instruction to 1 and specifies a long load (for example, double-precision instead of single-precision data transfer). If L is omitted, the N bit is 0 and the instruction specifies a short load. Specifies the name of the coprocessor, and causes the corresponding coprocessor number to be placed in the cp_num field of the instruction. The standard generic coprocessor names are p0, p1, ..., p15. Specifies the coprocessor destination register.
LDC2
L
<coproc>
<CRd>
<addressing_mode>
Is described in Addressing Mode 5 - Load and Store Coprocessor on page A5-49. It determines the P, U, Rn, W and 8_bit_word_offset bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
LDC is in all versions. LDC2 is in version 5 and above.
A4-34
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
Undefined Instruction, Data Abort.
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then address = start_address load Memory[address,4] for Coprocessor[cp_num] while (NotFinished(Coprocessor[cp_num])) address = address + 4 load Memory[address,4] for Coprocessor[cp_num] assert address == end_address
Usage
LDC is useful for loading coprocessor data from memory.
Notes
Coprocessor fields Only instruction bits[31:23], bits[21:16], and bits[11:0] are ARM architecture-defined. The remaining fields (bit[22] and bits[15:12]) are recommendations, for compatibility with ARM Development Systems. In the case of the Unindexed addressing mode (P==0, U==1, W==0), instruction bits[7:0] are also not defined by the ARM architecture, and can be used to specify additional coprocessor options. Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Non word-aligned addresses For CP15_reg1_Ubit == 0, the load coprocessor register instruction ignores the least significant two bits of the address. If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor), and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception. For CP15_reg1_Ubit == 1, all non-word aligned accesses cause an alignment fault. Unimplemented coprocessor instructions Hardware coprocessor support is optional, regardless of the architecture version. An implementation can choose to implement a subset of the coprocessor instructions, or no coprocessor instructions at all. Any coprocessor instructions that are not implemented instead cause an Undefined Instruction exception.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-35
ARM Instructions
A4.1.20 LDM (1)
31 28 27 26 25 24 23 22 21 20 19 16 15 0
cond
1 0 0 PU0W1
Rn
register_list
LDM (1) (Load Multiple) loads a non-empty subset, or possibly all, of the general-purpose registers from
sequential memory locations. It is useful for block loads, stack operations and procedure exit sequences. The general-purpose registers loaded can include the PC. If they do, the word loaded for the PC is treated as an address and a branch occurs to that address. In ARMv5 and above, bit[0] of the loaded value determines whether execution continues after this branch in ARM state or in Thumb state, as though a BX (loaded_value) instruction had been executed (but see also The T and J bits on page A2-15 for operation on non-T variants of ARMv5). In earlier versions of the architecture, bits[1:0] of the loaded value are ignored and execution continues in ARM state, as though the instruction MOV PC,(loaded_value) had been executed.
Syntax
LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used.
<addressing_mode>
Is described in Addressing Mode 4 - Load and Store Multiple on page A5-41. It determines the P, U, and W bits of the instruction.
<Rn>
Specifies the base register used by <addressing_mode>. Using R15 as the base register <Rn> gives an UNPREDICTABLE result. Sets the W bit, causing the instruction to write a modified value back to its base register Rn as specified in Addressing Mode 4 - Load and Store Multiple on page A5-41. If ! is omitted, the W bit is 0 and the instruction does not change its base register in this way. (However, if the base register is included in <registers>, it changes when a value is loaded into it.)
!
<registers>
Is a list of registers, separated by commas and surrounded by { and }. It specifies the set of registers to be loaded by the LDM instruction. The registers are loaded in sequence, the lowest-numbered register from the lowest memory address (start_address), through to the highest-numbered register from the highest memory address (end_address). If the PC is specified in the register list (opcode bit[15] is set), the instruction causes a branch to the address (data) loaded into the PC. For each of i=0 to 15, bit[i] in the register_list field of the instruction is 1 if Ri is in the list and 0 otherwise. If bits[15:0] are all zero, the result is UNPREDICTABLE.
A4-36
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Architecture version
All.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then address = start_address for i = 0 to 14 if register_list[i] == 1 then Ri = Memory[address,4] address = address + 4 if register_list[15] == 1 then value = Memory[address,4] if (architecture version 5 or above) then pc = value AND 0xFFFFFFFE T Bit = value[0] else pc = value AND 0xFFFFFFFC address = address + 4 assert end_address == address - 4
Notes
Operand restrictions If the base register <Rn> is specified in <registers>, and base register write-back is specified, the final value of <Rn> is UNPREDICTABLE. Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Non word-aligned addresses For CP15_reg1_Ubit == 0, the Load Multiple instructions ignore the least significant two bits of the address. If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor), an address with bits[1:0] != 0b00 causes an alignment exception if alignment checking is enabled. For CP15_reg1_Ubit == 1, all non-word aligned accesses cause an alignment fault. ARM/Thumb state transfers (ARM architecture version 5 and above) If bits[1:0] of a value loaded for R15 are 0b10, the result is UNPREDICTABLE, as branches to non word-aligned addresses are impossible in ARM state. Time order The time order of the accesses to individual words of memory generated by this instruction is only defined in some circumstances. See Memory access restrictions on page B2-13for details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-37
ARM Instructions
A4.1.21 LDM (2)
31 28 27 26 25 24 23 22 21 20 19 16 15 14 0
cond
100PU101
Rn
0
register_list
LDM (2) loads User mode registers when the processor is in a privileged mode. This is useful when performing process swaps, and in instruction emulators. LDM (2) loads a non-empty subset of the User mode
general-purpose registers from sequential memory locations.
Syntax
LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used.
<addressing_mode>
Is described in Addressing Mode 4 - Load and Store Multiple on page A5-41. It determines the P and U bits of the instruction. Only the forms of this addressing mode with W == 0 are available for this form of the LDM instruction.
<Rn>
Specifies the base register used by <addressing_mode>. Using R15 as <Rn> gives an UNPREDICTABLE result.
<registers_without_pc>
Is a list of registers, separated by commas and surrounded by { and }. This list must not include the PC, and specifies the set of registers to be loaded by the LDM instruction. The registers are loaded in sequence, the lowest-numbered register from the lowest memory address (start_address), through to the highest-numbered register from the highest memory address (end_address). For each of i=0 to 14, bit[i] in the register_list field of the instruction is 1 if Ri is in the list and 0 otherwise. If bits[15:0] are all zero, the result is UNPREDICTABLE.
^
For an LDM instruction that does not load the PC, this indicates that User mode registers are to be loaded.
Architecture version
All.
Exceptions
Data Abort.
A4-38
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then address = start_address for i = 0 to 14 if register_list[i] == 1 Ri_usr = Memory[address,4] address = address + 4 assert end_address == address - 4
Notes
Write-back Setting bit[21] (the W bit) has UNPREDICTABLE results.
User and System mode This form of LDM is UNPREDICTABLE in User mode or System mode. Base register mode Data Abort The base register is read from the current processor mode registers, not the User mode registers. For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Non word-aligned addresses For CP15_reg1_Ubit == 0, the Load Multiple instructions ignore the least significant two bits of the address. If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor), an address with bits[1:0] != 0b00 causes an alignment exception if alignment checking is enabled. For CP15_reg1_Ubit == 1, all non-word aligned accesses cause an alignment fault. Time order The time order of the accesses to individual words of memory generated by this instruction is only defined in some circumstances. See Memory access restrictions on page B2-13 for details. In ARM architecture versions earlier than ARMv6, this form of LDM must not be followed by an instruction that accesses banked registers. A following NOP is a good way to ensure this.
Banked registers
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-39
ARM Instructions
A4.1.22 LDM (3)
31 28 27 26 25 24 23 22 21 20 19 16 15 14 0
cond
1 0 0 PU1W1
Rn
1
register_list
LDM (3) loads a subset, or possibly all, of the general-purpose registers and the PC from sequential memory
locations. Also, the SPSR of the current mode is copied to the CPSR. This is useful for returning from an exception. The value loaded for the PC is treated as an address and a branch occurs to that address. In ARMv5 and above, and in T variants of version 4, the value copied from the SPSR T bit to the CPSR T bit determines whether execution continues after the branch in ARM state or in Thumb state (but see also The T and J bits on page A2-15 for operation on non-T variants of ARMv5). In earlier architecture versions, it continues after the branch in ARM state (the only possibility in those architecture versions).
Syntax
LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Is described in Addressing Mode 4 - Load and Store Multiple on page A5-41. It determines the P, U, and W bits of the instruction. Specifies the base register used by <addressing_mode>. Using R15 as <Rn> gives an UNPREDICTABLE result. Sets the W bit, and the instruction writes a modified value back to its base register Rn (see Addressing Mode 4 - Load and Store Multiple on page A5-41). If ! is omitted, the W bit is 0 and the instruction does not change its base register in this way. (However, if the base register is included in <registers>, it changes when a value is loaded into it.) Is a list of registers, separated by commas and surrounded by { and }. This list must include the PC, and specifies the set of registers to be loaded by the LDM instruction. The registers are loaded in sequence, the lowest-numbered register from the lowest memory address (start_address), through to the highest-numbered register from the highest memory address (end_address). For each of i=0 to 15, bit[i] in the register_list field of the instruction is 1 if Ri is in the list and 0 otherwise. For an LDM instruction that loads the PC, this indicates that the SPSR of the current mode is copied to the CPSR.
<addressing_mode>
<Rn> !
<registers_and_pc>
^
Architecture version
All.
A4-40 Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100I
ARM Instructions
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then address = start_address for i = 0 to 14 if register_list[i] == 1 then Ri = Memory[address,4] address = address + 4 if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE value = Memory[address,4] PC = value address = address + 4 assert end_address == address - 4
Notes
User and System mode This instruction is UNPREDICTABLE in User or System mode. Operand restrictions If the base register <Rn> is specified in <registers_and_pc>, and base register write-back is specified, the final value of <Rn> is UNPREDICTABLE. Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Non word-aligned addresses For CP15_reg1_Ubit == 0, the Load Multiple instructions ignore the least significant two bits of the address. If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor), an address with bits[1:0] != 0b00 causes an alignment exception if alignment checking is enabled. For CP15_reg1_Ubit == 1, all non-word aligned accesses cause an alignment fault.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-41
ARM Instructions
ARM/Thumb state transfers (ARM architecture versions 4T, 5 and above) If the SPSR T bit is 0 and bit[1] of the value loaded into the PC is 1, the results are UNPREDICTABLE because it is not possible to branch to an ARM instruction at a non word-aligned address. Note that no special precautions against this are needed on normal exception returns, because exception entries always either set the T bit of the SPSR to 1 or bit[1] of the return link value in R14 to 0. Time order The time order of the accesses to individual words of memory generated by this instruction is not defined. See Memory access restrictions on page B2-13 for details.
A4-42
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.23 LDR
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
0 1 I PU0W1
Rn
Rd
addr_mode
LDR (Load Register) loads a word from a memory address.
If the PC is specified as register <Rd>, the instruction loads a data word which it treats as an address, then branches to that address. In ARMv5T and above, bit[0] of the loaded value determines whether execution continues after this branch in ARM state or in Thumb state, as though a BX (loaded_value) instruction had been executed. In earlier versions of the architecture, bits[1:0] of the loaded value are ignored and execution continues in ARM state, as though a MOV PC,(loaded_value) instruction had been executed.
Syntax
LDR{<cond>} <Rd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the loaded value.
<Rd>
<addressing_mode>
Is described in Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18. It determines the I, P, U, W, Rn and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-43
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then if (CP15_reg1_Ubit == 0) then data = Memory[address,4] Rotate_Right (8 * address[1:0]) else /* CP15_reg_Ubit == 1 */ data = Memory[address,4] if (Rd is R15) then if (ARMv5 or above) then PC = data AND 0xFFFFFFFE T Bit = data[0] else PC = data AND 0xFFFFFFFC else Rd = data
Usage
Using the PC as the base register allows PC-relative addressing, which facilitates position-independent code. Combined with a suitable addressing mode, LDR allows 32-bit memory data to be loaded into a general-purpose register where its value can be manipulated. If the destination register is the PC, this instruction loads a 32-bit address from memory and branches to that address. To synthesize a Branch with Link, precede the LDR instruction with MOV LR, PC.
Alignment
ARMv5 and below If the address is not word-aligned, the loaded value is rotated right by 8 times the value of bits[1:0] of the address. For a little-endian memory system, this rotation causes the addressed byte to occupy the least significant byte of the register. For a big-endian memory system, it causes the addressed byte to occupy bits[31:24] or bits[15:8] of the register, depending on whether bit[0] of the address is 0 or 1 respectively. If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor), and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception. ARMv6 and above From ARMv6, a byte-invariant mixed-endian format is supported, along with an alignment-checking option. The pseudo-code for the ARMv6 case assumes that unaligned mixed-endian support is configured, with the endianness of the transfer defined by the CPSR E-bit. For more details on endianness and alignment see Endian support on page A2-30 and Unaligned access support on page A2-38.
A4-44
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Notes
Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Operand restrictions If <addressing_mode> specifies base register write-back, and the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Use of R15 If R15 is specified for <Rd>, the value of the address of the loaded value must be word aligned. That is, address[1:0] must be 0b00. In addition, for Thumb interworking reasons, R15[1:0] must not be loaded with the value 0b10. If these constraints are not met, the result is UNPREDICTABLE.
ARM/Thumb state transfers (ARM architecture version 5 and above) If bits[1:0] of a value loaded for R15 are 0b10, the result is UNPREDICTABLE, as branches to non word-aligned addresses are impossible in ARM state.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-45
ARM Instructions
A4.1.24 LDRB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
0 1 I PU1W1
Rn
Rd
addr_mode
LDRB (Load Register Byte) loads a byte from memory and zero-extends the byte to a 32-bit word.
Syntax
LDR{<cond>}B <Rd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the loaded value. If register 15 is specified for <Rd>, the result is UNPREDICTABLE.
<Rd>
<addressing_mode>
Is described in Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18. It determines the I, P, U, W, Rn and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then Rd = Memory[address,1]
A4-46
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
Combined with a suitable addressing mode, LDRB allows 8-bit memory data to be loaded into a general-purpose register where it can be manipulated. Using the PC as the base register allows PC-relative addressing, to facilitate position-independent code.
Notes
Operand restrictions If <addressing_mode> specifies base register write-back, and the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-47
ARM Instructions
A4.1.25 LDRBT
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
01I0U111
Rn
Rd
addr_mode
LDRBT (Load Register Byte with Translation) loads a byte from memory and zero-extends the byte to a 32-bit
word. If LDRBT is executed when the processor is in a privileged mode, the memory system is signaled to treat the access as if the processor were in User mode.
Syntax
LDR{<cond>}BT <Rd>, <post_indexed_addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the loaded value. If R15 is specified for <Rd>, the result is UNPREDICTABLE.
<Rd>
<post_indexed_addressing_mode>
Is described in Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18. It determines the I, U, Rn and addr_mode bits of the instruction. Only post-indexed forms of Addressing Mode 2 are available for this instruction. These forms have P == 0 and W == 0, where P and W are bit[24] and bit[21] respectively. This instruction uses P == 0 and W == 1 instead, but the addressing mode is the same in all other respects. The syntax of all forms of <post_indexed_addressing_mode> includes a base register <Rn>. All forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
Operation
if ConditionPassed(cond) then Rd = Memory[address,1] Rn = address
A4-48
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
LDRBT can be used by a (privileged) exception handler that is emulating a memory access instruction that
would normally execute in User mode. The access is restricted as if it had User mode privilege.
Notes
User mode If this instruction is executed in User mode, an ordinary User mode access is performed.
Operand restrictions If the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-49
ARM Instructions
A4.1.26 LDRD
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0 0 0 PU IW0
Rn
Rd
addr_mode 1 1 0 1 addr_mode
LDRD (Load Registers Doubleword) loads a pair of ARM registers from two consecutive words of memory. The pair of registers is restricted to being an even-numbered register and the odd-numbered register that immediately follows it (for example, R10 and R11).
A greater variety of addressing modes is available than for a two-register LDM.
Syntax
LDR{<cond>}D <Rd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the even-numbered destination register for the memory word addressed by <addressing_mode>. The immediately following odd-numbered register is the destination register for the next memory word. If <Rd> is R14, which would specify R15 as the second destination register, the instruction is UNPREDICTABLE. If <Rd> specifies an odd-numbered register, the instruction is UNDEFINED.
<Rd>
<addressing_mode>
Is described in Addressing Mode 3 - Miscellaneous Loads and Stores on page A5-33. It determines the P, U, I, W, Rn, and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back). The address generated by <addressing_mode> is the address of the lower of the two words loaded by the LDRD instruction. The address of the higher word is generated by adding 4 to this address.
Architecture version
Version 5TE and above, excluding ARMv5TExP.
Exceptions
Data Abort.
A4-50
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit)
if ConditionPassed(cond) then if (Rd is even-numbered) and (Rd is not R14) and (address[1:0] == 0b00) and ((CP15_reg1_Ubit == 1) or (address[2] == 0)) then Rd = Memory[address,4] R(d+1) = memory[address+4,4] else UNPREDICTABLE
Notes
Operand restrictions If <addressing_mode> performs base register write-back and the base register <Rn> is one of the two destination registers of the instruction, the results are UNPREDICTABLE. If <addressing_mode> specifies an index register <Rm>, and <Rm> is one of the two destination registers of the instruction, the results are UNPREDICTABLE. Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not 64-bit aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort), and support for a big-endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed-endian format is supported, along with alignment checking options; modulo4 and modulo8. The pseudo-code for the ARMv6 case assumes that unaligned mixed-endian support is configured, with the endianness of the transfer defined by the CPSR E-bit. For more details on endianness and alignment see Endian support on page A2-30 and Unaligned access support on page A2-38. Time order The time order of the accesses to the two memory words is not architecturally defined. In particular, an implementation is allowed to perform the two 32-bit memory accesses in either order, or to combine them into a single 64-bit memory access.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-51
ARM Instructions
A4.1.27 LDREX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00011001
Rn
Rd
SBO
1001
SBO
LDREX (Load Register Exclusive) loads a register from memory, and:
if the address has the Shared memory attribute, marks the physical address as exclusive access for the executing processor in a shared monitor causes the executing processor to indicate an active inclusive access in the local monitor.
Syntax
LDREX{<cond>} <Rd>, [<Rn>]
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the memory word addressed by <Rd>. Specifies the register containing the address.
<Rd> <Rn>
Architecture version
Version 6 and above.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then processor_id = ExecutingProcessor() Rd = Memory[Rn,4] physical_address = TLB(Rn) if Shared(Rn) == 1 then MarkExclusiveGlobal(physical_address,processor_id,4) MarkExclusiveLocal(physical_address,processor_id,4) /* See Summary of operation on page A2-49 */
A4-52
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
Use LDREX in combination with STREX to implement inter-process communication in shared memory multiprocessor systems. For more information see Synchronization primitives on page A2-44. The mechanism can also be used locally to ensure that an atomic load-store sequence occurs with no intervening context switch.
Notes
Use of R15 Data Abort If register 15 is specified for <Rd> or <Rn>, the result is UNPREDICTABLE. If a data abort occurs during a LDREX it is UNPREDICTABLE whether the MarkExclusiveGlobal() and MarkExclusiveLocal() operations are executed. Rd is not updated. If CP15 register 1(A,U) != (0,0) and Rd<1:0> != 0b00, an alignment exception will be taken. There is no support for unaligned Load Exclusive. If Rd<1:0> != 0b00 and (A,U) = (0,0), the result is UNPREDICTABLE. Memory support for exclusives The behavior of LDREX in regions of shared memory that do not support exclusives (for example, have no exclusives monitor implemented) is UNPREDICTABLE.
Alignment
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-53
ARM Instructions
A4.1.28 LDRH
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0 0 0 PU IW1
Rn
Rd
addr_mode 1 0 1 1 addr_mode
LDRH (Load Register Halfword) loads a halfword from memory and zero-extends it to a 32-bit word.
Syntax
LDR{<cond>}H <Rd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the loaded value. If R15 is specified for <Rd>, the result is UNPREDICTABLE.
<Rd>
<addressing_mode>
Is described in Addressing Mode 3 - Miscellaneous Loads and Stores on page A5-33. It determines the P, U, I, W, Rn and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
A4-54
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then if (CP15_reg1_Ubit == 0) then if address[0] == 0 then data = Memory[address,2] else data = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ data = Memory[address,2] Rd = ZeroExtend(data[15:0])
Usage
Used with a suitable addressing mode, LDRH allows 16-bit memory data to be loaded into a general-purpose register where its value can be manipulated. Using the PC as the base register allows PC-relative addressing to facilitate position-independent code.
Notes
Operand restrictions If <addressing_mode> specifies base register write-back, and the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not halfword aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort when address[0] != 0), and support for a big-endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed-endian format is supported, along with an alignment checking option. The pseudo-code for the ARMv6 case assumes that mixed-endian support is configured, with the endianness of the transfer defined by the CPSR E-bit. For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-55
ARM Instructions
A4.1.29 LDRSB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0 0 0 PU IW1
Rn
Rd
addr_mode 1 1 0 1 addr_mode
LDRSB (Load Register Signed Byte) loads a byte from memory and sign-extends the byte to a 32-bit word.
Syntax
LDR{<cond>}SB <Rd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the loaded value. If R15 is specified for <Rd>, the result is UNPREDICTABLE.
<Rd>
<addressing_mode>
Is described in Addressing Mode 3 - Miscellaneous Loads and Stores on page A5-33. It determines the P, U, I, W, Rn and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
Version 4 and above.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then data = Memory[address,1] Rd = SignExtend(data)
A4-56
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
Use LDRSB with a suitable addressing mode to load 8-bit signed memory data into a general-purpose register where it can be manipulated. You can perform PC-relative addressing by using the PC as the base register. This facilitates position-independent code.
Notes
Operand restrictions If <addressing_mode> specifies base register write-back, and the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-57
ARM Instructions
A4.1.30 LDRSH
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0 0 0 PU IW1
Rn
Rd
addr_mode 1 1 1 1 addr_mode
LDRSH (Load Register Signed Halfword) loads a halfword from memory and sign-extends the halfword to a 32-bit word.
If the address is not halfword-aligned, the result is UNPREDICTABLE.
Syntax
LDR{<cond>}SH <Rd>, <addressing_mode>
where:
<cond> <Rd>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the loaded value. If R15 is specified for <Rd>, the result is UNPREDICTABLE. Is described in Addressing Mode 3 - Miscellaneous Loads and Stores on page A5-33. It determines the P, U, I, W, Rn and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
<addressing_mode>
Architecture version
Version 4 and above.
Exceptions
Data Abort.
A4-58
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then if (CP15_reg1_Ubit == 0) then if address[0] == 0 then data = Memory[address,2] else data = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ data = Memory[address,2] Rd = SignExtend(data[15:0])
Usage
Used with a suitable addressing mode, LDRSH allows 16-bit signed memory data to be loaded into a general-purpose register where its value can be manipulated. Using the PC as the base register allows PC-relative addressing, which facilitates position-independent code.
Notes
Operand restrictions If <addressing_mode> specifies base register write-back, and the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not halfword aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort when address[0] != 0), and support for a big-endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed-endian format is supported, along with an alignment checking option. The pseudo-code for the ARMv6 case assumes that mixed-endian support is configured, with the endianness of the transfer defined by the CPSR E-bit. For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-59
ARM Instructions
A4.1.31 LDRT
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
01I0U011
Rn
Rd
addr_mode
LDRT (Load Register with Translation) loads a word from memory.
If LDRT is executed when the processor is in a privileged mode, the memory system is signaled to treat the access as if the processor were in User mode.
Syntax
LDR{<cond>}T <Rd>, <post_indexed_addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the loaded value. If R15 is specified for <Rd>, the result is UNPREDICTABLE.
<Rd>
<post_indexed_addressing_mode>
Is described in Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18. It determines the I, U, Rn and addr_mode bits of the instruction. Only post-indexed forms of Addressing Mode 2 are available for this instruction. These forms have P == 0 and W == 0, where P and W are bit[24] and bit[21] respectively. This instruction uses P == 0 and W == 1 instead, but the addressing mode is the same in all other respects. The syntax of all forms of <post_indexed_addressing_mode> includes a base register <Rn>. All forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
A4-60
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then if (CP15_reg1_Ubit == 0) then Rd = Memory[address,4] Rotate_Right (8 * address[1:0]) else /* CP15_reg1_Ubit == 1 */ Rd = Memory[address,4]
Usage
LDRT can be used by a (privileged) exception handler that is emulating a memory access instruction that
would normally execute in User mode. The access is restricted as if it had User mode privilege.
Notes
User mode If this instruction is executed in User mode, an ordinary User mode access is performed.
Operand restrictions If the same register is specified for <Rd> and <Rn> the results are UNPREDICTABLE. Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. As for LDR, see LDR on page A4-43.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-61
ARM Instructions
A4.1.32 MCR
31 28 27 26 25 24 23 21 20 19 16 15 12 11 8 7 543 0
cond
1 1 1 0 opcode_1 0
CRn
Rd
cp_num
opcode_2 1
CRm
MCR (Move to Coprocessor from ARM Register) passes the value of register <Rd> to the coprocessor whose number is cp_num.
If no coprocessors indicate that they can execute the instruction, an Undefined Instruction exception is generated.
Syntax
MCR{<cond>} MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the condition field of the instruction to be set to 0b1111. This provides additional opcode space for coprocessor designers. The resulting instructions can only be executed unconditionally. Specifies the name of the coprocessor, and causes the corresponding coprocessor number to be placed in the cp_num field of the instruction. The standard generic coprocessor names are p0, p1, ..., p15. Is a coprocessor-specific opcode. Is the ARM register whose value is transferred to the coprocessor. If R15 is specified for <Rd>, the result is UNPREDICTABLE. Is the destination coprocessor register. Is an additional destination or source coprocessor register. Is a coprocessor-specific opcode. If it is omitted, <opcode_2> is assumed to be 0.
MCR2
<coproc>
<opcode_1> <Rd>
<CRn> <CRm> <opcode_2>
Architecture version
MCR is in all versions. MCR2 is in version 5 and above.
Exceptions
Undefined Instruction.
A4-62
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then send Rd value to Coprocessor[cp_num]
Usage
Use MCR to initiate a coprocessor operation that acts on a value from an ARM register. An example is a fixed-point to floating-point conversion instruction for a floating-point coprocessor.
Notes
Coprocessor fields Only instruction bits[31:24], bit[20], bits[15:8], and bit[4] are defined by the ARM architecture. The remaining fields are recommendations, for compatibility with ARM Development Systems.
Unimplemented coprocessor instructions Hardware coprocessor support is optional for coprocessors 0-13, regardless of the architecture version, and is optional for coprocessors 14 and 15 before ARMv6. An implementation can choose to implement a subset of the coprocessor instructions, or no coprocessor instructions at all. Any coprocessor instructions that are not implemented instead cause an Undefined Instruction exception.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-63
ARM Instructions
A4.1.33 MCRR
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 43 0
cond
11000100
Rn
Rd
cp_num
opcode
CRm
MCRR (Move to Coprocessor from two ARM Registers) passes the values of two ARM registers to a
coprocessor. If no coprocessors indicate that they can execute the instruction, an Undefined Instruction exception is generated.
Syntax
MCRR{<cond>} <coproc>, <opcode>, <Rd>, <Rn>, <CRm> MCRR2 <coproc>, <opcode>, <Rd>, <Rn>, <CRm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the condition field of the instruction to be set to 0b1111. This provides additional opcode space for coprocessor designers. The resulting instructions can only be executed unconditionally. Specifies the name of the coprocessor, and causes the corresponding coprocessor number to be placed in the cp_num field of the instruction. The standard generic coprocessor names are p0, p1, , p15. Is a coprocessor-specific opcode. Is the first ARM register whose value is transferred to the coprocessor. If R15 is specified for <Rd>, the result is UNPREDICTABLE. Is the second ARM register whose value is transferred to the coprocessor. If R15 is specified for <Rn>, or Rn = Rd, the result is UNPREDICTABLE. Is the destination coprocessor register.
MCRR2
<coproc>
<opcode> <Rd>
<Rn>
<CRm>
Architecture version
MCRR is in version 5TE and above, excluding ARMv5TExP. MCRR2 is in version 6 and above.
Exceptions
Undefined Instruction.
A4-64
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then send Rd value to Coprocessor[cp_num] send Rn value to Coprocessor[cp_num]
Usage
Use MCRR to initiate a coprocessor operation that acts on values from two ARM registers. An example for a floating-point coprocessor is an instruction to transfer a double-precision floating-point number held in two ARM registers to a floating-point register.
Notes
Coprocessor fields Only instruction bits[31:8] are defined by the ARM architecture. The remaining fields are recommendations, for compatibility with ARM Development Systems. Unimplemented coprocessor instructions Hardware coprocessor support is optional for coprocessors 0-13, regardless of the architecture version, and is optional for coprocessors 14 and 15 before ARMv6. An implementation can choose to implement a subset of the coprocessor instructions, or no coprocessor instructions at all. Any coprocessor instructions that are not implemented instead cause an Undefined Instruction exception. Order of transfers If a coprocessor uses these instructions, it defines how each of the values of <Rd> and <Rn> is used. There is no architectural requirement for the two register transfers to occur in any particular time order. It is IMPLEMENTATION DEFINED whether Rd is transferred before Rn, after Rn, or at the same time as Rn.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-65
ARM Instructions
A4.1.34 MLA
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0000001S
Rd
Rn
Rs
1001
Rm
MLA (Multiply Accumulate) multiplies two signed or unsigned 32-bit values, and adds a third 32-bit value. The least significant 32 bits of the result are written to the destination register. MLA can optionally update the condition code flags, based on the result.
Syntax
MLA{<cond>}{S} <Rd>, <Rm>, <Rs>, <Rn>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction updates the CPSR by setting the N and Z flags according to the result of the multiply-accumulate. If S is omitted, the S bit of the instruction is set to 0 and the entire CPSR is unaffected by the instruction. Specifies the destination register. Holds the value to be multiplied with the value of <Rs>. Holds the value to be multiplied with the value of <Rm>. Contains the value that is added to the product of <Rs> and <Rm>.
S
<Rd> <Rm> <Rs> <Rn>
Architecture version
All.
Exceptions
None.
A4-66
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then Rd = (Rm * Rs + Rn)[31:0] if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = unaffected in v5 and above, UNPREDICTABLE in v4 and earlier V Flag = unaffected
Notes
Use of R15 Early termination Specifying R15 for register <Rd>, <Rm>, <Rs>, or <Rn> has UNPREDICTABLE results. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
Signed and unsigned The MLA instruction produces only the lower 32 bits of the 64-bit product. Therefore, MLA gives the same answer for multiplication of both signed and unsigned numbers. C flag The MLAS instruction is defined to leave the C flag unchanged in ARMv5 and above. In earlier versions of the architecture, the value of the C flag was UNPREDICTABLE after an MLAS instruction.
Operand restriction Specifying the same register for <Rd> and <Rm> was previously described as producing UNPREDICTABLE results. There is no restriction in ARMv6, and it is believed that all relevant ARMv4 and ARMv5 implementations do not require this restriction either, because high performance multipliers read all their operands prior to writing back any results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-67
ARM Instructions
A4.1.35 MOV
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I1101S
SBZ
Rd
shifter_operand
MOV (Move) writes a value to the destination register. The value can be either an immediate value or a value
from a register, and can be shifted before the write.
MOV can optionally update the condition code flags, based on the result.
Syntax
MOV{<cond>}{S} <Rd>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Sets the S bit (bit[20]) in the instruction to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the value moved (post-shift if a shift is specified), and the C flag is set to the carry output bit generated by the shifter (see Addressing Mode 1 - Data-processing operands on page A5-2). The V flag and the rest of the CPSR are unaffected. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd>
Specifies the destination register.
<shifter_operand>
Specifies the operand. The options for this operand are described in Addressing Mode 1 Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not MOV. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
Exceptions
None.
A4-68
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then Rd = shifter_operand if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = shifter_carry_out V Flag = unaffected
Usage
Use MOV to: Move a value from one register to another. Put a constant value into a register. Perform a shift without any other arithmetic or logical operation. Use a left shift by n to multiply by 2n. When the PC is the destination of the instruction, a branch occurs. The instruction:
MOV PC, LR
can therefore be used to return from a subroutine (see instructions B, BL on page A4-10). In T variants of architecture 4 and in architecture 5 and above, the instruction BX LR must be used in place of MOV PC, LR, as the BX instruction automatically switches back to Thumb state if appropriate (but see also The T and J bits on page A2-15 for operation on non-T variants of ARM architecture version 5). When the PC is the destination of the instruction and the S bit is set, a branch occurs and the SPSR of the current mode is copied to the CPSR. This means that you can use a MOVS PC, LR instruction to return from some types of exception (see Exceptions on page A2-16).
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-69
ARM Instructions
A4.1.36 MRC
31 28 27 26 25 24 23 21 20 19 16 15 12 11 8 7 543 0
cond
1 1 1 0 opcode_1 1
CRn
Rd
cp_num
opcode_2 1
CRm
MRC (Move to ARM Register from Coprocessor) causes a coprocessor to transfer a value to an ARM register
or to the condition flags. If no coprocessors can execute the instruction, an Undefined Instruction exception is generated.
Syntax
MRC{<cond>} MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the condition field of the instruction to be set to 0b1111. This provides additional opcode space for coprocessor designers. The resulting instructions can only be executed unconditionally. Specifies the name of the coprocessor, and causes the corresponding coprocessor number to be placed in the cp_num field of the instruction. The standard generic coprocessor names are p0, p1, ..., p15. Is a coprocessor-specific opcode. Specifies the destination ARM register for the instruction. If R15 is specified for <Rd>, the condition code flags are updated instead of a general-purpose register. Specifies the coprocessor register that contains the first operand. Is an additional coprocessor source or destination register. Is a coprocessor-specific opcode. If it is omitted, <opcode_2> is assumed to be 0.
MRC2
<coproc>
<opcode_1> <Rd>
<CRn> <CRm> <opcode_2>
Architecture version
MRC is in all versions. MRC2 is in version 5 and above.
Exceptions
Undefined Instruction.
A4-70
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then data = value from Coprocessor[cp_num] if Rd is R15 then N flag = data[31] Z flag = data[30] C flag = data[29] V flag = data[28] else /* Rd is not R15 */ Rd = data
Usage
MRC has two uses:
1.
If <Rd> specifies R15, the condition code flags bits are updated from the top four bits of the value from the coprocessor specified by <coproc> (to allow conditional branching on the status of a coprocessor) and the other 28 bits are ignored. An example of this use would be to transfer the result of a comparison performed by a floating-point coprocessor to the ARM's condition flags.
2.
Otherwise the instruction writes into register <Rd> a value from the coprocessor specified by <coproc>. An example of this use is a floating-point to integer conversion instruction in a floating-point coprocessor.
Notes
Coprocessor fields Only instruction bits[31:24], bit[20], bits[15:8] and bit[4] are defined by the ARM architecture. The remaining fields are recommendations, for compatibility with ARM Development Systems.
Unimplemented coprocessor instructions Hardware coprocessor support is optional for coprocessors 0-13, regardless of the architecture version, and is optional for coprocessors 14 and 15 before ARMv6. An implementation can choose to implement a subset of the coprocessor instructions, or no coprocessor instructions at all. Any coprocessor instructions that are not implemented instead cause an Undefined Instruction exception.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-71
ARM Instructions
A4.1.37 MRRC
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 43 0
cond
11000101
Rn
Rd
cp_num
opcode
CRm
MRRC (Move to two ARM registers from Coprocessor) causes a coprocessor to transfer values to two ARM
registers. If no coprocessors can execute the instruction, an Undefined Instruction exception is generated.
Syntax
MRRC{<cond>} <coproc>, <opcode>, <Rd>, <Rn>, <CRm> MRRC2 <coproc>, <opcode>, <Rd>, <Rn>, <CRm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the condition field of the instruction to be set to 0b1111. This provides additional opcode space for coprocessor designers. The resulting instructions can only be executed unconditionally. Specifies the name of the coprocessor, and causes the corresponding coprocessor number to be placed in the cp_num field of the instruction. The standard generic coprocessor names are p0, p1, , p15. Is a coprocessor-specific opcode. Is the first destination ARM register. If R15 is specified for <Rd>, the result is
UNPREDICTABLE.
MRRC2
<coproc>
<opcode> <Rd>
<Rn>
Is the second destination ARM register. If R15 is specified for <Rn>, the result is
UNPREDICTABLE.
<CRm>
Is the coprocessor register which supplies the data to be transferred.
Architecture version
MRRC is in version 5TE and above, excluding ARMv5TExP. MRRC2 is in version 6 and above.
Exceptions
Undefined Instruction.
A4-72
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then Rd = first value from Coprocessor[cp_num] Rn = second value from Coprocessor[cp_num]
Usage
Use MRRC to initiate a coprocessor operation that writes values to two ARM registers. An example for a floating-point coprocessor is an instruction to transfer a double-precision floating-point number held in a floating-point register to two ARM registers.
Notes
Operand restrictions Specifying the same register for <Rd> and <Rn> has UNPREDICTABLE results. Coprocessor fields Only instruction bits[31:8] are defined by the ARM architecture. The remaining fields are recommendations, for compatibility with ARM Development Systems. Unimplemented coprocessor instructions Hardware coprocessor support is optional for coprocessors 0-13, regardless of the architecture version, and is optional for coprocessors 14 and 15 before ARMv6. An implementation can choose to implement a subset of the coprocessor instructions, or no coprocessor instructions at all. Any coprocessor instructions that are not implemented instead cause an Undefined Instruction exception. Order of transfers If a coprocessor uses these instructions, it defines which value is written to <Rd> and which value to <Rn>. There is no architectural requirement for the two register transfers to occur in any particular time order. It is IMPLEMENTATION DEFINED whether Rd is transferred before Rn, after Rn, or at the same time as Rn.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-73
ARM Instructions
A4.1.38 MRS
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00010R00
SBO
Rd
SBZ
MRS (Move PSR to general-purpose register) moves the value of the CPSR or the SPSR of the current mode
into a general-purpose register. In the general-purpose register, the value can be examined or manipulated with normal data-processing instructions.
Syntax
MRS{<cond>} MRS{<cond>} <Rd>, CPSR <Rd>, SPSR
where:
<cond> <Rd>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. If R15 is specified for <Rd>, the result is UNPREDICTABLE.
Architecture version
All.
Exceptions
None.
Operation
if ConditionPassed(cond) then if R == 1 then Rd = SPSR else Rd = CPSR
A4-74
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
The MRS instruction is commonly used for three purposes: As part of a read/modify/write sequence for updating a PSR. For more details, see MSR on page A4-76. When an exception occurs and there is a possibility of a nested exception of the same type occurring, the SPSR of the exception mode is in danger of being corrupted. To deal with this, the SPSR value must be saved before the nested exception can occur, and later restored in preparation for the exception return. The saving is normally done by using an MRS instruction followed by a store instruction. Restoring the SPSR uses the reverse sequence of a load instruction followed by an MSR instruction. In process swap code, the programmers model state of the process being swapped out must be saved, including relevant PSR contents, and similar state of the process being swapped in must be restored. Again, this involves the use of MRS/store and load/MSR instruction sequences.
Notes
User mode SPSR Accessing the SPSR when in User mode or System mode is UNPREDICTABLE.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-75
ARM Instructions
A4.1.39 MSR
Immediate operand:
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 0
cond
0 0 1 1 0 R 1 0 field_mask
SBO
rotate_imm
8_bit_immediate
Register operand:
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0 0 0 1 0 R 1 0 field_mask
SBO
SBZ
0000
Rm
MSR (Move to Status Register from ARM Register) transfers the value of a general-purpose register or an immediate constant to the CPSR or the SPSR of the current mode.
Syntax
MSR{<cond>} MSR{<cond>} MSR{<cond>} MSR{<cond>} CPSR_<fields>, CPSR_<fields>, SPSR_<fields>, SPSR_<fields>, #<immediate> <Rm> #<immediate> <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Is a sequence of one or more of the following: c sets the control field mask bit (bit 16) x sets the extension field mask bit (bit 17) s sets the status field mask bit (bit 18) f sets the flags field mask bit (bit 19). Is the immediate value to be transferred to the CPSR or SPSR. Allowed immediate values are 8-bit immediates (in the range 0x00 to 0xFF) and values that can be obtained by rotating them right by an even amount in the range 0 to 30. These immediate values are the same as those allowed in the immediate form as shown in Data-processing operands - Immediate on page A5-6. Is the general-purpose register to be transferred to the CPSR or SPSR.
<fields>
<immediate>
<Rm>
Architecture version
All.
A4-76
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
None.
Operation
There are four categories of PSR bits, according to rules about updating them, see Types of PSR bits on page A2-11 for details. The pseudo-code uses four bit mask constants to identify these categories of PSR bits. The values of these masks depend on the architecture version, see Table A4-1. Table A4-1 Bit mask constants Architecture versions 4 4T, 5T 5TE, 5TExP 5TEJ 6 UnallocMask
0x0FFFFF20 0x0FFFFF00 0x07FFFF00 0x06FFFF00 0x06F0FC00
UserMask
0xF0000000 0xF0000000 0xF8000000 0xF8000000 0xF80F0200
PrivMask
0x0000000F 0x0000000F 0x0000000F 0x0000000F 0x000001DF
StateMask
0x00000000 0x00000020 0x00000020 0x01000020 0x01000020
if ConditionPassed(cond) then if opcode[25] == 1 then operand = 8_bit_immediate Rotate_Right (rotate_imm * 2) else operand = Rm if (operand AND UnallocMask) !=0 then UNPREDICTABLE /* Attempt to set reserved bits */ byte_mask = (if field_mask[0] == 1 then 0x000000FF else 0x00000000) OR (if field_mask[1] == 1 then 0x0000FF00 else 0x00000000) OR (if field_mask[2] == 1 then 0x00FF0000 else 0x00000000) OR (if field_mask[3] == 1 then 0xFF000000 else 0x00000000) if R == 0 then if InAPrivilegedMode() then if (operand AND StateMask) != 0 then UNPREDICTABLE /* Attempt to set non-ARM execution state */ else mask = byte_mask AND (UserMask OR PrivMask) else mask = byte_mask AND UserMask CPSR = (CPSR AND NOT mask) OR (operand AND mask) else /* R == 1 */ if CurrentModeHasSPSR() then mask = byte_mask AND (UserMask OR PrivMask OR StateMask) SPSR = (SPSR AND NOT mask) OR (operand AND mask) else UNPREDICTABLE
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-77
ARM Instructions
Usage
Use MSR to update the value of the condition code flags, interrupt enables, or the processor mode. You must normally update the value of a PSR by moving the PSR to a general-purpose register (using the
MRS instruction), modifying the relevant bits of the general-purpose register, and restoring the updated general-purpose register value back into the PSR (using the MSR instruction). For example, a good way to
switch the ARM to Supervisor mode from another privileged mode is:
MRS BIC ORR MSR R0,CPSR R0,R0,#0x1F R0,R0,#0x13 CPSR_c,R0 ; ; ; ; Read CPSR Modify by removing current mode and substituting Supervisor mode Write the result back to CPSR
For maximum efficiency, MSR instructions should only write to those fields that they can potentially change. For example, the last instruction in the above code can only change the CPSR control field, as all bits in the other fields are unchanged since they were read from the CPSR by the first instruction. So it writes to CPSR_c, not CPSR_fsxc or some other combination of fields. However, if the only reason that an MSR instruction cannot change a field is that no bits are currently allocated to the field, then the field must be written, to ensure future compatibility. You can use the immediate form of MSR to set any of the fields of a PSR, but you must take care to use the read-modify-write technique described above. The immediate form of the instruction is equivalent to reading the PSR concerned, replacing all the bits in the fields concerned by the corresponding bits of the immediate constant and writing the result back to the PSR. The immediate form must therefore only be used when the intention is to modify all the bits in the specified fields and, in particular, must not be used if the specified fields include any as-yet-unallocated bits. Failure to observe this rule might result in code which has unanticipated side effects on future versions of the ARM architecture. As an exception to the above rule, it is legitimate to use the immediate form of the instruction to modify the flags byte, despite the fact that bits[26:25] of the PSRs have no allocated function at present. For example, you can use MSR to set all four flags (and clear the Q flag if the processor implements the Enhanced DSP extension):
MSR CPSR_f,#0xF0000000
Any functionality allocated to bits[26:25] in a future version of the ARM architecture will be designed so that such code does not have unexpected side effects. Several bits must not be changed to reserved values or the results are UNPREDICTABLE. For example, an attempt to write a reserved value to the mode bits (4:0), or changing the J-bit (24).
A4-78
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Notes
The R bit Bit[22] of the instruction is 0 if the CPSR is to be written and 1 if the SPSR is to be written.
User mode CPSR Any writes to privileged or execution state bits are ignored. User mode SPSR Accessing the SPSR when in User mode is UNPREDICTABLE. System mode SPSR Accessing the SPSR when in System mode is UNPREDICTABLE. Obsolete field specification The CPSR, CPSR_flg, CPSR_ctl, CPSR_all, SPSR, SPSR_flg, SPSR_ctl and SPSR_all forms of PSR field specification have been superseded by the csxf format shown on page A4-76.
CPSR, SPSR, CPSR_all and SPSR_all produce a field mask of 0b1001. CPSR_flg and SPSR_flg produce a field mask of 0b1000. CPSR_ctl and SPSR_ctl produce a field mask of 0b0001.
The T bit or J bit The MSR instruction must not be used to alter the T bit or the J bit in the CPSR. If such an attempt is made, the results are UNPREDICTABLE. Addressing modes The immediate and register forms are specified in precisely the same way as the immediate and unshifted register forms of Addressing Mode 1 (see Addressing Mode 1 Data-processing operands on page A5-2). All other forms of Addressing Mode 1 yield UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-79
ARM Instructions
A4.1.40 MUL
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0000000S
Rd
SBZ
Rs
1001
Rm
MUL (Multiply) multiplies two signed or unsigned 32-bit values. The least significant 32 bits of the result are
written to the destination register.
MUL can optionally update the condition code flags, based on the result.
Syntax
MUL{<cond>}{S} <Rd>, <Rm>, <Rs>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction updates the CPSR by setting the N and Z flags according to the result of the multiplication. If S is omitted, the S bit of the instruction is set to 0 and the entire CPSR is unaffected by the instruction. Specifies the destination register for the instruction. Specifies the register that contains the first value to be multiplied. Holds the value to be multiplied with the value of <Rm>.
S
<Rd> <Rm> <Rs>
Architecture version
All.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = (Rm * Rs)[31:0] if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = unaffected in v5 and above, UNPREDICTABLE in v4 and earlier V Flag = unaffected
A4-80
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Notes
Use of R15 Early termination Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
Signed and unsigned Because the MUL instruction produces only the lower 32 bits of the 64-bit product, MUL gives the same answer for multiplication of both signed and unsigned numbers. C flag The MULS instruction is defined to leave the C flag unchanged in ARM architecture version 5 and above. In earlier versions of the architecture, the value of the C flag was UNPREDICTABLE after a MULS instruction.
Operand restriction Specifying the same register for <Rd> and <Rm> was previously described as producing UNPREDICTABLE results. There is no restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 implementations do not require this restriction either, because high performance multipliers read all their operands prior to writing back any results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-81
ARM Instructions
A4.1.41 MVN
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I1111S
SBZ
Rd
shifter_operand
MVN (Move Not) generates the logical ones complement of a value. The value can be either an immediate
value or a value from a register, and can be shifted before the MVN operation.
MVN can optionally update the condition code flags, based on the result.
Syntax
MVN{<cond>}{S} <Rd>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Sets the S bit (bit[20]) in the instruction to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the operation, and the C flag is set to the carry output bit generated by the shifter (see Addressing Mode 1 - Data-processing operands on page A5-2). The V flag and the rest of the CPSR are unaffected. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd>
Specifies the destination register.
<shifter_operand>
Specifies the operand. The options for this operand are described in Addressing Mode 1 Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not MVN. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
Exceptions
None.
A4-82
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then Rd = NOT shifter_operand if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = shifter_carry_out V Flag = unaffected
Usage
Use MVN to: form a bit mask take the ones complement of a value.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-83
ARM Instructions
A4.1.42 ORR
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I1100S
Rn
Rd
shifter_operand
ORR (Logical OR) performs a bitwise (inclusive) OR of two values. The first value comes from a register.
The second value can be either an immediate value or a value from a register, and can be shifted before the OR operation.
ORR can optionally update the condition code flags, based on the result.
Syntax
ORR{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Sets the S bit (bit[20]) in the instruction to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the operation, and the C flag is set to the carry output bit generated by the shifter (see Addressing Mode 1 - Data-processing operands on page A5-2). The V flag and the rest of the CPSR are unaffected. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the first operand.
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not ORR. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
A4-84
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = Rn OR shifter_operand if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = shifter_carry_out V Flag = unaffected
Usage
Use ORR to set selected bits in a register. For each bit, OR with 1 sets the bit, and OR with 0 leaves it unchanged.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-85
ARM Instructions
A4.1.43 PKHBT
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 76 43 0
cond
01101000
Rn
Rd
shift_imm
001
Rm
PKHBT (Pack Halfword Bottom Top) combines the bottom (least significant) halfword of its first operand with
the top (most significant) halfword of its shifted second operand. The shift is a left shift, by any amount from 0 to 31.
Syntax
PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Bits[15:0] of this operand become bits[15:0] of the result of the operation. Specifies the register that contains the second operand. This is shifted left by the specified amount, then bits[31:16] of this operand become bits[31:16] of the result of the operation. Specifies the amount by which <Rm> is to be shifted left. This is a value from 0 to 31. If the shift specifier is omitted, a left shift by 0 is used.
<Rd> <Rn>
<Rm>
<shift_imm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15:0] = Rn[15:0] Rd[31:16] = (Rm Logical_Shift_Left shift_imm)[31:16]
A4-86
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
To construct the word in Rd consisting of the top half of register Ra and the bottom half of register Rb as its most and least significant halfwords respectively, use:
PKHBT Rd, Rb, Ra
To construct the word in Rd consisting of the bottom half of register Ra and the bottom half of register Rb as its most and least significant halfwords respectively, use:
PKHBT Rd, Rb, Ra, LSL #16
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-87
ARM Instructions
A4.1.44 PKHTB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 76 43 0
cond
01101000
Rn
Rd
shift_imm
101
Rm
PKHTB (Pack Halfword Top Bottom) combines the top (most significant) halfword of its first operand with the bottom (least significant) halfword of its shifted second operand. The shift is an arithmetic right shift, by any amount from 1 to 32.
Syntax
PKHTB {<cond>} <Rd>, <Rn>, <Rm> {, ASR #<shift_imm>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Bits[31:16] of this operand become bits[31:16] of the result of the operation. Specifies the register that contains the second operand. This is shifted right arithmetically by the specified amount, then bits[15:0] of this operand become bits[15:0] of the result of the operation. Specifies the amount by which <Rm> is to be shifted right. A shift by 32 is encoded as shift_imm == 0. If the shift specifier is omitted, the assembler converts the instruction to PKHBT Rd,
Rm, Rn. This produces the same effect as an arithmetic shift right by 0.
<Rd> <Rn>
<Rm>
<shift_imm>
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ASR #0 here. It is equivalent to omitting the shift specifier.
Architecture version
Version 6 and above.
Exceptions
None.
A4-88
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if shift_imm == 0 then /* ASR #32 case */ if Rm[31] == 0 then Rd[15:0] = 0x0000 else Rd[15:0] = 0xFFFF else Rd[15:0] = (Rm Arithmetic_Shift_Right shift_imm)[15:0] Rd[31:16] = Rn[31:16]
Usage
To construct the word in Rd consisting of the top half of register Ra and the top half of register Rb as its most and least significant halfwords respectively, use:
PKHTB Rd, Ra, Rb, ASR #16
You can use this to truncate a Q31 number in Rb, and put the result into the bottom half of Rd. You can scale the Rb value by using a different shift amount. To construct the word in Rd consisting of the top half of register Ra and the bottom half of register Rb as its most and least significant halfwords respectively, you can use:
PKHTB Rd, Ra, Rb
The assembler converts this into:
PKHBT Rd, Rb, Ra
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-89
ARM Instructions
A4.1.45 PLD
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 14 13 12 11 0
111101I1U101
Rn
1111
addr_mode
PLD (Preload Data) signals the memory system that memory accesses from a specified address are likely in
the near future. The memory system can respond by taking actions which are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the cache. PLD is a hint instruction, aimed at optimizing memory system performance. It has no architecturally-defined effect, and memory systems that do not support this optimization can ignore it. On such memory systems, PLD acts as a NOP.
Syntax
PLD <addressing_mode>
where:
<addressing_mode>
Is described in Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18. It specifies the I, U, Rn, and addr_mode bits of the instruction. Only addressing modes with P == 1 and W == 0 are available for this instruction. Pre-indexed and post-indexed addressing modes have P == 0 or W == 1 and so are not available.
Architecture version
Version 5TE and above, excluding ARMv5TExP.
Exceptions
None.
Operation
/* No change occurs to programmer's model state, but where * appropriate, the memory system is signaled that memory accesses * to the specified address are likely in the near future. */
A4-90
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Notes
Condition Write-back Data Aborts Unlike most other ARM instructions, PLD cannot be executed conditionally. Clearing bit[24] (the P bit) or setting bit[21] (the W bit) has UNPREDICTABLE results. This instruction never signals a precise Data Abort generated by the VMSA MMU, PMSA MPU or by the rest of the memory system. Other memory system exceptions caused as a side-effect of this operation might be reported using an imprecise Data Abort or by some other exception mechanism. There are no alignment restrictions on the address generated by <addressing_mode>. If an implementation contains a System Control coprocessor (see Chapter B3 The System Control Coprocessor), it must not generate an alignment exception for any PLD instruction.
Alignment
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-91
ARM Instructions
A4.1.46 QADD
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00010000
Rn
Rd
SBZ
0101
Rm
QADD (Saturating Add) performs integer addition. It saturates the result to the 32-bit signed integer range 231
x 231 1. If saturation occurs, QADD sets the Q flag in the CPSR.
Syntax
QADD{<cond>} <Rd>, <Rm>, <Rn>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rm> <Rn>
Architecture version
Version 5TE and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = SignedSat(Rm + Rn, 32) if SignedDoesSat(Rm + Rn, 32) then Q Flag = 1
A4-92
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
As well as performing saturated integer and Q31 additions, you can use QADD in combination with an SMUL<x><y>, SMULW<y>, or SMULL instruction to produce multiplications of Q15 and Q31 numbers. Three examples are: To multiply the Q15 numbers in the bottom halves of R0 and R1 and place the Q31 result in R2, use:
SMULBB QADD R2, R0, R1 R2, R2, R2
To multiply the Q31 number in R0 by the Q15 number in the top half of R1 and place the Q31 result in R2, use:
SMULWT QADD R2, R0, R1 R2, R2, R2
To multiply the Q31 numbers in R0 and R1 and place the Q31 result in R2, use:
SMULL QADD R3, R2, R0, R1 R2, R2, R2
Notes
Use of R15 Condition flags Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
QADD does not affect the N, Z, C, or V flags.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-93
ARM Instructions
A4.1.47 QADD16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100010
Rn
Rd
SBO
0001
Rm
QADD16 performs two 16-bit integer additions. It saturates the results to the 16-bit signed integer range
215 x 215 1.
QADD16 does not affect any flags.
Syntax
QADD16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15:0] = SignedSat(Rn[15:0] + Rm[15:0], 16) Rd[31:16] = SignedSat(Rn[31:16] + Rm[31:16], 16)
Usage
Use QADD16 in similar ways to the SADD16 instruction, but for signed saturated arithmetic. QADD16 does not set the GE bits for use with SEL. See SADD16 on page A4-119 for more details.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-94
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.48 QADD8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100010
Rn
Rd
SBO
1001
Rm
QADD8 performs four 8-bit integer additions. It saturates the results to the 8-bit signed integer range
27 x 27 1.
QADD8 does not affect any flags.
Syntax
QADD8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[7:0] = SignedSat(Rn[7:0] Rd[15:8] = SignedSat(Rn[15:8] Rd[23:16] = SignedSat(Rn[23:16] Rd[31:24] = SignedSat(Rn[31:24] + + + + Rm[7:0], Rm[15:8], Rm[23:16], Rm[31:24], 8) 8) 8) 8)
Usage
Use QADD8 in similar ways to the SADD8 instruction, but for signed saturated arithmetic. QADD8 does not set the GE bits for use with SEL. See SADD8 on page A4-121 for more details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-95
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-96
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.49 QADDSUBX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100010
Rn
Rd
SBO
0011
Rm
QADDSUBX (Saturating Add and Subtract with Exchange) performs one 16-bit integer addition and one 16-bit
subtraction. It saturates the results to the 16-bit signed integer range 215 x 215 1. QADDSUBX exchanges the two halfwords of the second operand before it performs the arithmetic.
QADDSUBX does not affect any flags.
Syntax
QADDSUBX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[31:16] = SignedSat(Rn[31:16] + Rm[15:0], 16) Rd[15:0] = SignedSat(Rn[15:0] - Rm[31:16], 16)
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-97
ARM Instructions
Usage
You can use QADDSUBX for operations on complex numbers that are held as pairs of 16-bit integers or Q15 numbers. If you hold the real and imaginary parts of a complex number in the bottom and top half of a register respectively, then the instruction:
QADDSUBX Rd, Ra, Rb
performs the complex arithmetic operation Rd = (Ra + i * Rb).
QADDSUBX does not set the Q flag, even if saturation occurs on either operation.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-98
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.50 QDADD
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
00010100
Rn
Rd
SBZ
0101
Rm
QDADD (Saturating Double and Add) doubles its second operand, then adds the result to its first operand.
Both the doubling and the addition have their results saturated to the 32-bit signed integer range 231 x 231 1. If saturation occurs in either operation, the instruction sets the Q flag in the CPSR.
Syntax
QDADD{<cond>} <Rd>, <Rm>, <Rn>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register whose value is to be doubled, saturated, and used as the second operand for the saturated addition.
<Rd> <Rm> <Rn>
Architecture version
Version 5TE and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = SignedSat(Rm + SignedSat(Rn*2, 32), 32) if SignedDoesSat(Rm + SignedSat(Rn*2, 32), 32) or SignedDoesSat(Rn*2, 32) then Q Flag = 1
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-99
ARM Instructions
Usage
The primary use for this instruction is to generate multiply-accumulate operations on Q15 and Q31 numbers, by placing it after an integer multiply instruction. Three examples are: To multiply the Q15 numbers in the top halves of R4 and R5 and add the product to the Q31 number in R6, use:
SMULTT QDADD R0, R4, R5 R6, R6, R0
To multiply the Q15 number in the bottom half of R2 by the Q31 number in R3 and add the product to the Q31 number in R7, use:
SMULWB QDADD R0, R3, R2 R7, R7, R0
To multiply the Q31 numbers in R2 and R3 and add the product to the Q31 number in R4, use:
SMULL QDADD R0, R1, R2, R3 R4, R4, R1
Notes
Use of R15 Condition flags Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results. The QDADD instruction does not affect the N, Z, C, or V flags.
A4-100
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.51 QDSUB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
00010110
Rn
Rd
SBZ
0101
Rm
QDSUB (Saturating Double and Subtract) doubles its second operand, then subtracts the result from its first
operand. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range 231 x 231 1. If saturation occurs in either operation, QDSUB sets the Q flag in the CPSR.
Syntax
QDSUB{<cond>} <Rd>, <Rm>, <Rn>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register whose value is to be doubled, saturated, and used as the second operand for the saturated subtraction.
<Rd> <Rm> <Rn>
Rm and Rn are in reversed order in the assembler syntax, compared with the majority of ARM instructions.
Architecture version
Version 5TE and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = SignedSat(Rm - SignedSat(Rn*2, 32), 32) if SignedDoesSat(Rm - SignedSat(Rn*2, 32), 32) or SignedDoesSat(Rn*2, 32) then Q Flag = 1
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-101
ARM Instructions
Usage
The primary use for this instruction is to generate multiply-subtract operations on Q15 and Q31 numbers, by placing it after an integer multiply instruction. Three examples are: To multiply the Q15 numbers in the top half of R4 and the bottom half of R5, and subtract the product from the Q31 number in R6, use:
SMULTB QDSUB R0, R4, R5 R6, R6, R0
To multiply the Q15 number in the bottom half of R2 by the Q31 number in R3 and subtract the product from the Q31 number in R7, use:
SMULWB QDSUB R0, R3, R2 R7, R7, R0
To multiply the Q31 numbers in R2 and R3 and subtract the product from the Q31 number in R4, use:
SMULL QDSUB R0, R1, R2, R3 R4, R4, R1
Notes
Use of R15 Condition flags Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results. The QDSUB instruction does not affect the N, Z, C, or V flags.
A4-102
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.52 QSUB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
00010010
Rn
Rd
SBZ
0101
Rm
QSUB (Saturating Subtract) performs integer subtraction. It saturates the result to the 32-bit signed integer range 231 x 231 1.
If saturation occurs, QSUB sets the Q flag in the CPSR.
Syntax
QSUB{<cond>} <Rd>, <Rm>, <Rn>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rm> <Rn>
Rm and Rn are in reversed order in the assembler syntax, compared with the majority of ARM instructions.
Architecture version
Version 5TE and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = SignedSat(Rm - Rn, 32) if SignedDoesSat(Rm - Rn, 32) then Q Flag = 1
Notes
Use of R15 Condition flags Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
QSUB does not affect the N, Z, C, or V flags.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-103
ARM Instructions
A4.1.53 QSUB16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100010
Rn
Rd
SBO
0111
Rm
QSUB16 performs two 16-bit subtractions. It saturates the results to the 16-bit signed integer range
215 x 215 1.
QSUB16 does not affect any flags.
Syntax
QSUB16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15:0] = SignedSat(Rn[15:0] - Rm[15:0], 16) Rd[31:16] = SignedSat(Rn[31:16] - Rm[31:16], 16)
Usage
Use QSUB16 in similar ways to the SSUB16 instruction, but for signed saturated arithmetic. QSUB16 does not set the GE bits for use with SEL. See SSUB16 on page A4-180 for more details.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-104
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.54 QSUB8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100010
Rn
Rd
SBO
1111
Rm
QSUB8 performs four 8-bit subtractions. It saturates the results to the 8-bit signed integer range
27 x 27 1.
QSUB8 does not affect any flags.
Syntax
QSUB8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[7:0] = SignedSat(Rn[7:0] Rd[15:8] = SignedSat(Rn[15:8] Rd[23:16] = SignedSat(Rn[23:16] Rd[31:24] = SignedSat(Rn[31:24] Rm[7:0], Rm[15:8], Rm[23:16], Rm[31:24], 8) 8) 8) 8)
Usage
Use QSUB8 in similar ways to SSUB8, but for signed saturated arithmetic. QSUB8 does not set the GE bits for use with SEL. See SSUB8 on page A4-182 for more details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-105
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-106
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.55 QSUBADDX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100010
Rn
Rd
SBO
0101
Rm
QSUBADDX (Saturating Subtract and Add with Exchange) performs one 16-bit signed integer addition and one
16-bit signed integer subtraction, saturating the results to the 16-bit signed integer range 215 x 215 1. It exchanges the two halfwords of the second operand before it performs the arithmetic. QSUBADDX does not affect any flags.
Syntax
QSUBADDX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[31:16] = SignedSat(Rn[31:16] - Rm[15:0], 16) Rd[15:0] = SignedSat(Rn[15:0] + Rm[31:16], 16)
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-107
ARM Instructions
Usage
You can use QSUBADDX for operations on complex numbers that are held as pairs of 16-bit integers or Q15 numbers. If you hold the real and imaginary parts of a complex number in the bottom and top half of a register respectively, then the instruction:
QSUBADDX Rd, Ra, Rb
performs the complex arithmetic operation Rd = (Ra i * Rb).
QSUBADDX does not set the Q flag, even if saturation occurs on either operation.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-108
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.56 REV
31 28 27 23 22 21 20 19 16 15 12 11 876 4 3 0
cond
01101011
SBO
Rd
SBO
0011
Rm
REV (Byte-Reverse Word) reverses the byte order in a 32-bit register.
Syntax
REV{<cond>} Rd, Rm
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the operand.
<Rd> <Rm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[31:24] = Rm[ 7: 0] Rd[23:16] = Rm[15: 8] Rd[15: 8] = Rm[23:16] Rd[ 7: 0] = Rm[31:24]
Usage
Use REV to convert 32-bit big-endian data into little-endian data, or 32-bit little-endian data into big-endian data.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-109
ARM Instructions
A4.1.57 REV16
31 28 27 23 22 21 20 19 16 15 12 11 8 76 43 0
cond
01101011
SBO
Rd
SBO
1011
Rm
REV16 (Byte-Reverse Packed Halfword) reverses the byte order in each 16-bit halfword of a 32-bit register.
Syntax
REV16{<cond>} Rd, Rm
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the operand.
<Rd> <Rm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15: 8] = Rm[ 7: 0] Rd[ 7: 0] = Rm[15: 8] Rd[31:24] = Rm[23:16] Rd[23:16] = Rm[31:24]
Usage
Use REV16 to convert 16-bit big-endian data into little-endian data, or 16-bit little-endian data into big-endian data.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
A4-110
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.58 REVSH
31 28 27 23 22 21 20 19 16 15 12 11 876 4 3 0
cond
01101111
SBO
Rd
SBO
1011
Rm
REVSH (Byte-Reverse Signed Halfword) reverses the byte order in the lower 16-bit halfword of a 32-bit
register, and sign extends the result to 32-bits.
Syntax
REVSH{<cond>} Rd, Rm
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the operand.
<Rd> <Rm>
Architecture version
Version 6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15: 8] = Rm[ 7: 0] Rd[ 7: 0] = Rm[15: 8] if Rm[7] == 1 then Rd[31:16] = 0xFFFF else Rd[31:16] = 0x0000
Usage
Use REVSH to convert either: 16-bit signed big-endian data into 32-bit signed little-endian data 16-bit signed little-endian data into 32-bit signed big-endian data.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-111
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
A4-112
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.59 RFE
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 0
1 1 1 1 1 0 0 PU0W1
Rn
SBZ
1010
SBZ
RFE (Return From Exception) loads the PC and the CPSR from the word at the specified address and the
following word respectively.
Syntax
RFE<addressing_mode> <Rn>{!}
where:
<addressing_mode>
Is similar to the <addressing_mode> in LDM and STM instructions, see Addressing Mode 4 Load and Store Multiple on page A5-41, but with the following differences:
<Rn>
The number of registers to load is 2. The register list is {PC, CPSR}.
Specifies the base register to be used by <addressing_mode>. If R15 is specified as the base register, the result is UNPREDICTABLE. If present, sets the W bit. This causes the instruction to write a modified value back to its base register, in a manner similar to that specified for Addressing Mode 4 - Load and Store Multiple on page A5-41. If ! is omitted, the W bit is 0 and the instruction does not change the base register.
!
Architecture version
Version 6 and above.
Exceptions
Data Abort.
Usage
While RFE supports different base registers, a general usage case is where Rn == sp (the stack pointer), held in R13. The instruction can then be used as the return method associated with instructions SRS and CPS. See New instructions to improve exception handling on page A2-28 for more details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-113
ARM Instructions
Operation
address = start_address value = Memory[address,4] If InAPrivilegedMode() then CPSR = Memory[address+4,4] else UNPREDICTABLE PC = value assert end_address == address + 8
where start_address and end_address are determined as described in Addressing Mode 4 - Load and Store Multiple on page A5-41, except that Number_Of_Set_Bits_in(register_list) evaluates to 2, rather than depending on bits[15:0] of the instruction.
Notes
Data Abort For details of the effects of this instruction if a Data Abort occurs, see Data Abort (data access memory abort) on page A2-21.
Non word-aligned addresses In ARMv6, an address with bits[1:0] != 0b00 causes an alignment exception if the CP15 register 1 bits U==1 or A==1, otherwise RFE behaves as if bits[1:0] are 0b00. In earlier implementations, if they include a System Control coprocessor (see Chapter B3 The System Control Coprocessor), an address with bits[1:0] != 0b00 causes an alignment exception if the CP15 register 1 bit A==1, otherwise RFE behaves as if bits[1:0] are 0b00. Time order The time order of the accesses to individual words of memory generated by RFE is not architecturally defined. Do not use this instruction on memory-mapped I/O locations where access order matters.
RFE is UNPREDICTABLE in User mode.
User mode Condition
Unlike most other ARM instructions, RFE cannot be executed conditionally.
ARM/Thumb State transfers If the CPSR T bit as loaded is 0 and bit[1] of the value loaded into the PC is 1, the results are UNPREDICTABLE because it is not possible to branch to an ARM instruction at a non word-aligned address.
A4-114
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.60 RSB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I0011S
Rn
Rd
shifter_operand
RSB (Reverse Subtract) subtracts a value from a second value.
The first value comes from a register. The second value can be either an immediate value or a value from a register, and can be shifted before the subtraction. This is the reverse of the normal order of operands in ARM assembler language.
RSB can optionally update the condition code flags, based on the result.
Syntax
RSB{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Sets the S bit (bit[20]) in the instruction to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the subtraction, and the C and V flags are set according to whether the subtraction generated a borrow (unsigned underflow) and a signed overflow, respectively. The rest of the CPSR is unchanged. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the second operand.
<shifter_operand>
Specifies the first operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not RSB. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
ARM DDI 0100I Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. A4-115
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = shifter_operand - Rn if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = NOT BorrowFrom(shifter_operand - Rn) V Flag = OverflowFrom(shifter_operand - Rn)
Usage
The following instruction stores the negation (twos complement) of Rx in Rd:
RSB Rd, Rx, #0
You can perform constant multiplication (of Rx) by 2n1 (into Rd) with:
RSB Rd, Rx, Rx, LSL #n
Notes
C flag If S is specified, the C flag is set to: 1 if no borrow occurs 0 if a borrow does occur. In other words, the C flag is used as a NOT(borrow) flag. This inversion of the borrow condition is used by subsequent instructions: SBC and RSC use the C flag as a NOT(borrow) operand, performing a normal subtraction if C == 1 and subtracting one more than usual if C == 0. The HS (unsigned higher or same) and LO (unsigned lower) conditions are equivalent to CS (carry set) and CC (carry clear) respectively.
A4-116
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.61 RSC
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I0111S
Rn
Rd
shifter_operand
RSC (Reverse Subtract with Carry) subtracts one value from another, taking account of any borrow from a preceding less significant subtraction. The normal order of the operands is reversed, to allow subtraction from a shifted register value, or from an immediate value. RSC can optionally update the condition code flags, based on the result.
Syntax
RSC{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Sets the S bit (bit[20]) in the instruction to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the subtraction, and the C and V flags are set according to whether the subtraction generated a borrow (unsigned underflow) and a signed overflow, respectively. The rest of the CPSR is unchanged. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the second operand.
<shifter_operand>
Specifies the first operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not RSC. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-117
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = shifter_operand - Rn - NOT(C Flag) if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = NOT BorrowFrom(shifter_operand - Rn - NOT(C Flag)) V Flag = OverflowFrom(shifter_operand - Rn - NOT(C Flag))
Usage
Use RSC to synthesize multi-word subtraction, in cases where you need the order of the operands reversed to allow subtraction from a shifted register value, or from an immediate value.
Example
You can negate the 64-bit value in R0,R1 using the following sequence (R0 holds the least significant word), which stores the result in R2,R3:
RSBS RSC R2,R0,#0 R3,R1,#0
Notes
C flag If S is specified, the C flag is set to: 1 if no borrow occurs 0 if a borrow does occur. In other words, the C flag is used as a NOT(borrow) flag. This inversion of the borrow condition is used by subsequent instructions: SBC and RSC use the C flag as a NOT(borrow) operand, performing a normal subtraction if C == 1 and subtracting one more than usual if C == 0. The HS (unsigned higher or same) and LO (unsigned lower) conditions are equivalent to CS (carry set) and CC (carry clear) respectively.
A4-118
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.62 SADD16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100001
Rn
Rd
SBO
0001
Rm
SADD16 (Signed Add) performs two 16-bit signed integer additions. It sets the GE bits in the CPSR according
to the results of the additions.
Syntax
SADD16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[15:0] + Rm[15:0] /* Signed addition */ Rd[15:0] = sum[15:0] GE[1:0] = if sum >= 0 then 0b11 else 0 sum = Rn[31:16] + Rm[31:16] /* Signed addition */ Rd[31:16] = sum[15:0] GE[3:2] = if sum >= 0 then 0b11 else 0
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-119
ARM Instructions
Usage
Use the SADD16 instruction to speed up operations on arrays of halfword data. For example, consider the instruction sequence:
LDR LDR SADD16 STR R3, R5, R3, R3, [R0], #4 [R1], #4 R3, R5 [R2], #4
This performs the same operations as the instruction sequence:
LDRH LDRH ADD STRH LDRH LDRH ADD STRH R3, R4, R3, R3, R3, R4, R3, R3, [R0], #2 [R1], #2 R3, R4 [R2], #2 [R0], #2 [R1], #2 R3, R4 [R2], #2
The first sequence uses half as many instructions and typically half as many cycles as the second sequence. You can also use SADD16 for operations on complex numbers that are held as pairs of 16-bit integers or Q15 numbers. If you hold the real and imaginary parts of a complex number in the bottom and top half of a register respectively, then the instruction:
SADD16 Rd, Ra, Rb
performs the complex arithmetic operation Rd = Ra + Rb.
SADD16 sets the GE flags according to the results of each addition. You can use these in a following SEL
instruction. See SEL on page A4-127.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-120
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.63 SADD8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100001
Rn
Rd
SBO
1001
Rm
SADD8 performs four 8-bit signed integer additions. It sets the GE bits in the CPSR according to the results
of the additions.
Syntax
SADD8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[7:0] + Rm[7:0] /* Signed Rd[7:0] = sum[7:0] GE[0] = if sum >= 0 then 1 else 0 sum = Rn[15:8] + Rm[15:8] /* Signed Rd[15:8] = sum[7:0] GE[1] = if sum >= 0 then 1 else 0 sum = Rn[23:16] + Rm[23:16] /* Signed Rd[23:16] = sum[7:0] GE[2] = if sum >= 0 then 1 else 0 sum = Rn[31:24] + Rm[31:24] /* Signed Rd[31:24] = sum[7:0] GE[3] = if sum >= 0 then 1 else 0 addition */
addition */
addition */
addition */
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-121
ARM Instructions
Usage
Use SADD8 to speed up operations on arrays of byte data. This is similar to the way you can use the SADD16 instruction. See the usage subsection for SADD16 on page A4-119 for details.
SADD8 sets the GE flags according to the results of each addition. You can use these in a following SEL
instruction, see SEL on page A4-127.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-122
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.64 SADDSUBX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100001
Rn
Rd
SBO
0011
Rm
SADDSUBX (Signed Add and Subtract with Exchange) performs one 16-bit signed integer addition and one 16-bit signed integer subtraction. It exchanges the two halfwords of the second operand before it performs the arithmetic. It sets the GE bits in the CPSR according to the results of the additions.
Syntax
SADDSUBX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[31:16] + Rm[15:0] /* Signed addition */ Rd[31:16] = sum[15:0] GE[3:2] = if sum >= 0 then 0b11 else 0 diff = Rn[15:0] - Rm[31:16] /* Signed subtraction */ Rd[15:0] = diff[15:0] GE[1:0] = if diff >= 0 then 0b11 else 0
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-123
ARM Instructions
Usage
You can use SADDSUBX for operations on complex numbers that are held as pairs of 16-bit integers or Q15 numbers. If you hold the real and imaginary parts of a complex number in the bottom and top half of a register respectively, then the instruction:
SADDSUBX Rd, Ra, Rb
performs the complex arithmetic operation Rd = Ra + (i * Rb).
SADDSUBX sets the GE flags according to the results the operation. You can use these in a following SEL
instruction, see SEL on page A4-127.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-124
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.65 SBC
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I0110S
Rn
Rd
shifter_operand
SBC (Subtract with Carry) subtracts the value of its second operand and the value of NOT(Carry flag) from
the value of its first operand. The first operand comes from a register. The second operand can be either an immediate value or a value from a register, and can be shifted before the subtraction. Use SBC to synthesize multi-word subtraction.
SBC can optionally update the condition code flags, based on the result.
Syntax
SBC{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Sets the S bit (bit[20]) in the instruction to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the subtraction, and the C and V flags are set according to whether the subtraction generated a borrow (unsigned underflow) and a signed overflow, respectively. The rest of the CPSR is unchanged. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the first operand.
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not SBC. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
ARM DDI 0100I Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. A4-125
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = Rn - shifter_operand - NOT(C Flag) if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rn - shifter_operand - NOT(C Flag)) V Flag = OverflowFrom(Rn - shifter_operand - NOT(C Flag))
Usage
If register pairs R0,R1 and R2,R3 hold 64-bit values (R0 and R2 hold the least significant words), the following instructions leave the 64-bit difference in R4,R5:
SUBS SBC R4,R0,R2 R5,R1,R3
Notes
C flag If S is specified, the C flag is set to: 1 if no borrow occurs 0 if a borrow does occur. In other words, the C flag is used as a NOT(borrow) flag. This inversion of the borrow condition is used by subsequent instructions: SBC and RSC use the C flag as a NOT(borrow) operand, performing a normal subtraction if C == 1 and subtracting one more than usual if C == 0. The HS (unsigned higher or same) and LO (unsigned lower) conditions are equivalent to CS (carry set) and CC (carry clear) respectively.
A4-126
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.66 SEL
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01101000
Rn
Rd
SBO
1011
Rm
SEL (Select) selects each byte of its result from either its first operand or its second operand, according to the
values of the GE flags.
Syntax
SEL{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) Rd[7:0] = if GE[0] Rd[15:8] = if GE[1] Rd[23:16] = if GE[2] Rd[31:24] = if GE[3] then == 1 == 1 == 1 == 1 then then then then Rn[7:0] Rn[15:8] Rn[23:16] Rn[31:24] else else else else Rm[7:0] Rm[15:8] Rm[23:16] Rm[31:24]
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-127
ARM Instructions
Usage
Use SEL after instructions such as SADD8, SADD16, SSUB8, SSUB16, UADD8, UADD16, USUB8, USUB16, SADDSUBX, SSUBADDX, UADDSUBX and USUBADDX, that set the GE flags. For example, the following sequence of instructions sets each byte of Rd equal to the unsigned minimum of the corresponding bytes of Ra and Rb:
USUB8 SEL Rd, Ra, Rb Rd, Rb, Ra
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-128
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.67 SETEND
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10 9 8 7 43 0
1111000100000001
SBZ
E SBZ 0 0 0 0
SBZ
SETEND modifies the CPSR E bit, without changing any other bits in the CPSR.
Syntax
SETEND <endian_specifier>
where:
<endian_specifier>
Is one of:
BE LE
Sets the E bit in the instruction. This sets the CPSR E bit. Clears the E bit in the instruction. This clears the CPSR E bit.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
CPSR = CPSR with specified E bit modification
Usage
Use SETEND to change the byte order for data accesses. You can use SETEND to increase the efficiency of access to a series of big-endian data fields in an otherwise little-endian application, or to a series of little-endian data fields in an otherwise big-endian application.
Notes
Condition Unlike most other ARM instructions, SETEND cannot be executed conditionally.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-129
ARM Instructions
A4.1.68 SHADD16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100011
Rn
Rd
SBO
0001
Rm
SHADD16 (Signed Halving Add) performs two 16-bit signed integer additions, and halves the results. It has no effect on the GE flags.
Syntax
SHADD16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[15:0] + Rm[15:0] /* Signed addition */ Rd[15:0] = sum[16:1] sum = Rn[31:16] + Rm[31:16] /* Signed addition */ Rd[31:16] = sum[16:1]
Usage
Use SHADD16 for similar purposes to SADD16 (see SADD16 on page A4-119). SHADD16 averages the operands. It does not set any flags, as overflow is not possible.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-130
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.69 SHADD8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100011
Rn
Rd
SBO
1001
Rm
SHADD8 performs four 8-bit signed integer additions, and halves the results. It has no effect on the GE flags.
Syntax
SHADD8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[7:0] + Rm[7:0] /* Signed addition */ Rd[7:0] = sum[8:1] sum = Rn[15:8] + Rm[15:8] /* Signed addition */ Rd[15:8] = sum[8:1] sum = Rn[23:16] + Rm[23:16] /* Signed addition */ Rd[23:16] = sum[8:1] sum = Rn[31:24] + Rm[31:24] /* Signed addition */ Rd[31:24] = sum[8:1]
Usage
Use SHADD8 similar purposes to SADD16 (see SADD16 on page A4-119). SHADD8 averages the operands. It does not set any flags, as overflow is not possible.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-131
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-132
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.70 SHADDSUBX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100011
Rn
Rd
SBO
0011
Rm
SHADDSUBX (Signed Halving Add and Subtract with Exchange) performs one 16-bit signed integer addition and one 16-bit signed integer subtraction, and halves the results. It exchanges the two halfwords of the second operand before it performs the arithmetic. SHADDSUBX has no effect on the GE flags.
Syntax
SHADDSUBX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[31:16] + Rm[15:0] Rd[31:16] = sum[16:1] diff = Rn[15:0] - Rm[31:16] Rd[15:0] = diff[16:1] /* Signed addition */ /* Signed subtraction */
Usage
Use SHADDSUBX for similar purposes to SADDSUBX, but when you want the results halved. See SADDSUBX on page A4-123 for further details.
SHADDSUBX does not set any flags, as overflow is not possible.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-133
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-134
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.71 SHSUB16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100011
Rn
Rd
SBO
0111
Rm
SHSUB16 (Signed Halving Subtract) performs two 16-bit signed integer subtractions, and halves the results. SHSUB16 has no effect on the GE flags.
Syntax
SHSUB16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[15:0] - Rm[15:0] Rd[15:0] = diff[16:1] diff = Rn[31:16] - Rm[31:16] Rd[31:16] = diff[16:1] /* Signed subtraction */ /* Signed subtraction */
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-135
ARM Instructions
Usage
Use SHSUB16 to speed up operations on arrays of halfword data. This is similar to the way you can use SADD16. See the usage subsection for SADD16 on page A4-119 for details. You can also use SHSUB16 for operations on complex numbers that are held as pairs of 16-bit integers or Q15 numbers. If you hold the real and imaginary parts of a complex number in the bottom and top half of a register respectively, then the instruction:
SHSUB16 Rd, Ra, Rb
performs the complex arithmetic operation Rd = (Ra - Rb)/2.
SHSUB16 does not set any flags, as overflow is not possible.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-136
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.72 SHSUB8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100011
Rn
Rd
SBO
1111
Rm
SHSUB8 performs four 8-bit signed integer subtractions, and halves the results. SHSUB8 has no effect on the GE flags.
Syntax
SHSUB8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[7:0] - Rm[7:0] Rd[7:0] = diff[8:1] diff = Rn[15:8] - Rm[15:8] Rd[15:8] = diff[8:1] diff = Rn[23:16] - Rm[23:16] Rd[23:16] = diff[8:1] diff = Rn[31:24] - Rm[31:24] Rd[31:24] = diff[8:1] /* Signed subtraction */ /* Signed subtraction */ /* Signed subtraction */ /* Signed subtraction */
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-137
ARM Instructions
Usage
Use SHSUB8 to speed up operations on arrays of byte data. This is similar to the way you can use SADD16 to speed up operations on halfword data. See the usage subsection for SADD16 on page A4-119 for details.
SHSUB8 does not set any flags, as overflow is not possible.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-138
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.73 SHSUBADDX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100011
Rn
Rd
SBO
0101
Rm
SHSUBADDX (Signed Halving Subtract and Add with Exchange) performs one 16-bit signed integer subtraction and one 16-bit signed integer addition, and halves the results. It exchanges the two halfwords of the second operand before it performs the arithmetic. SHSUBADDX has no effect on the GE flags.
Syntax
SHSUBADDX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[31:16] - Rm[15:0] Rd[31:16] = diff[16:1] sum = Rn[15:0] + Rm[31:16] Rd[15:0] = sum[16:1] /* Signed subtraction */ /* Signed addition */
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-139
ARM Instructions
Usage
Use SHSUBADDX for similar purposes to SSUBADDX, but when you want the results halved. See SSUBADDX on page A4-184 for further details.
SHSUBADDX does not set any flags, as overflow is not possible.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-140
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.74 SMLA<x><y>
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
00010000
Rd
Rn
Rs
1yx0
Rm
SMLA<x><y> (Signed multiply-accumulate BB, BT, TB, and TT) performs a signed multiply-accumulate
operation. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is added to a 32-bit accumulate value and the result is written to the destination register. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the CPSR. It is not possible for overflow to occur during the multiplication.
Syntax
SMLA<x><y>{<cond>} <Rd>, <Rm>, <Rs>, <Rn>
where:
<x>
Specifies which half of the source register <Rm> is used as the first multiply operand. If <x> is B, then x == 0 in the instruction encoding and the bottom half (bits[15:0]) of <Rm> is used. If <x> is T, then x == 1 in the instruction encoding and the top half (bits[31:16]) of <Rm> is used. Specifies which half of the source register <Rs> is used as the second multiply operand. If <y> is B, then y == 0 in the instruction encoding and the bottom half (bits[15:0]) of <Rs> is used. If <y> is T, then y == 1 in the instruction encoding and the top half (bits[31:16]) of <Rs> is used. Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the source register whose bottom or top half (selected by <x>) is the first multiply operand. Specifies the source register whose bottom or top half (selected by <y>) is the second multiply operand. Specifies the register which contains the accumulate value.
<y>
<cond>
<Rd> <Rm>
<Rs>
<Rn>
Architecture version
Version 5TE and above.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-141
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then if (x == 0) then operand1 = SignExtend(Rm[15:0]) else /* x == 1 */ operand1 = SignExtend(Rm[31:16]) if (y == 0) then operand2 = SignExtend(Rs[15:0]) else /* y == 1 */ operand2 = SignExtend(Rs[31:16]) Rd = (operand1 * operand2) + Rn if OverflowFrom((operand1 * operand2) + Rn) then Q Flag = 1
A4-142
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
In addition to its straightforward uses for integer multiply-accumulates, these instructions sometimes provide a faster alternative to Q15 Q15 + Q31 Q31 multiply-accumulates synthesized from SMUL<x><y> and QDADD instructions. The main circumstances under which this is possible are: if it is known that saturation and/or overflow cannot occur during the calculation if saturation and/or overflow can occur during the calculation but the Q flag is going to be used to detect this and take remedial action if it does occur.
For example, the following code produces the dot product of the four Q15 numbers in R0 and R1 by the four Q15 numbers in R2 and R3:
SMULBB QADD SMULTT QDADD SMULBB QDADD SMULTT QDADD R4, R4, R5, R4, R5, R4, R5, R4, R0, R4, R0, R4, R1, R4, R1, R4, R2 R4 R2 R5 R3 R5 R3 R5
In the absence of saturation, the following code provides a faster alternative:
SMULBB SMLATT SMLABB SMLATT QADD R4, R4, R4, R4, R4, R0, R0, R1, R1, R4, R2 R2, R4 R3, R4 R3, R4 R4
Furthermore, if saturation and/or overflow occurs in this second sequence, it sets the Q flag. This allows remedial action to be taken, such as scaling down the data values and repeating the calculation.
Notes
Use of R15 Condition flags Specifying R15 for register <Rd>, <Rm>, <Rs>, or <Rn> has UNPREDICTABLE results. The SMLA<x><y> instructions do not affect the N, Z, C, or V flags.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-143
ARM Instructions
A4.1.75 SMLAD
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01110000
Rd
Rn
Rs
00X1
Rm
SMLAD (Signed Multiply Accumulate Dual) performs two signed 16 x 16-bit multiplications. It adds the
products to a 32-bit accumulate operand. Optionally, you can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications.
Syntax
SMLAD{X}{<cond>} <Rd>, <Rm>, <Rs>, <Rn>
where:
X
Sets the X bit of the instruction to 1, and the multiplications are bottom x top and top x bottom. If the X is omitted, sets the X bit to 0, and the multiplications are bottom x bottom and top x top.
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand. Specifies the register that contains the accumulate operand.
<Rd> <Rm> <Rs> <Rn>
Architecture version
ARMv6 and above.
Exceptions
None.
A4-144
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if X == 1 then operand2 = Rs Rotate_Right 16 else operand2 = Rs product1 = Rm[15:0] * operand2[15:0] /* Signed multiplication */ product2 = Rm[31:16] * operand2[31:16] /* Signed multiplication */ Rd = Rn + product1 + product2 if OverflowFrom(Rn + product1 + product2) then Q flag = 1
Usage
Use SMLAD to accumulate the sums of products of 16-bit data, with a 32-bit accumulator. This instruction enables you to do this at approximately twice the speed otherwise possible. This is useful in many applications, for example in filters. You can use the X option for calculating the imaginary part for similar filters acting on complex numbers with 16-bit real and 16-bit imaginary parts.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results.
Note
Your assembler must fault the use of R15 for register <Rn>.
Encoding Early termination
If the <Rn> field of the instruction contains 0b1111, the instruction is an SMUAD instruction instead, see SMUAD on page A4-164. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED. The SMLAD instruction leaves the N, Z, C and V flags unchanged.
N, Z, C and V flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-145
ARM Instructions
A4.1.76 SMLAL
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0000111S
RdHi
RdLo
Rs
1001
Rm
SMLAL (Signed Multiply Accumulate Long) multiplies two signed 32-bit values to produce a 64-bit value,
and accumulates this with a 64-bit value.
SMLAL can optionally update the condition code flags, based on the result.
Syntax
SMLAL{<cond>}{S} <RdLo>, <RdHi>, <Rm>, <Rs>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction updates the CPSR by setting the N and Z flags according to the result of the multiply-accumulate. If S is omitted, the S bit of the instruction is set to 0 and the entire CPSR is unaffected by the instruction. Supplies the lower 32 bits of the value to be added to the product of <Rm> and <Rs>, and is the destination register for the lower 32 bits of the result. Supplies the upper 32 bits of the value to be added to the product of <Rm> and <Rs>, and is the destination register for the upper 32 bits of the result. Holds the signed value to be multiplied with the value of <Rs>. Holds the signed value to be multiplied with the value of <Rm>.
S
<RdLo>
<RdHi>
<Rm> <Rs>
Architecture version
All
Exceptions
None.
A4-146
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then RdLo = (Rm * Rs)[31:0] + RdLo /* Signed multiplication */ RdHi = (Rm * Rs)[63:32] + RdHi + CarryFrom((Rm * Rs)[31:0] + RdLo) if S == 1 then N Flag = RdHi[31] Z Flag = if (RdHi == 0) and (RdLo == 0) then 1 else 0 C Flag = unaffected /* See "C and V flags" note */ V Flag = unaffected /* See "C and V flags" note */
Usage
SMLAL multiplies signed variables to produce a 64-bit result, which is added to the 64-bit value in the two
destination general-purpose registers. The result is written back to the two destination general-purpose registers.
Notes
Use of R15 Specifying R15 for register <RdHi>, <RdLo>, <Rm>, or <Rs> has UNPREDICTABLE results.
Operand restriction <RdHi> and <RdLo> must be distinct registers, or the results are UNPREDICTABLE. Specifying the same register for either <RdHi> and <Rm>, or <RdLo> and <Rm>, was previously described as producing UNPREDICTABLE results. There is no restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 implementations do not require this restriction either, because high performance multipliers read all their operands prior to writing back any results. Early termination If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMLALS is defined to leave the C and V flags unchanged in ARMv5 and above. In earlier versions of the architecture, the values of the C and V flags were UNPREDICTABLE after an SMLALS instruction.
C and V flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-147
ARM Instructions
A4.1.77 SMLAL<x><y>
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00010100
RdHi
RdLo
Rs
1yx0
Rm
SMLAL<x><y> (Signed Multiply-Accumulate Long BB, BT, TB, and TT) performs a signed multiply-accumulate operation. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is sign-extended and added to the 64-bit accumulate value held in <RdHi> and <RdLo>, and the result is written back to <RdHi> and <RdLo>.
Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264.
Syntax
SMLAL<x><y>{<cond>} <RdLo>, <RdHi>, <Rm>, <Rs>
where:
<x>
Specifies which half of the source register <Rm> is used as the first multiply operand. If <x> is B, then x == 0 in the instruction encoding and the bottom half (bits[15:0]) of <Rm> is used. If <x> is T, then x == 1 in the instruction encoding and the top half (bits[31:16]) of <Rm> is used. Specifies which half of the source register <Rs> is used as the second multiply operand. If <y> is B, then y == 0 in the instruction encoding and the bottom half (bits[15:0]) of <Rs> is used. If <y> is T, then y == 1 in the instruction encoding and the top half (bits[31:16]) of <Rs> is used. Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Supplies the lower 32 bits of the 64-bit accumulate value to be added to the product, and is the destination register for the lower 32 bits of the 64-bit result. Supplies the upper 32 bits of the 64-bit accumulate value to be added to the product, and is the destination register for the upper 32 bits of the 64-bit result. Specifies the source register whose bottom or top half (selected by <x>) is the first multiply operand. Specifies the source register whose bottom or top half (selected by <y>) is the second multiply operand.
<y>
<cond>
<RdLo>
<RdHi>
<Rm>
<Rs>
Architecture version
Version 5TE and above.
A4-148
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then if (x == 0) then operand1 = SignExtend(Rm[15:0]) else /* x == 1 */ operand1 = SignExtend(Rm[31:16]) if (y == 0) then operand2 = SignExtend(Rs[15:0]) else /* y == 1 */ operand2 = SignExtend(Rs[31:16]) RdLo = RdLo + (operand1 * operand2) RdHi = RdHi + (if (operand1*operand2) < 0 then 0xFFFFFFFF else 0) + CarryFrom(RdLo + (operand1 * operand2))
Usage
These instructions allow a long sequence of multiply-accumulates of signed 16-bit integers or Q15 numbers to be performed, with sufficient guard bits to ensure that the result cannot overflow the 64-bit destination in practice. It would take more than 233 consecutive multiply-accumulates to cause such overflow. If the overall calculation does not overflow a signed 32-bit number, then <RdLo> holds the result of the calculation. A simple test to determine whether such a calculation has overflowed <RdLo> is to execute the instruction:
CMP <RdHi>, <RdLo>, ASR #31
at the end of the calculation. If the Z flag is set, <RdLo> holds an accurate final result. If the Z flag is clear, the final result has overflowed a signed 32-bit destination.
Notes
Use of R15 Specifying R15 for register <RdLo>, <RdHi>, <Rm>, or <Rs> has UNPREDICTABLE results.
Operand restriction If <RdLo> and <RdHi> are the same register, the results are UNPREDICTABLE. Early termination If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED. The SMLAL<x><y> instructions do not affect the N, Z, C, V, or Q flags.
Condition flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-149
ARM Instructions
A4.1.78 SMLALD
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01110100
RdHi
RdLo
Rs
00X1
Rm
SMLALD (Signed Multiply Accumulate Long Dual) performs two signed 16 x 16-bit multiplications. It adds
the products to a 64-bit accumulate operand. Optionally, you can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.
Syntax
SMLALD{X}{<cond>} <RdLo>, <RdHi>, <Rm>, <Rs>
where:
X
Sets the X bit of the instruction to 1, and the multiplications are bottom x top and top x bottom. If the X is omitted, sets the X bit to 0, and the multiplications are bottom x bottom and top x top.
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Supplies the lower 32 bits of the 64-bit accumulate value to be added to the product, and is the destination register for the lower 32 bits of the 64-bit result. Supplies the upper 32 bits of the 64-bit accumulate value to be added to the product, and is the destination register for the upper 32 bits of the 64-bit result. Specifies the register that contains the first multiply operand. Specifies the register that contains the second multiply operand.
<RdLo>
<RdHi>
<Rm> <Rs>
Architecture version
ARMv6 and above.
Exceptions
None.
A4-150
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if X == 1 then operand2 = Rs Rotate_Right 16 else operand2 = Rs accvalue[31:0] = RdLo accvalue[63:32] = RdHi product1 = Rm[15:0] * operand2[15:0] product2 = Rm[31:16] * operand2[31:16] result = accvalue + product1 + product2 RdLo = result[31:0] RdHi = result[63:32]
/* Signed multiplication */ /* Signed multiplication */ /* Signed addition */
Usage
Use SMLALD in similar ways to SMLAD, but when you require a 64-bit accumulator instead of a 32-bit accumulator. On most implementations, this runs more slowly. See the usage section for SMLAD on page A4-144 for further details.
Notes
Use of R15 Specifying R15 for register <RdLo>, <RdHi>, <Rm>, or <Rs> has UNPREDICTABLE results.
Operand restriction If <RdLo> and <RdHi> are the same register, the results are UNPREDICTABLE. Early termination If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMLALD leaves all the flags unchanged.
Flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-151
ARM Instructions
A4.1.79 SMLAW<y>
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00010010
Rd
Rn
Rs
1y00
Rm
SMLAW<y> (Signed Multiply-Accumulate Word B and T) performs a signed multiply-accumulate operation.
The multiply acts on a signed 32-bit quantity and a signed 16-bit quantity, with the latter being taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are added to a 32-bit accumulate value and the result is written to the destination register. The bottom 16 bits of the 48-bit product are ignored. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the CPSR. No overflow can occur during the multiplication, because of the use of the top 32 bits of the 48-bit product.
Syntax
SMLAW<y>{<cond>} <Rd>, <Rm>, <Rs>, <Rn>
where:
<y>
Specifies which half of the source register <Rs> is used as the second multiply operand. If <y> is B, then y == 0 in the instruction encoding and the bottom half (bits[15:0]) of <Rs> is used. If <y> is T, then y == 1 in the instruction encoding and the top half (bits[31:16]) of <Rs> is used. Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the source register which contains the 32-bit first multiply operand. Specifies the source register whose bottom or top half (selected by <y>) is the second multiply operand. Specifies the register which contains the accumulate value.
<cond>
<Rd> <Rm> <Rs>
<Rn>
Architecture version
Version 5TE and above.
Exceptions
None.
A4-152
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if (y == 0) then operand2 = SignExtend(Rs[15:0]) else /* y == 1 */ operand2 = SignExtend(Rs[31:16]) Rd = (Rm * operand2)[47:16] + Rn /* Signed multiplication */ if OverflowFrom((Rm * operand2)[47:16] + Rn) then Q Flag = 1
Usage
In addition to their straightforward uses for integer multiply-accumulates, these instructions sometimes provide a faster alternative to Q31 Q15 + Q31 Q31 multiply-accumulates synthesized from SMULW<y> and QDADD instructions. The circumstances under which this is possible and the benefits it provides are very similar to those for the SMLA<x><y> instructions. See Usage on page A4-143 for more details.
Notes
Use of R15 Early termination Specifying R15 for register <Rd>, <Rm>, <Rs>, or <Rn> has UNPREDICTABLE results. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED. The SMLAW<y> instructions do not affect the N, Z, C, or V flags.
Condition flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-153
ARM Instructions
A4.1.80 SMLSD
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01110000
Rd
Rn
Rs
01X1
Rm
SMLSD (Signed Multiply Subtract accumulate Dual) performs two signed 16 x 16-bit multiplications. It adds
the difference of the products to a 32-bit accumulate operand. Optionally, you can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction.
Syntax
SMLSD{X}{<cond>} <Rd>, <Rm>, <Rs>, <Rn>
where:
X
Sets the X bit of the instruction to 1, and the multiplications are bottom x top and top x bottom. If the X is omitted, sets the X bit to 0, and the multiplications are bottom x bottom and top x top.
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first multiply operand. Specifies the register that contains the second multiply operand. Specifies the register that contains the accumulate operand.
<Rd> <Rm> <Rs> <Rn>
Architecture version
ARMv6 and above.
Exceptions
None.
A4-154
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if X == 1 then operand2 = Rs Rotate_Right 16 else operand2 = Rs product1 = Rm[15:0] * operand2[15:0] /* Signed multiplication */ product2 = Rm[31:16] * operand2[31:16] /* Signed multiplication */ diffofproducts = product1 - product2 /* Signed subtraction */ Rd = Rn + diffofproducts if OverflowFrom(Rn + diffofproducts) then Q flag = 1
Usage
You can use SMLSD for calculating the real part in filters with 32-bit accumulators, acting on complex numbers with 16-bit real and 16-bit imaginary parts. See also the usage section for SMLAD on page A4-144.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results.
Note
Your assembler must fault the use of R15 for register <Rn>.
Encoding Early termination
If the <Rn> field of the instruction contains 0b1111, the instruction is an SMUSD instruction instead, see SMUSD on page A4-172. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMLSD leaves the N, Z, C and V flags unchanged.
N, Z, C and V flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-155
ARM Instructions
A4.1.81 SMLSLD
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01110100
RdHi
RdLo
Rs
01X1
Rm
SMLSLD (Signed Multiply Subtract accumulate Long Dual) performs two signed 16 x 16-bit multiplications.
It adds the difference of the products to a 64-bit accumulate operand. Optionally, you can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.
Syntax
SMLSLD{X}{<cond>} <RdLo>, <RdHi>, <Rm>, <Rs>
where:
X
Sets the X bit of the instruction to 1, and the multiplications are bottom x top and top x bottom. If the X is omitted, sets the X bit to 0, and the multiplications are bottom x bottom and top x top.
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Supplies the lower 32 bits of the 64-bit accumulate value to be added to the product, and is the destination register for the lower 32 bits of the 64-bit result. Supplies the upper 32 bits of the 64-bit accumulate value to be added to the product, and is the destination register for the upper 32 bits of the 64-bit result. Specifies the register that contains the first multiply operand. Specifies the register that contains the second multiply operand.
<RdLo>
<RdHi>
<Rm> <Rs>
Architecture version
ARMv6 and above.
Exceptions
None.
A4-156
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if X == 1 then operand2 = Rs Rotate_Right 16 else operand2 = Rs accvalue[31:0] = RdLo accvalue[63:32] = RdHi product1 = Rm[15:0] * operand2[15:0] product2 = Rm[31:16] * operand2[31:16] result = accvalue + product1 - product2 RdLo = result[31:0] RdHi = result[63:32]
/* Signed multiplication */ /* Signed multiplication */ /* Signed subtraction */
Usage
The instruction has similar uses to those of the SMLSD instruction (see the Usage section for SMLSD on page A4-154), but when 64-bit accumulators are required rather than 32-bit accumulators. On most implementations, the resulting filter will not run as fast as a version using SMLSD, but it has many more guard bits against overflow. See also the usage section for SMLAD on page A4-144.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results.
Operand restriction If <RdLo> and <RdHi> are the same register, the results are UNPREDICTABLE. Early termination If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMLSD leaves all the flags unchanged.
Flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-157
ARM Instructions
A4.1.82 SMMLA
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01110101
Rd
Rn
Rs
00R1
Rm
SMMLA (Signed Most significant word Multiply Accumulate) multiplies two signed 32-bit values, extracts the
most significant 32 bits of the result, and adds an accumulate value. Optionally, you can specify that the result is rounded instead of being truncated. In this case, the constant
0x80000000 is added to the product before the high word is extracted.
Syntax
SMMLA{R}{<cond>} <Rd>, <Rm>, <Rs>, <Rn>
where:
R
Sets the R bit of the instruction to 1. The multiplication is rounded. If the R is omitted, sets the R bit to 0. The multiplication is truncated.
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first multiply operand. Specifies the register that contains the second multiply operand. Specifies the register that contains the accumulate operand.
<Rd> <Rm> <Rs> <Rn>
Architecture version
ARMv6 and above.
Exceptions
None.
A4-158
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then value = Rm * Rs /* Signed multiplication */ if R == 1 then Rd = ((Rn<<32) + value + 0x80000000)[63:32] else Rd = ((Rn<<32) + value)[63:32]
Usage
Provides fast multiplication for 32-bit fractional arithmetic. For example, the multiplies take two Q31 inputs and give a Q30 result (where Qn is a fixed point number with n bits of fraction). A short discussion on fractional arithmetic is provided in Saturated Q15 and Q31 arithmetic on page A2-69.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results.
Note
Your assembler must fault the use of R15 for register <Rn>.
Encoding Early termination
If the <Rn> field of the instruction contains 0b1111, the instruction is an SMMUL instruction instead, see SMMUL on page A4-162. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMMLA leaves all the flags unchanged.
Flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-159
ARM Instructions
A4.1.83 SMMLS
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01110101
Rd
Rn
Rs
11R1
Rm
SMMLS (Signed Most significant word Multiply Subtract) multiplies two signed 32-bit values, extracts the
most significant 32 bits of the result, and subtracts it from an accumulate value. Optionally, you can specify that the result is rounded instead of being truncated. In this case, the constant
0x80000000 is added to the accumulated value before the high word is extracted.
Syntax
SMMLS{R}{<cond>} <Rd>, <Rm>, <Rs>, <Rn>
where:
R
Sets the R bit of the instruction to 1. The multiplication is rounded. If the R is omitted, sets the R bit to 0. The multiplication is truncated.
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first multiply operand. Specifies the register that contains the second multiply operand. Specifies the register that contains the accumulate operand.
<Rd> <Rm> <Rs> <Rn>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then value = Rm * Rs /* Signed multiplication */ if R == 1 then Rd = ((Rn<<32) - value + 0x80000000)[63:32] else Rd = ((Rn<<32) value)[63:32]
A4-160
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
Provides fast multiplication for 32-bit fractional arithmetic. For example, the multiplies take two Q31 inputs and give a Q30 result (where Qn is a fixed point number with n bits of fraction).
Notes
Use of R15 Early termination Specifying R15 for register <Rd>, <Rm>, <Rs>, or <Rn> has UNPREDICTABLE results. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMMLS leaves all the flags unchanged.
Flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-161
ARM Instructions
A4.1.84 SMMUL
31 28 27 26 25 24 23 22 21 20 19 16 15 14 13 12 11 8 76543 0
cond
01110101
Rd
1111
Rs
00R1
Rm
SMMUL (Signed Most significant word Multiply) multiplies two signed 32-bit values, and extracts the most
significant 32 bits of the result. Optionally, you can specify that the result is rounded instead of being truncated. In this case, the constant
0x80000000 is added to the product before the high word is extracted.
Syntax
SMMUL{R}{<cond>} <Rd>, <Rm>, <Rs>
where:
R
Sets the R bit of the instruction to 1. The multiplication is rounded. If the R is omitted, sets the R bit to 0. The multiplication is truncated.
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first multiply operand. Specifies the register that contains the second multiply operand.
<Rd> <Rm> <Rs>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then if R == 1 then value = Rm * Rs + 0x80000000 else value = Rm * Rs Rd = value[63:32]
/* Signed multiplication */ /* Signed multiplication */
A4-162
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
You can use SMMUL in combination with QADD or QDADD to perform Q31 multiplies and multiply-accumulates. It has two advantages over a combination of SMULL with QADD or QDADD: you can round the product no scratch register is required for the least significant half of the product. You can also use SMMUL in optimized Fast Fourier Transforms and similar algorithms.
Notes
Use of R15 Early termination Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMMUL leaves all the flags unchanged.
Flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-163
ARM Instructions
A4.1.85 SMUAD
31 28 27 26 25 24 23 22 21 20 19 16 15 14 13 12 11 8 76543 0
cond
01110000
Rd
1111
Rs
00X1
Rm
SMUAD (Signed Dual Multiply Add) performs two signed 16 x 16-bit multiplications. It adds the products
together, giving a 32-bit result. Optionally, you can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow.
Syntax
SMUAD{X}{<cond>} <Rd>, <Rm>, <Rs>
where:
X
Sets the X bit of the instruction to 1, and the multiplications are bottom x top and top x bottom. If the X is omitted, sets the X bit to 0, and the multiplications are bottom x bottom and top x top.
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rm> <Rs>
Architecture version
ARMv6 and above.
Exceptions
None.
A4-164
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if X == 1 then operand2 = Rs Rotate_Right 16 else operand2 = Rs product1 = Rm[15:0] * operand2[15:0] /* Signed multiplication */ product2 = Rm[31:16] * operand2[31:16] /* Signed multiplication */ Rd = product1 + product2 if OverflowFrom(product1 + product2) then Q flag = 1
Usage
Use SMUAD for the first pair of multiplications in a sequence that uses the SMLAD instruction for the following multiplications, see SMLAD on page A4-144. You can use the X option for calculating the imaginary part of a product of complex numbers with 16-bit real and 16-bit imaginary parts.
Notes
Use of R15 Early termination Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMUAD leaves the N, Z, C and V flags unchanged.
N, Z, C and V flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-165
ARM Instructions
A4.1.86 SMUL<x><y>
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00010110
Rd
SBZ
Rs
1yx0
Rm
SMUL<x><y> (Signed Multiply BB, BT, TB, or TT) performs a signed multiply operation. The multiply acts on
two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. No overflow is possible during this instruction.
Syntax
SMUL<x><y>{<cond>} <Rd>, <Rm>, <Rs>
where:
<x>
Specifies which half of the source register <Rm> is used as the first multiply operand. If <x> is B, then x == 0 in the instruction encoding and the bottom half (bits[15:0]) of <Rm> is used. If <x> is T, then x == 1 in the instruction encoding and the top half (bits[31:16]) of <Rm> is used. Specifies which half of the source register <Rs> is used as the second multiply operand. If <y> is B, then y == 0 in the instruction encoding and the bottom half (bits[15:0]) of <Rs> is used. If <y> is T, then y == 1 in the instruction encoding and the top half (bits[31:16]) of <Rs> is used. Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the source register whose bottom or top half (selected by <x>) is the first multiply operand. Specifies the source register whose bottom or top half (selected by <y>) is the second multiply operand.
<y>
<cond>
<Rd> <Rm>
<Rs>
Architecture version
ARMv5TE and above.
Exceptions
None.
A4-166
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if (x == 0) then operand1 = SignExtend(Rm[15:0]) else /* x == 1 */ operand1 = SignExtend(Rm[31:16]) if (y == 0) then operand2 = SignExtend(Rs[15:0]) else /* y == 1 */ operand2 = SignExtend(Rs[31:16]) Rd = operand1 * operand2
Usage
In addition to its straightforward uses for integer multiplies, this instruction can be used in combination with QADD, QDADD, and QDSUB to perform multiplies, multiply-accumulates, and multiply-subtracts on Q15 numbers. See the Usage sections on page A4-93, page A4-100, and page A4-102 for examples.
Notes
Use of R15 Early termination Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMUL<x><y> does not affect the N, Z, C, V, or Q flags.
Condition flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-167
ARM Instructions
A4.1.87 SMULL
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0000110S
RdHi
RdLo
Rs
1001
Rm
SMULL (Signed Multiply Long) multiplies two 32-bit signed values to produce a 64-bit result. SMULL can optionally update the condition code flags, based on the 64-bit result.
Syntax
SMULL{<cond>}{S} <RdLo>, <RdHi>, <Rm>, <Rs>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction updates the CPSR by setting the N and Z flags according to the result of the multiplication. If S is omitted, the S bit of the instruction is set to 0 and the entire CPSR is unaffected by the instruction. Stores the lower 32 bits of the result. Stores the upper 32 bits of the result. Holds the signed value to be multiplied with the value of <Rs>. Holds the signed value to be multiplied with the value of <Rm>.
S
<RdLo> <RdHi> <Rm> <Rs>
Architecture version
All.
Exceptions
None.
A4-168
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then RdHi = (Rm * Rs)[63:32] /* Signed multiplication */ RdLo = (Rm * Rs)[31:0] if S == 1 then N Flag = RdHi[31] Z Flag = if (RdHi == 0) and (RdLo == 0) then 1 else 0 C Flag = unaffected /* See "C and V flags" note */ V Flag = unaffected /* See "C and V flags" note */
Usage
SMULL multiplies signed variables to produce a 64-bit result in two general-purpose registers.
Notes
Use of R15 Specifying R15 for register <RdHi>, <RdLo>, <Rm>, or <Rs> has UNPREDICTABLE results.
Operand restriction <RdHi> and <RdLo> must be distinct registers, or the results are UNPREDICTABLE. Specifying the same register for either <RdHi> and <Rm>, or <RdLo> and <Rm>, was previously described as producing UNPREDICTABLE results. There is no restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 implementations do not require this restriction either, because high performance multipliers read all their operands prior to writing back any results. Early termination If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMULLS is defined to leave the C and V flags unchanged in ARMv5 and above. In earlier versions of the architecture, the values of the C and V flags were UNPREDICTABLE after an SMULLS instruction.
C and V flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-169
ARM Instructions
A4.1.88 SMULW<y>
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00010010
Rd
SBZ
Rs
1y10
Rm
SMULW<y> (Signed Multiply Word B and T) performs a signed multiply operation. The multiply acts on a
signed 32-bit quantity and a signed 16-bit quantity, with the latter being taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are written to the destination register. The bottom 16 bits of the 48-bit product are ignored. No overflow is possible during this instruction.
Syntax
SMULW<y>{<cond>} <Rd>, <Rm>, <Rs>
where:
<y>
Specifies which half of the source register <Rs> is used as the second multiply operand. If <y> is B, then y == 0 in the instruction encoding and the bottom half (bits[15:0]) of <Rs> is used. If <y> is T, then y == 1 in the instruction encoding and the top half (bits[31:16]) of <Rs> is used. Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the source register which contains the 32-bit first operand. Specifies the source register whose bottom or top half (selected by <y>) is the second operand.
<cond>
<Rd> <Rm> <Rs>
Architecture version
ARMv5TE and above.
Exceptions
None.
A4-170
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if (y == 0) then operand2 = SignExtend(Rs[15:0]) else /* y == 1 */ operand2 = SignExtend(Rs[31:16]) Rd = (Rm * operand2)[47:16] /* Signed multiplication */
Usage
In addition to its straightforward uses for integer multiplies, this instruction can be used in combination with QADD, QDADD, and QDSUB to perform multiplies, multiply-accumulates and multiply-subtracts between Q31 and Q15 numbers. See the Usage sections on page A4-93, page A4-100, and page A4-102 for examples.
Notes
Use of R15 Early termination Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMULW<y> leaves all the flags unchanged.
Flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-171
ARM Instructions
A4.1.89 SMUSD
31 28 27 26 25 24 23 22 21 20 19 16 15 14 13 12 11 8 76543 0
cond
01110000
Rd
1111
Rs
01X1
Rm
SMUSD (Signed Dual Multiply Subtract) performs two signed 16 x 16-bit multiplications. It subtracts one product from the other, giving a 32-bit result.
Optionally, you can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication. Overflow cannot occur.
Syntax
SMUSD{X}{<cond>} <Rd>, <Rm>, <Rs>
where:
X
Sets the X bit of the instruction to 1. The multiplications are bottom x top and top x bottom. If the X is omitted, sets the X bit to 0. The multiplications are bottom x bottom and top x top.
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first multiply operand. Specifies the register that contains the second multiply operand.
<Rd> <Rm> <Rs>
Architecture version
ARMv6 and above.
Exceptions
None.
A4-172
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then if X == 1 then operand2 = Rs Rotate_Right 16 else operand2 = Rs product1 = Rm[15:0] * operand2[15:0] product2 = Rm[31:16] * operand2[31:16] Rd = product1 - product2
/* Signed multiplication */ /* Signed multiplication */ /* Signed subtraction */
Usage
You can use SMUSD for calculating the real part of a complex product of complex numbers with 16-bit real and 16-bit imaginary parts.
Notes
Use of R15 Early termination Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results. If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
SMUSD leaves all the flags unchanged.
Flags
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-173
ARM Instructions
A4.1.90 SRS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 7 54 0
1 1 1 1 1 0 0 PU1W0 1 1 0 1
SBZ
0101
SBZ
mode
SRS (Store Return State) stores the R14 and SPSR of the current mode to the word at the specified address
and the following word respectively. The address is determined from the banked version of R13 belonging to a specified mode.
Syntax
SRS<addressing_mode> #<mode>{!}
where:
<addressing_mode>
Is similar to the <addressing_mode> in LDM and STM instructions, see Addressing Mode 4 Load and Store Multiple on page A5-41, but with the following differences:
<mode>
The base register, Rn, is the banked version of R13 for the mode specified by <mode>, rather than the current mode. The number of registers to store is 2. The register list is {R14, SPSR}, with both R14 and the SPSR being the versions belonging to the current mode.
Specifies the number of the mode whose banked register is used as the base register for <addressing_mode>. The mode number is the 5-bit encoding of the chosen mode in a PSR, as described in The mode bits on page A2-14. If present, sets the W bit. This causes the instruction to write a modified value back to its base register, in a manner similar to that specified for Addressing Mode 4 - Load and Store Multiple on page A5-41. If ! is omitted, the W bit is 0 and the instruction does not change the base register.
!
Architecture version
ARMv6 and above.
Exceptions
Data Abort.
A4-174
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() address = start_address Memory[address,4] = R14 if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,4) if CurrentModeHasSPSR() then Memory[address+4,4] = SPSR if Shared(address+4) then /* from ARMv6 */ physical_address = TLB(address+4) ClearExclusiveByAddress(physical_address,processor_id,4) else UNPREDICTABLE assert end_address == address + 8
where start_address and end_address are determined as described in Addressing Mode 4 - Load and Store Multiple on page A5-41, with the following modifications:
Number_Of_Set_Bits_in(register_list) evaluates to 2, rather than depending on bits[15:0] of the
instruction.
Rn is the banked version of R13 belonging to the mode specified by the instruction, rather than being the version of R13 of the current mode.
Notes
Data Abort For details of the effects of this instruction if a Data Abort occurs, see Data Abort (data access memory abort) on page A2-21.
Non word-aligned addresses In ARMv6, an address with bits[1:0] != 0b00 causes an alignment exception if CP15 register 1 bits U==1 or A==1. Otherwise, SRS behaves as if bits[1:0] are 0b00. Time order The time order of the accesses to individual words of memory generated by SRS is not architecturally defined. Do not use this instruction on memory-mapped I/O locations where access order matters.
User and System modes
SRS is UNPREDICTABLE in User and System modes, because they do not have SPSRs.
Note
In User mode, SRS must not give access to any banked registers belonging to other modes. This would constitute a security hole. Condition Unlike most other ARM instructions, SRS cannot be executed conditionally.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-175
ARM Instructions
A4.1.91 SSAT
31 28 27 26 25 24 23 22 21 20 16 15 12 11 76543 0
cond
0110101
sat_imm
Rd
shift_imm
sh 0 1
Rm
SSAT (Signed Saturate) saturates a signed value to a signed range. You can choose the bit position at which
saturation occurs. You can apply a shift to the value before the saturation occurs. The Q flag is set if the operation saturates.
Syntax
SSAT{<cond>} <Rd>, #<immed>, <Rm>{, <shift>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the bit position for saturation, in the range 1 to 32. It is encoded in the sat_imm field of the instruction as <immed>-1. Specifies the register that contains the signed value to be saturated. Specifies the optional shift. If present, it must be one of:
LSL #N. N must be in the range 0 to 31. This is encoded as sh == 0 and shift_imm == N. ASR #N. N must be in the range 1 to 32. This is encoded as sh == 1 and either shift_imm == 0 for N == 32, or shift_imm == N otherwise.
<Rd> <immed>
<Rm> <shift>
If <shift> is omitted, LSL #0 is used.
Return
The value returned in Rd is: 2(n1) X 2(n1) 1 if X is < 2(n1) if 2(n1) <= X <= 2(n1) 1 if X > 2(n1) 1
where n is <immed>, and X is the shifted value from Rm.
A4-176
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then if shift == 1 then if shift_imm == 0 then operand = (Rm Artihmetic_Shift_Right 32)[31:0] else operand = (Rm Artihmetic_Shift_Right shift_imm)[31:0] else operand = (Rm Logical_Shift_Left shift_imm)[31:0] Rd = SignedSat(operand, sat_imm + 1) if SignedDoesSat(operand, sat_imm + 1) then Q Flag = 1
Usage
You can use SSAT in various DSP algorithms that require scaling and saturation of signed data.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-177
ARM Instructions
A4.1.92 SSAT16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01101010
sat_imm
Rd
SBO
0011
Rm
SSAT16 saturates two 16-bit signed values to a signed range. You can choose the bit position at which saturation occurs. The Q flag is set if either halfword operation saturates.
Syntax
SSAT16{<cond>} <Rd>, #<immed>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the bit position for saturation. This lies in the range 1 to 16. It is encoded in the sat_imm field of the instruction as <immed>-1. Specifies the register that contains the signed value to be saturated.
<Rd> <immed>
<Rm>
Return
The value returned in each half of Rd is: 2(n1) X 2(n1) 1 if X is < 2(n1) if 2(n1) <= X <= 2(n1) 1 if X > 2(n1) 1
where n is <immed>, and X is the value from the corresponding half of Rm.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-178
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then Rd[15:0] = SignedSat(Rm[15:0], sat_imm + 1) Rd[31:16] = SignedSat(Rm[31:16], sat_imm + 1) if SignedDoesSat(Rm[15:0], sat_imm + 1) OR SignedDoesSat(Rm[31:16], sat_imm + 1) then Q Flag = 1
Usage
You can use SSAT16 in various DSP algorithms that require saturation of signed data.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-179
ARM Instructions
A4.1.93 SSUB16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100001
Rn
Rd
SBO
0111
Rm
SSUB16 (Signed Subtract) performs two 16-bit signed integer subtractions. It sets the GE bits in the CPSR according to the results of the subtractions.
Syntax
SSUB16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[15:0] - Rm[15:0] Rd[15:0] = diff[15:0] GE[1:0] = if diff >= 0 then 0b11 diff = Rn[31:16] - Rm[31:16] Rd[31:16] = diff[15:0] GE[3:2] = if diff >= 0 then 0b11 /* Signed subtraction */ else 0 /* Signed subtraction */ else 0
A4-180
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
Use SSUB16 to speed up operations on arrays of halfword data. This is similar to the way you can use SADD16. See the usage subsection for SADD16 on page A4-119 for details. You can also use SSUB16 for operations on complex numbers that are held as pairs of 16-bit integers or Q15 numbers. If you hold the real and imaginary parts of a complex number in the bottom and top half of a register respectively, then the instruction:
SSUB16 Rd, Ra, Rb
performs the complex arithmetic operation Rd = Ra - Rb.
SSUB16 sets the GE flags according to the results of each subtraction. You can use these in a following SEL instruction. See SEL on page A4-127 for further information.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-181
ARM Instructions
A4.1.94 SSUB8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100001
Rn
Rd
SBO
1111
Rm
SSUB8 performs four 8-bit signed integer subtractions. It sets the GE bits in the CPSR according to the results of the subtractions.
Syntax
SSUB8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[7:0] - Rm[7:0] /* Signed Rd[7:0] = diff[7:0] GE[0] = if diff >= 0 then 1 else 0 diff = Rn[15:8] - Rm[15:8] /* Signed Rd[15:8] = diff[7:0] GE[1] = if diff >= 0 then 1 else 0 diff = Rn[23:16] - Rm[23:16] /* Signed Rd[23:16] = diff[7:0] GE[2] = if diff >= 0 then 1 else 0 diff = Rn[31:24] - Rm[31:24] /* Signed Rd[31:24] = diff[7:0] GE[3] = if diff >= 0 then 1 else 0 subtraction */
subtraction */
subtraction */
subtraction */
A4-182
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
Use SSUB8 to speed up operations on arrays of byte data. This is similar to the way you can use SADD16 to speed up operations on halfword data. See the usage subsection for SADD16 on page A4-119 for details.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-183
ARM Instructions
A4.1.95 SSUBADDX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100001
Rn
Rd
SBO
0101
Rm
SSUBADDX (Signed Subtract and Add with Exchange) performs one 16-bit signed integer subtraction and one
16-bit signed integer addition. It exchanges the two halfwords of the second operand before it performs the arithmetic.
SSUBADDX sets the GE bits in the CPSR according to the results.
Syntax
SSUBADDX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[31:16] - Rm[15:0] /* Signed subtraction */ Rd[31:16] = diff[15:0] GE[3:2] = if diff >= 0 then 0b11 else 0 sum = Rn[15:0] + Rm[31:16] /* Signed addition */ Rd[15:0] = sum[15:0] GE[1:0] = if sum >= 0 then 0b11 else 0
A4-184
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
You can use SSUBADDX for operations on complex numbers that are held as pairs of 16-bit integers or Q15 numbers. If you hold the real and imaginary parts of a complex number in the bottom and top half of a register respectively, then the instruction:
SSUBADDX Rd, Ra, Rb
performs the complex arithmetic operation Rd = Ra - i * Rb.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-185
ARM Instructions
A4.1.96 STC
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 0
cond
1 1 0 P UNW0
Rn
CRd
cp_num
8_bit_word_offset
STC (Store Coprocessor) stores data from a coprocessor to a sequence of consecutive memory addresses. If no coprocessors indicate that they can execute the instruction, an Undefined Instruction exception is generated.
Syntax
STC{<cond>}{L} STC2{L} <coproc>, <CRd>, <addressing_mode> <coproc>, <CRd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the condition field of the instruction to be set to 0b1111. This provides additional opcode space for coprocessor designers. The resulting instructions can only be executed unconditionally. Sets the N bit (bit[22]) in the instruction to 1 and specifies a long store (for example, double-precision instead of single-precision data transfer). If L is omitted, the N bit is 0 and the instruction specifies a short store. Specifies the name of the coprocessor, and causes the corresponding coprocessor number to be placed in the cp_num field of the instruction. The standard generic coprocessor names are p0, p1, ..., p15. Specifies the coprocessor source register.
STC2
L
<coproc>
<CRd>
<addressing_mode>
Is described in Addressing Mode 5 - Load and Store Coprocessor on page A5-49. It determines the P, U, Rn, W and 8_bit_word_offset bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
STC is in all versions. STC2 is in ARMv5 and above.
A4-186
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
Undefined Instruction, Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() if ConditionPassed(cond) then address = start_address Memory[address,4] = value from Coprocessor[cp_num] if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,4) while (NotFinished(coprocessor[cp_num])) address = address + 4 Memory[address,4] = value from Coprocessor[cp_num] if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,4) /* See Summary of operation on page A2-49 */ assert address == end_address
Usage
STC is useful for storing coprocessor data to memory. The L (long) option controls the N bit and could be used to distinguish between a single- and double-precision transfer for a floating-point store instruction.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-187
ARM Instructions
Notes
Coprocessor fields Only instruction bits[31:23], bits[21:16} and bits[11:0] are defined by the ARM architecture. The remaining fields (bit[22] and bits[15:12]) are recommendations, for compatibility with ARM Development Systems. In the case of the Unindexed addressing mode (P==0, U==1, W==0), instruction bits[7:0] are also not ARM architecture-defined, and can be used to specify additional coprocessor options. Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Non word-aligned addresses For CP15_reg1_Ubit == 0 the store coprocessor register instructions ignore the least significant two bits of address. For CP15_reg1_Ubit == 1, all non-word aligned accesses cause an alignment fault. Alignment If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor), and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception.
Unimplemented coprocessor instructions Hardware coprocessor support is optional, regardless of the architecture version. An implementation can choose to implement a subset of the coprocessor instructions, or no coprocessor instructions at all. Any coprocessor instructions that are not implemented instead cause an Undefined Instruction exception.
A4-188
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.97 STM (1)
31 28 27 26 25 24 23 22 21 20 19 16 15 0
cond
1 0 0 PU0W0
Rn
register_list
STM (1) (Store Multiple) stores a non-empty subset (or possibly all) of the general-purpose registers to
sequential memory locations.
Syntax
STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used.
<addressing_mode>
Is described in Addressing Mode 4 - Load and Store Multiple on page A5-41. It determines the P, U, and W bits of the instruction.
<Rn>
Specifies the base register used by <addressing_mode>. If R15 is specified as <Rn>, the result is UNPREDICTABLE. Sets the W bit, causing the instruction to write a modified value back to its base register Rn as specified in Addressing Mode 4 - Load and Store Multiple on page A5-41. If ! is omitted, the W bit is 0 and the instruction does not change its base register in this way. Is a list of registers, separated by commas and surrounded by { and }. It specifies the set of registers to be stored by the STM instruction. The registers are stored in sequence, the lowest-numbered register to the lowest memory address (start_address), through to the highest-numbered register to the highest memory address (end_address). For each of i=0 to 15, bit[i] in the register_list field of the instruction is 1 if Ri is in the list and 0 otherwise. If bits[15:0] are all zero, the result is UNPREDICTABLE. If R15 is specified in <registers>, the value stored is IMPLEMENTATION DEFINED. For more details, see Reading the program counter on page A2-9.
!
<registers>
Architecture version
All.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-189
ARM Instructions
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() if ConditionPassed(cond) then address = start_address for i = 0 to 15 if register_list[i] == 1 then Memory[address,4] = Ri address = address + 4 if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,4) /* See Summary of operation on page A2-49 */ assert end_address == address - 4
Usage
STM is useful as a block store instruction (combined with LDM it allows efficient block copy) and for stack operations. A single STM used in the sequence of a procedure can push the return address and general-purpose register values on to the stack, updating the stack pointer in the process.
Notes
Operand restrictions If <Rn> is specified in <registers> and base register write-back is specified: Data Abort If <Rn> is the lowest-numbered register specified in <registers>, the original value of <Rn> is stored. Otherwise, the stored value of <Rn> is UNPREDICTABLE.
For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Non word-aligned addresses For CP15_reg1_Ubit == 0, the STM[1] instruction ignores the least significant two bits of address. For CP15_reg1_Ubit == 1, all non-word aligned accesses cause an alignment fault. Alignment If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor), and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception. The time order of the accesses to individual words of memory generated by this instruction is only defined in some circumstances. See Memory access restrictions on page B2-13 for details.
Time order
A4-190
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.98 STM (2)
31 28 27 26 25 24 23 22 21 20 19 16 15 0
cond
100PU100
Rn
register_list
STM (2) stores a subset (or possibly all) of the User mode general-purpose registers to sequential memory locations.
Syntax
STM{<cond>}<addressing_mode> <Rn>, <registers>^
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used.
<addressing_mode>
Is described in Addressing Mode 4 - Load and Store Multiple on page A5-41. It determines the P and U bits of the instruction. Only the forms of this addressing mode with W == 0 are available for this form of the STM instruction.
<Rn>
Specifies the base register used by <addressing_mode>. If R15 is specified as the base register <Rn>, the result is UNPREDICTABLE. Is a list of registers, separated by commas and surrounded by { and }. It specifies the set of registers to be stored by the STM instruction. The registers are stored in sequence, the lowest-numbered register to the lowest memory address (start_address), through to the highest-numbered register to the highest memory address (end_address). For each of i=0 to 15, bit[i] in the register_list field of the instruction is 1 if Ri is in the list and 0 otherwise. If bits[15:0] are all zero, the result is UNPREDICTABLE. If R15 is specified in <registers> the value stored is IMPLEMENTATION DEFINED. For more details, see Reading the program counter on page A2-9.
<registers>
^
For an STM instruction, indicates that User mode registers are to be stored.
Architecture version
All.
Exceptions
Data Abort.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-191
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() if ConditionPassed(cond) then address = start_address for i = 0 to 15 if register_list[i] == 1 Memory[address,4] = Ri_usr address = address + 4 if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,4) /* See Summary of operation on page A2-49 */ assert end_address == address - 4
Usage
Use STM (2) to store the User mode registers when the processor is in a privileged mode (useful when performing process swaps, and in instruction emulators).
Notes
Write-back Setting bit 21, the W bit, has UNPREDICTABLE results.
User and System mode This instruction is UNPREDICTABLE in User or System mode. Base register mode Data Abort For the purpose of address calculation, the base register is read from the current processor mode registers, not the User mode registers. For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Non word-aligned addresses For CP15_reg1_Ubit == 0, the STM[2] instruction ignores the least significant two bits of address. For CP15_reg1_Ubit == 1, all non-word aligned accesses cause an alignment fault Alignment If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor), and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception. The time order of the accesses to individual words of memory generated by this instruction is only defined in some circumstances. See Memory access restrictions on page B2-13 for details. In ARM architecture versions earlier than ARMv6, this form of STM must not be followed by an instruction that accesses banked registers (a following NOP is a good way to ensure this).
Time order
Banked registers
A4-192
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.99 STR
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
0 1 I PU0W0
Rn
Rd
addr_mode
STR (Store Register) stores a word from a register to memory.
Syntax
STR{<cond>} <Rd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the source register for the operation. If R15 is specified for <Rd>, the value stored is IMPLEMENTATION DEFINED. For more details, see Reading the program counter on page A2-9.
<Rd>
<addressing_mode>
Is described in Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18. It determines the I, P, U, W, Rn and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() if ConditionPassed(cond) then Memory[address,4] = Rd if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,4) /* See Summary of operation on page A2-49 */
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-193
ARM Instructions
Usage
Combined with a suitable addressing mode, STR stores 32-bit data from a general-purpose register into memory. Using the PC as the base register allows PC-relative addressing, which facilitates position-independent code.
Notes
Operand restrictions If <addressing_mode> specifies base register write-back, and the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, STR ignores the least significant two bits of the address. This is different from the LDR behavior. Alignment checking (taking a data abort when address[1:0] != 0b00), and support for a big-endian (BE-32) data format are implementation options. From ARMv6, a byte- invariant mixed-endian format is supported, along with an alignment checking option. The pseudo-code for the ARMv6 case assumes that unaligned mixed-endian support is configured, with the endianness of the transfer defined by the CPSR E-bit. For more details on endianness and alignment see Endian support on page A2-30and Unaligned access support on page A2-38.
A4-194
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.100 STRB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
0 1 I PU1W0
Rn
Rd
addr_mode
STRB (Store Register Byte) stores a byte from the least significant byte of a register to memory.
Syntax
STR{<cond>}B <Rd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the source register for the operation. If R15 is specified for <Rd>, the result is
UNPREDICTABLE.
<Rd>
<addressing_mode>
Is described in Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18. It determines the I, P, U, W, Rn and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
Operation
processor_id = ExecutingProcessor() if ConditionPassed(cond) then Memory[address,1] = Rd[7:0] if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,1) /* See Summary of operation on page A2-49 */
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-195
ARM Instructions
Usage
Combined with a suitable addressing mode, STRB writes the least significant byte of a general-purpose register to memory. Using the PC as the base register allows PC-relative addressing, which facilitates position-independent code.
Notes
Operand restrictions If <addressing_mode> specifies base register write-back, and the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
A4-196
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.101 STRBT
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
01I0U110
Rn
Rd
addr_mode
STRBT (Store Register Byte with Translation) stores a byte from the least significant byte of a register to
memory. If the instruction is executed when the processor is in a privileged mode, the memory system is signaled to treat the access as if the processor were in User mode.
Syntax
STR{<cond>}BT <Rd>, <post_indexed_addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the source register for the operation. If R15 is specified for <Rd>, the result is
UNPREDICTABLE.
<Rd>
<post_indexed_addressing_mode>
Is described in Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18. It determines the I, U, Rn and addr_mode bits of the instruction. Only post-indexed forms of Addressing Mode 2 are available for this instruction. These forms have P == 0 and W == 0, where P and W are bit[24] and bit[21] respectively. This instruction uses P == 0 and W == 1 instead, but the addressing mode is the same in all other respects. The syntax of all forms of <post_indexed_addressing_mode> includes a base register <Rn>. All forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-197
ARM Instructions
Operation
processor_id = ExecutingProcessor() if ConditionPassed(cond) then Memory[address,1] = Rd[7:0] if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,1) /* See Summary of operation on page A2-49 */
Usage
STRBT can be used by a (privileged) exception handler that is emulating a memory access instruction which would normally execute in User mode. The access is restricted as if it had User mode privilege.
Notes
User mode If this instruction is executed in User mode, an ordinary User mode access is performed.
Operand restrictions If the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
A4-198
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.102 STRD
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
0 0 0 PU IW0
Rn
Rd
addr_mode 1 1 1 1 addr_mode
STRD (Store Registers Doubleword) stores a pair of ARM registers to two consecutive words of memory. The
pair of registers is restricted to being an even-numbered register and the odd-numbered register that immediately follows it (for example, R10 and R11). A greater variety of addressing modes is available than for a two-register STM.
Syntax
STR{<cond>}D <Rd>, <addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the even-numbered register that is stored to the memory word addressed by <addressing_mode>. The immediately following odd-numbered register is stored to the next memory word. If <Rd> is R14, which would specify R15 as the second source register, the instruction is UNPREDICTABLE. If <Rd> specifies an odd-numbered register, the instruction is UNDEFINED.
<Rd>
<addressing_mode>
Is described in Addressing Mode 3 - Miscellaneous Loads and Stores on page A5-33. It determines the P, U, I, W, Rn, and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back). The address generated by <addressing_mode> is the address of the lower of the two words stored by the STRD instruction. The address of the higher word is generated by adding 4 to this address.
Architecture version
ARMv5TE and above, excluding ARMv5TExP.
Exceptions
Data Abort.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-199
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() if ConditionPassed(cond) then if (Rd is even-numbered) and (Rd is not R14) and (address[1:0] == 0b00) and ((CP15_reg1_Ubit == 1) or (address[2] == 0)) then Memory[address,4] = Rd Memory[address+4,4] = R(d+1) else UNPREDICTABLE if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,4) if Shared(address+4) physical_address = TLB(address+4) ClearExclusiveByAddress(physical_address,processor_id,4)
A4-200
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Notes
Operand restrictions If <addressing_mode> performs base register write-back and the base register <Rn> is one of the two source registers of the instruction, the results are UNPREDICTABLE. Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not 64-bit aligned, the instruction is UNPREDICTABLE. Alignment checking (taking a data abort), and support for a big-endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed-endian format is supported, along with alignment checking options; modulo4 and modulo8. The pseudo-code for the ARMv6 case assumes that unaligned mixed-endian support is configured, with the endianness of the transfer defined by the CPSR E-bit. For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38. Time order The time order of the accesses to the two memory words is not architecturally defined. In particular, an implementation is allowed to perform the two 32-bit memory accesses in either order, or to combine them into a single 64-bit memory access.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-201
ARM Instructions
A4.1.103 STREX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00011000
Rn
Rd
SBO
1001
Rm
STREX (Store Register Exclusive) performs a conditional store to memory. The store only occurs if the
executing processor has exclusive access to the memory addressed.
Syntax
STREX{<cond>} <Rd>, <Rm>, [<Rn>]
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the returned status value. The value returned is: 0 if the operation updates memory 1 if the operation fails to update memory. Specifies the register containing the word to be stored to memory. Specifies the register containing the address.
<Rd>
<Rm> <Rn>
Architecture version
ARMv6 and above.
Exceptions
Data Abort.
A4-202
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) if ConditionPassed(cond) then processor_id = ExecutingProcessor() physical_address = TLB(Rn) if IsExclusiveLocal(physical_address, processor_id, 4) then if Shared(Rn) == 1 then if IsExclusiveGlobal(physical_address, processor_id, 4) then Memory[Rn,4] = Rm Rd = 0 ClearExclusiveByAddress(physical_address,processor_id,4) else Rd = 1 else Memory[Rn,4] = Rm Rd = 0 else Rd = 1 ClearExclusiveLocal(processor_id) /* See Summary of operation on page A2-49 */ /* The notes take precedence over any implied atomicity or order of events indicated in the pseudo-code */
Usage
Use STREX in combination with LDREX to implement inter-process communication in multiprocessor and shared memory systems. See LDREX on page A4-52 for further information.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rn>, or <Rm> has UNPREDICTABLE results.
Operand restrictions
<Rd> must be distinct from both <Rm> and <Rn>, otherwise the results are UNPREDICTABLE.
Data Abort
For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. If a Data Abort occurs during execution of a STREX instruction: memory is not updated <Rd> is not updated. If CP15 register 1(A,U) != (0,0) and Rd<1:0> != 0b00, an alignment exception will be taken. There is no support for unaligned Load Exclusive. If Rd<1:0> != 0b00 and (A,U) = (0,0), the result is UNPREDICTABLE
Alignment
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-203
ARM Instructions
A4.1.104 STRH
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0 0 0 PU IW0
Rn
Rd
addr_mode 1 0 1 1 addr_mode
STRH (Store Register Halfword) stores a halfword from the least significant halfword of a register to memory. If the address is not halfword-aligned, the result is UNPREDICTABLE.
Syntax
STR{<cond>}H <Rd>, <addressing_mode>
where:
<cond> <Rd>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the source register for the operation. If R15 is specified for <Rd>, the result is
UNPREDICTABLE.
<addressing_mode>
Is described in Addressing Mode 3 - Miscellaneous Loads and Stores on page A5-33. It determines the P, U, I, W, Rn and addr_mode bits of the instruction. The syntax of all forms of <addressing_mode> includes a base register <Rn>. Some forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
A4-204
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() if ConditionPassed(cond) then if (CP15_reg1_Ubit == 0) then if address[0] == 0b0 then Memory[address,2] = Rd[15:0] else Memory[address,2] = UNPREDICTABLE else /* CP15_reg1_Ubit ==1 */ Memory[address,2] = Rd[15:0] if Shared(address) then /* ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,2) /* See Summary of operation on page A2-49 */
Usage
Combined with a suitable addressing mode, STRH allows 16-bit data from a general-purpose register to be stored to memory. Using the PC as the base register allows PC-relative addressing, to facilitate position-independent code.
Notes
Operand restrictions If <addressing_mode> specifies base register write-back, and the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not halfword aligned, the instruction is Alignment checking (taking a data abort when address[0] != 0), and support for a big-endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed-endian format is supported, along with an alignment checking option. The pseudo-code for the ARMv6 case assumes that mixed-endian support is configured, with the endianness of the transfer defined by the CPSR E-bit. For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
UNPREDICTABLE.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-205
ARM Instructions
A4.1.105 STRT
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
01I0U010
Rn
Rd
addr_mode
STRT (Store Register with Translation) stores a word from a register to memory. If the instruction is executed when the processor is in a privileged mode, the memory system is signaled to treat the access as if the processor was in User mode.
Syntax
STR{<cond>}T <Rd>, <post_indexed_addressing_mode>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the source register for the operation. If R15 is specified for <Rd>, the value stored is IMPLEMENTATION DEFINED. For more details, see Reading the program counter on page A2-9.
<Rd>
<post_indexed_addressing_mode>
Is described in Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18. It determines the I, U, Rn and addr_mode bits of the instruction. Only post-indexed forms of Addressing Mode 2 are available for this instruction. These forms have P == 0 and W == 0, where P and W are bit[24] and bit[21] respectively. This instruction uses P == 0 and W == 1 instead, but the addressing mode is the same in all other respects. The syntax of all forms of <post_indexed_addressing_mode> includes a base register <Rn>. All forms also specify that the instruction modifies the base register value (this is known as base register write-back).
Architecture version
All.
Exceptions
Data Abort.
A4-206
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() if ConditionPassed(cond) then Memory[address,4] = Rd if Shared(address) then /* ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,4) /* See Summary of operation on page A2-49 */
Usage
STRT can be used by a (privileged) exception handler that is emulating a memory access instruction that
would normally execute in User mode. The access is restricted as if it had User mode privilege.
Notes
User mode If this instruction is executed in User mode, an ordinary User mode access is performed.
Operand restrictions If the same register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE. Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. As for STR, see STR on page A4-193. If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor), and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-207
ARM Instructions
A4.1.106 SUB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I0010S
Rn
Rd
shifter_operand
SUB (Subtract) subtracts one value from a second value.
The second value comes from a register. The first value can be either an immediate value or a value from a register, and can be shifted before the subtraction.
SUB can optionally update the condition code flags, based on the result.
Syntax
SUB{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Sets the S bit (bit[20]) in the instruction to 1 and specifies that the instruction updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction. Two types of CPSR update can occur when S is specified: If <Rd> is not R15, the N and Z flags are set according to the result of the subtraction, and the C and V flags are set according to whether the subtraction generated a borrow (unsigned underflow) and a signed overflow, respectively. The rest of the CPSR is unchanged. If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of the instruction is UNPREDICTABLE if executed in User mode or System mode, because these modes do not have an SPSR.
S
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the first operand.
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not SUB. Instead, see Extending the instruction set on page A3-32 to determine which instruction it is.
Architecture version
All.
A4-208
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd = Rn - shifter_operand if S == 1 and Rd == R15 then if CurrentModeHasSPSR() then CPSR = SPSR else UNPREDICTABLE else if S == 1 then N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rn - shifter_operand) V Flag = OverflowFrom(Rn - shifter_operand)
Usage
Use SUB to subtract one value from another. To decrement a register value (in Ri) use:
SUB Ri, Ri, #1
SUBS is useful as a loop counter decrement, as the loop branch can test the flags for the appropriate
termination condition, without the need for a separate compare instruction:
SUBS Ri, Ri, #1
This both decrements the loop counter in Ri and checks whether it has reached zero. You can use SUB, with the PC as its destination register and the S bit set, to return from interrupts and various other types of exception. See Exceptions on page A2-16 for more details.
Notes
C flag If S is specified, the C flag is set to: 1 if no borrow occurs 0 if a borrow does occur. In other words, the C flag is used as a NOT(borrow) flag. This inversion of the borrow condition is used by subsequent instructions: SBC and RSC use the C flag as a NOT(borrow) operand, performing a normal subtraction if C == 1 and subtracting one more than usual if C == 0. The HS (unsigned higher or same) and LO (unsigned lower) conditions are equivalent to CS (carry set) and CC (carry clear) respectively.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-209
ARM Instructions
A4.1.107 SWI
31 28 27 26 25 24 23 0
cond
1111
immed_24
SWI (Software Interrupt) causes a SWI exception (see Exceptions on page A2-16).
Syntax
SWI{<cond>} <immed_24>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Is a 24-bit immediate value that is put into bits[23:0] of the instruction. This value is ignored by the ARM processor, but can be used by an operating system SWI exception handler to determine what operating system service is being requested (see Usage on page A4-211 below for more details).
<immed_24>
Architecture version
All.
Exceptions
Software interrupt.
Operation
if ConditionPassed(cond) then R14_svc = address of next instruction after the SWI instruction SPSR_svc = CPSR CPSR[4:0] = 0b10011 /* Enter Supervisor mode */ CPSR[5] =0 /* Execute in ARM state */ /* CPSR[6] is unchanged */ CPSR[7] =1 /* Disable normal interrupts */ /* CPSR[8] is unchanged */ CPSR[9] = CP15_reg1_EEbit if high vectors configured then PC = 0xFFFF0008 else PC = 0x00000008
A4-210
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
SWI is used as an operating system service call. The method used to select which operating system service
is required is specified by the operating system, and the SWI exception handler for the operating system determines and provides the requested service. Two typical methods are: The 24-bit immediate in the instruction specifies which service is required, and any parameters needed by the selected service are passed in general-purpose registers. The 24-bit immediate in the instruction is ignored, general-purpose register R0 is used to select which service is wanted, and any parameters needed by the selected service are passed in other general-purpose registers.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-211
ARM Instructions
A4.1.108 SWP
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00010000
Rn
Rd
SBZ
1001
Rm
SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given by the value of register <Rn>. The value of register <Rm> is then stored to the memory address given by the value of <Rn>, and the original loaded value is written to register <Rd>. If the same register is specified for <Rd> and <Rm>, this instruction swaps the value of the register and the value at the memory address.
Syntax
SWP{<cond>} <Rd>, <Rm>, [<Rn>]
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the instruction. Contains the value that is stored to memory. Contains the memory address to load from.
<Rd> <Rm> <Rn>
Architecture version
All (deprecated in ARMv6).
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() if ConditionPassed(cond) then if (CP15_reg1_Ubit == 0) then temp = Memory[address,4] Rotate_Right (8 * address[1:0]) Memory[address,4] = Rm Rd = temp else /* CP15_reg1_Ubit ==1 */ temp = Memory[address,4] Memory[address,4] = Rm Rd = temp if Shared(address) then /* ARMv6 */
A4-212
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,4) /* See Summary of operation on page A2-49 */
Usage
You can use SWP to implement semaphores. This instruction is deprecated in ARMv6. Software should migrate to using the Load/Store exclusive instructions described in Synchronization primitives on page A2-44.
Notes
Use of R15 If R15 is specified for <Rd>, <Rn>, or <Rm>, the result is UNPREDICTABLE.
Operand restrictions If the same register is specified as <Rn> and <Rm>, or <Rn> and <Rd>, the result is
UNPREDICTABLE.
Data Abort
If a precise Data Abort is signaled on either the load access or the store access, the loaded value is not written to <Rd>. If a precise Data Abort is signaled on the load access, the store access does not occur. Prior to ARMv6, the alignment rules are the same as for an LDR on the read (see LDR on page A4-43) and an STR on the write (see STR on page A4-193). Alignment checking (taking a data abort when address[1:0] != 0b00), and support for a big-endian (BE-32) data format are implementation options. From ARMv6, if CP15 register 1(A,U) != (0,0) and Rn[1:0] != 0b00, an alignment exception is taken. If CP15 register 1(A,U) == (0,0), the behavior is the same as the behavior before ARMv6. For more details on endianness and alignment see Endian support on page A2-30 and Unaligned access support on page A2-38.
Alignment
Memory model considerations Swap is an atomic operation for all accesses, cached and non-cached. The swap operation does not include any memory barrier guarantees. For example, it does not guarantee flushing of write buffers, which is an important consideration on multiprocessor systems.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-213
ARM Instructions
A4.1.109 SWPB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
00010100
Rn
Rd
SBZ
1001
Rm
SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address given by the value of register <Rn>. The value of the least significant byte of register <Rm> is stored to the memory address given by <Rn>, the original loaded value is zero-extended to a 32-bit word, and the word is written to register <Rd>. If the same register is specified for <Rd> and <Rm>, this instruction swaps the value
of the least significant byte of the register and the byte value at the memory address.
Syntax
SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register for the instruction. Contains the value that is stored to memory. Contains the memory address to load from.
<Rd> <Rm> <Rn>
Architecture version
All (deprecated in ARMv6).
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() if ConditionPassed(cond) then temp = Memory[address,1] Memory[address,1] = Rm[7:0] Rd = temp if Shared(address) then /* ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address,processor_id,1) /* See Summary of operation on page A2-49 */
A4-214
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
You can use SWPB to implement semaphores. This instruction is deprecated in ARMv6. Software should migrate to using the Load /Store exclusive instructions described in Synchronization primitives on page A2-44.
Notes
Use of R15 If R15 is specified for <Rd>, <Rn>, or <Rm>, the result is UNPREDICTABLE.
Operand restrictions If the same register is specified as <Rn> and <Rm>, or <Rn> and <Rd>, the result is
UNPREDICTABLE.
Data Abort
If a precise Data Abort is signaled on either the load access or the store access, the loaded value is not written to <Rd>. If a precise Data Abort is signaled on the load access, the store access does not occur.
Memory model considerations Swap is an atomic operation for all accesses, cached and non-cached. The swap operation does not include any memory barrier guarantees. For example, it does not guarantee flushing of write buffers, which is an important consideration on multiprocessor systems.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-215
ARM Instructions
A4.1.110 SXTAB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 76543 0
cond
01101010
Rn
Rd
rotate SBZ 0 1 1 1
Rm
SXTAB extracts an 8-bit value from a register, sign extends it to 32 bits, and adds the result to the value in
another register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.
Syntax
SXTAB{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rn> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-216
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then operand2 = Rm Rotate_Right(8 * rotate) Rd = Rn + SignExtend(operand2[7:0])
Usage
You can use SXTAB to eliminate a separate sign-extension instruction in many instruction sequences that act on signed char values in C/C++.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
Note
Your assembler must fault the use of R15 for register <Rn>. Encoding If the <Rn> field of the instruction contains 0b1111, the instruction is an SXTB instruction instead, see SXTB on page A4-222.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-217
ARM Instructions
A4.1.111 SXTAB16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 76543 0
cond
01101000
Rn
Rd
rotate SBZ 0 1 1 1
Rm
SXTAB16 extracts two 8-bit values from a register, sign extends them to 16 bits each, and adds the results to
two 16-bit values from another register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.
Syntax
SXTAB16{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rn> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-218
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then operand2 = Rm Rotate_Right(8 * rotate) Rd[15:0] = Rn[15:0] + SignExtend(operand2[7:0]) Rd[31:16] = Rn[31:16] + SignExtend(operand2[23:16])
Usage
Use SXTAB16 when you need to keep intermediate values to higher precision while working on arrays of signed byte values. See UXTAB16 on page A4-276 for an example of a similar usage.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
Note
Your assembler must fault the use of R15 for register <Rn>. Encoding If the <Rn> field of the instruction contains 0b1111, the instruction is an SXTB16 instruction instead, see SXTB16 on page A4-224.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-219
ARM Instructions
A4.1.112 SXTAH
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 76543 0
cond
01101011
Rn
Rd
rotate SBZ 0 1 1 1
Rm
SXTAH extracts a 16-bit value from a register, sign extends it to 32 bits, and adds the result to a value in another register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.
Syntax
SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rn> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-220
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then operand2 = Rm Rotate_Right(8 * rotate) Rd = Rn + SignExtend(operand2[15:0])
Usage
You can use SXTAH to eliminate a separate sign-extension instruction in many instruction sequences that act on signed short values in C/C++.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
Note
Your assembler must fault the use of R15 for register <Rn>. Encoding If the <Rn> field of the instruction contains 0b1111, the instruction is an SXTH instruction instead, see SXTH on page A4-226.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-221
ARM Instructions
A4.1.113 SXTB
31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 76543 0
cond
011010101111
Rd
rotate SBZ 0 1 1 1
Rm
SXTB extracts an 8-bit value from a register and sign extends it to 32 bits. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.
Syntax
SXTB{<cond>} <Rd>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-222
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then operand2 = Rm Rotate_Right(8 * rotate) Rd[31:0] = SignExtend(operand2[7:0])
Usage
Use SXTB to sign-extend a byte to a word, for example in instruction sequences acting on signed char values in C/C++.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-223
ARM Instructions
A4.1.114 SXTB16
31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 76543 0
cond
011010001111
Rd
rotate SBZ 0 1 1 1
Rm
SXTB16 extracts two 8-bit values from a register and sign extends them to 16 bits each. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.
Syntax
SXTB16{<cond>} <Rd>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-224
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then operand2 = Rm Rotate_Right(8 * rotate) Rd[15:0] = SignExtend(operand2[7:0]) Rd[31:16] = SignExtend(operand2[23:16])
Usage
Use SXTB16 when you need to keep intermediate values to higher precision while working on arrays of signed byte values. See UXTAB16 on page A4-276 for an example of a similar usage.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-225
ARM Instructions
A4.1.115 SXTH
31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 76543 0
cond
011010111111
Rd
rotate SBZ 0 1 1 1
Rm
SXTH extracts a 16-bit value from a register and sign extends it to 32 bits. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.
Syntax
SXTH{<cond>} <Rd>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-226
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then operand2 = Rm Rotate_Right(8 * rotate) Rd[31:0] = SignExtend(operand2[15:0])
Usage
Use SXTH to sign-extend a halfword to a word, for example in instruction sequences acting on signed short values in C/C++.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-227
ARM Instructions
A4.1.116 TEQ
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I10011
Rn
SBZ
shifter_operand
TEQ (Test Equivalence) compares a register value with another arithmetic value. The condition flags are updated, based on the result of logically exclusive-ORing the two values, so that subsequent instructions can be conditionally executed.
Syntax
TEQ{<cond>} <Rn>, <shifter_operand>
where:
<cond> <Rn>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the register that contains the first operand. Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option sets the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not TEQ. Instead, see Multiply instruction extension space on page A3-35 to determine which instruction it is.
<shifter_operand>
Architecture version
All.
Exceptions
None.
Operation
if ConditionPassed(cond) then alu_out = Rn EOR shifter_operand N Flag = alu_out[31] Z Flag = if alu_out == 0 then 1 else 0 C Flag = shifter_carry_out V Flag = unaffected
A4-228
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
Use TEQ to test if two values are equal, without affecting the V flag (as CMP does). The C flag is also unaffected in many cases. TEQ is also useful for testing whether two values have the same sign. After the comparison, the N flag is the logical Exclusive OR of the sign bits of the two operands.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-229
ARM Instructions
A4.1.117 TST
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
00I10001
Rn
SBZ
shifter_operand
TST (Test) compares a register value with another arithmetic value. The condition flags are updated, based on the result of logically ANDing the two values, so that subsequent instructions can be conditionally executed.
Syntax
TST{<cond>} <Rn>, <shifter_operand>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the register that contains the first operand.
<Rn>
<shifter_operand>
Specifies the second operand. The options for this operand are described in Addressing Mode 1 - Data-processing operands on page A5-2, including how each option causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction. If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not TST. Instead, see Multiply instruction extension space on page A3-35 to determine which instruction it is.
Architecture version
All.
Exceptions
None.
Operation
if ConditionPassed(cond) then alu_out = Rn AND shifter_operand N Flag = alu_out[31] Z Flag = if alu_out == 0 then 1 else 0 C Flag = shifter_carry_out V Flag = unaffected
A4-230
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
Use TST to determine whether a particular subset of register bits includes at least one set bit. A very common use for TST is to test whether a single bit is set or clear.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-231
ARM Instructions
A4.1.118 UADD16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100101
Rn
Rd
SBO
0001
Rm
UADD16 (Unsigned Add) performs two 16-bit unsigned integer additions. It sets the GE bits in the CPSR as carry flags for the additions.
Syntax
UADD16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15:0] = Rn[15:0] + Rm[15:0] GE[1:0] = if CarryFrom16(Rn[15:0] + Rm[15:0]) == 1 then 0b11 else 0 Rd[31:16] = Rn[31:16] + Rm[31:16] GE[3:2] = if CarryFrom16(Rn[31:16] + Rm[31:16]) == 1 then 0b11 else 0
Usage
UADD16 produces the same result value as SADD16. However, the GE flag values are based on unsigned
arithmetic instead of signed arithmetic.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-232
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.119 UADD8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100101
Rn
Rd
SBO
1001
Rm
UADD8 performs four 8-bit unsigned integer additions. It sets the GE bits in the CPSR as carry flags for the
additions.
Syntax
UADD8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[7:0] = Rn[7:0] + Rm[7:0] GE[0] = CarryFrom8(Rn[7:0] + Rm[7:0]) Rd[15:8] = Rn[15:8] + Rm[15:8] GE[1] = CarryFrom8(Rn[15:8] + Rm[15:8]) Rd[23:16] = Rn[23:16] + Rm[23:16] GE[2] = CarryFrom8(Rn[23:16] + Rm[23:16]) Rd[31:24] = Rn[31:24] + Rm[31:24] GE[3] = CarryFrom8(Rn[31:24] + Rm[31:24])
Usage
UADD8 produces the same result value as SADD8. However, the GE flag values are based on unsigned arithmetic instead of signed arithmetic.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-233
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-234
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.120 UADDSUBX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100101
Rn
Rd
SBO
0011
Rm
UADDSUBX (Unsigned Add and Subtract with Exchange) performs one 16-bit unsigned integer addition and one 16-bit unsigned integer subtraction. It exchanges the two halfwords of the second operand before it performs the arithmetic. It sets the GE bits in the CPSR according to the results of the addition and subtraction.
Syntax
UADDSUBX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[31:16] + Rm[15:0] /* unsigned addition */ Rd[31:16] = sum[15:0] GE[3:2] = if CarryFrom16(Rn[31:16] + Rm[15:0]) then 0b11 else 0 diff = Rn[15:0] - Rm[31:16] /* unsigned subtraction */ Rd[15:0] = diff[15:0] GE[1:0] = if BorrowFrom(Rn[15:0] - Rm[31:16]) then 0b11 else 0
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-235
ARM Instructions
Usage
UADDSUBX produces the same result value as SADDSUBX. However, the GE flag values are based on unsigned arithmetic instead of signed arithmetic.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-236
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.121 UHADD16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100111
Rn
Rd
SBO
0001
Rm
UHADD16 (Unsigned Halving Add) performs two 16-bit unsigned integer additions, and halves the results. It has no effect on the GE flags.
Syntax
UHADD16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[15:0] + Rm[15:0] /* Unsigned addition */ Rd[15:0] = sum[16:1] sum = Rn[31:16] + Rm[31:16] /* Unsigned addition */ Rd[31:16] = sum[16:1]
Usage
Use UHADD16 for similar purposes to UADD16 (see UADD16 on page A4-232). UHADD16 averages the operands.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-237
ARM Instructions
A4.1.122 UHADD8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100111
Rn
Rd
SBO
1001
Rm
UHADD16 performs four 8-bit unsigned integer additions, and halves the results. It has no effect on the GE
flags.
Syntax
UHADD8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[7:0] + Rm[7:0] Rd[7:0] = sum[8:1] sum = Rn[15:8] + Rm[15:8] Rd[15:8] = sum[8:1] sum = Rn[23:16] + Rm[23:16] Rd[23:16] = sum[8:1] sum = Rn[31:24] + Rm[31:24] Rd[31:24] = sum[8:1] /* Unsigned addition */ /* Unsigned addition */ /* Unsigned addition */ /* Unsigned addition */
Usage
Use UHADD8 for similar purposes to UADD8 (see UADD8 on page A4-233). UHADD8 averages the operands.
A4-238
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-239
ARM Instructions
A4.1.123 UHADDSUBX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100111
Rn
Rd
SBO
0011
Rm
UHADDSUBX (Unsigned Halving Add and Subtract with Exchange) performs one 16-bit unsigned integer
addition and one 16-bit unsigned integer subtraction, and halves the results. It exchanges the two halfwords of the second operand before it performs the arithmetic. It has no effect on the GE flags.
Syntax
UHADDSUBX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then sum = Rn[31:16] + Rm[15:0] Rd[31:16] = sum[16:1] diff = Rn[15:0] - Rm[31:16] Rd[15:0] = diff[16:1] /* Unsigned addition */ /* Unsigned subtraction */
Usage
Use UHADDSUBX for similar purposes to UADDSUBX (see UADDSUBX on page A4-235). UHADDSUBX halves the results.
A4-240
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-241
ARM Instructions
A4.1.124 UHSUB16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100111
Rn
Rd
SBO
0111
Rm
UHSUB16 (Unsigned Halving Subtract) performs two 16-bit unsigned integer subtractions, and halves the
results. It has no effect on the GE flags.
Syntax
UHSUB16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[15:0] - Rm[15:0] Rd[15:0] = diff[16:1] diff = Rn[31:16] - Rm[31:16] Rd[31:16] = diff[16:1] /* Unsigned subtraction */ /* Unsigned subtraction */
Usage
Use UHSUB16 for similar purposes to USUB16 (see USUB16 on page A4-269). UHSUB16 gives half the difference instead of the full difference.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-242
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.125 UHSUB8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100111
Rn
Rd
SBO
1111
Rm
UHSUB8 performs four 8-bit unsigned integer subtractions, and halves the results. It has no effect on the GE
flags.
Syntax
UHSUB8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[7:0] - Rm[7:0] Rd[7:0] = diff[8:1] diff = Rn[15:8] - Rm[15:8] Rd[15:8] = diff[8:1] diff = Rn[23:16] - Rm[23:16] Rd[23:16] = diff[8:1] diff = Rn[31:24] - Rm[31:24] Rd[31:24] = diff[8:1] /* Unsigned subtraction */ /* Unsigned subtraction */ /* Unsigned subtraction */ /* Unsigned subtraction */
Usage
Use UHSUB8 for similar purposes to USUB8 (see USUB8 on page A4-270). UHSUB8 gives half the difference instead of the full difference.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-243
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-244
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.126 UHSUBADDX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100111
Rn
Rd
SBO
0101
Rm
UHSUBADDX (Unsigned Halving Subtract and Add with Exchange) performs one 16-bit unsigned integer
subtraction and one 16-bit unsigned integer addition, and halves the results. It exchanges the two halfwords of the second operand before it performs the arithmetic. It has no effect on the GE flags.
Syntax
UHSUBADDX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[31:16] - Rm[15:0] Rd[31:16] = diff[16:1] sum = Rn[15:0] + Rm[31:16] Rd[15:0] = sum[16:1] /* Unsigned subtraction */ /* Unsigned addition */
Usage
Use UHSUBADDX for similar purposes to USUBADDX (see USUBADDX on page A4-272). UHSUBADDX gives half the difference and the average instead of the full difference and sum.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-245
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-246
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.127 UMAAL
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
00000100
RdHi
RdLo
Rs
1001
Rm
UMAAL (Unsigned Multiply Accumulate Accumulate Long) multiplies the unsigned value of register <Rm> with the unsigned value of register <Rs> to produce a 64-bit product. Both the unsigned 32-bit value held in <RdHi> and the unsigned 32-bit value held in <RdLo> are added to this product, and the sum is written back to <RdHi> and <RdLo> as a 64-bit value. The flags are not updated.
Syntax
UMAAL{<cond>} <RdLo>, <RdHi>, <Rm>, <Rs>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Supplies one of the 32-bit values to be added to the product of <Rm> and <Rs>, and is the destination register for the lower 32 bits of the result. Supplies the other 32-bit value to be added to the product of <Rm> and <Rs>, and is the destination register for the upper 32 bits of the result. Holds the unsigned value to be multiplied with the value of <Rs>. Holds the unsigned value to be multiplied with the value of <Rm>.
<RdLo>
<RdHi>
<Rm> <Rs>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then result = Rm * Rs + RdLo + RdHi RdLo = result[31:0] RdHi = result[63:32] /* Unsigned multiplication and additions */
Usage
Adding two 32-bit values to a 32-bit unsigned multiply is a useful function in cryptographic applications.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-247
ARM Instructions
Notes
Use of R15 Specifying R15 for register <RdHi>, <RdLo>, <Rm>, or <Rs> has UNPREDICTABLE results.
Operand restriction If <RdLo> and <RdHi> are the same register, the results are UNPREDICTABLE. Early termination If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
A4-248
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.128 UMLAL
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
0000101S
RdHi
RdLo
Rs
1001
Rm
UMLAL (Unsigned Multiply Accumulate Long) multiplies the unsigned value of register <Rm> with the unsigned value of register <Rs> to produce a 64-bit product. This product is added to the 64-bit value held in <RdHi> and <RdLo>, and the sum is written back to <RdHi> and <RdLo>. The condition code flags are optionally updated, based on the result.
Syntax
UMLAL{<cond>}{S} <RdLo>, <RdHi>, <Rm>, <Rs>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction updates the CPSR by setting the N and Z flags according to the result of the multiply-accumulate. If S is omitted, the S bit of the instruction is set to 0 and the entire CPSR is unaffected by the instruction. Supplies the lower 32 bits of the value to be added to the product of <Rm> and <Rs>, and is the destination register for the lower 32 bits of the result. Supplies the upper 32 bits of the value to be added to the product of <Rm> and <Rs>, and is the destination register for the upper 32 bits of the result. Holds the signed value to be multiplied with the value of <Rs>. Holds the signed value to be multiplied with the value of <Rm>.
S
<RdLo>
<RdHi>
<Rm> <Rs>
Architecture version
All.
Exceptions
None.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-249
ARM Instructions
Operation
if ConditionPassed(cond) then RdLo = (Rm * Rs)[31:0] + RdLo /* Unsigned multiplication */ RdHi = (Rm * Rs)[63:32] + RdHi + CarryFrom((Rm * Rs)[31:0] + RdLo) if S == 1 then N Flag = RdHi[31] Z Flag = if (RdHi == 0) and (RdLo == 0) then 1 else 0 C Flag = unaffected /* See "C and V flags" note */ V Flag = unaffected /* See "C and V flags" note */
Usage
UMLAL multiplies unsigned variables to produce a 64-bit result, which is added to the 64-bit value in the two
destination general-purpose registers. The result is written back to the two destination general-purpose registers.
Notes
Use of R15 Specifying R15 for register <RdHi>, <RdLo>, <Rm>, or <Rs> has UNPREDICTABLE results.
Operand restriction <RdHi> and <RdLo> must be distinct registers, or the results are UNPREDICTABLE. Specifying the same register for either <RdHi> and <Rm>, or <RdLo> and <Rm>, was previously described as producing UNPREDICTABLE results. There is no restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 implementations do not require this restriction either, because high performance multipliers read all their operands prior to writing back any results. Early termination If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
UMLALS is defined to leave the C and V flags unchanged in ARMv5 and above. In
UNPREDICTABLE
C and V flags
earlier versions of the architecture, the values of the C and V flags were after a UMLALS instruction.
A4-250
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.129 UMULL
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
0000100S
RdHi
RdLo
Rs
1001
Rm
UMULL (Unsigned Multiply Long) multiplies the unsigned value of register <Rm> with the unsigned value of register <Rs> to produce a 64-bit result. The upper 32 bits of the result are stored in <RdHi>. The lower 32 bits are stored in <RdLo>. The condition code flags are optionally updated, based on the 64-bit result.
Syntax
UMULL{<cond>}{S} <RdLo>, <RdHi>, <Rm>, <Rs>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction updates the CPSR by setting the N and Z flags according to the result of the multiplication. If S is omitted, the S bit of the instruction is set to 0 and the entire CPSR is unaffected by the instruction. Stores the lower 32 bits of the result. Stores the upper 32 bits of the result. Holds the signed value to be multiplied with the value of <Rs>. Holds the signed value to be multiplied with the value of <Rm>.
S
<RdLo> <RdHi> <Rm> <Rs>
Architecture version
All.
Exceptions
None.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-251
ARM Instructions
Operation
if ConditionPassed(cond) then RdHi = (Rm * Rs)[63:32] /* Unsigned multiplication */ RdLo = (Rm * Rs)[31:0] if S == 1 then N Flag = RdHi[31] Z Flag = if (RdHi == 0) and (RdLo == 0) then 1 else 0 C Flag = unaffected /* See "C and V flags" note */ V Flag = unaffected /* See "C and V flags" note */
Usage
UMULL multiplies unsigned variables to produce a 64-bit result in two general-purpose registers.
Notes
Use of R15 Specifying R15 for register <RdHi>, <RdLo>, <Rm>, or <Rs> has UNPREDICTABLE results.
Operand restriction <RdHi> and <RdLo> must be distinct registers, or the results are UNPREDICTABLE. Specifying the same register for either <RdHi> and <Rm>, or <RdLo> and <Rm>, was previously described as producing UNPREDICTABLE results. There is no restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 implementations do not require this restriction either, because high performance multipliers read all their operands prior to writing back any results. Early termination If the multiplier implementation supports early termination, it must be implemented on the value of the <Rs> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
UMULLS is defined to leave the C and V flags unchanged in ARMv5 and above. In
UNPREDICTABLE
C and V flags
earlier versions of the architecture, the values of the C and V flags were after a UMULLS instruction.
A4-252
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.130 UQADD16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100110
Rn
Rd
SBO
0001
Rm
UQADD16 (Unsigned Saturating Add) performs two 16-bit integer additions. It saturates the results to the
16-bit unsigned integer range 0 x 216 1. It has no effect on the GE flags.
Syntax
UQADD16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15:0] = UnsignedSat(Rn[15:0] + Rm[15:0], 16) Rd[31:16] = UnsignedSat(Rn[31:16] + Rm[31:16], 16)
Usage
Use UQADD16 in similar ways to UADD16, but for unsigned saturated arithmetic. UQADD16 does not set the GE bits for use with SEL. See UADD16 on page A4-232 for more details.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-253
ARM Instructions
A4.1.131 UQADD8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100110
Rn
Rd
SBO
1001
Rm
UQADD8 performs four 8-bit integer additions. It saturates the results to the 8-bit unsigned integer range 0 x 28 1. It has no effect on the GE flags.
Syntax
UQADD8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[7:0] = UnsignedSat(Rn[7:0] Rd[15:8] = UnsignedSat(Rn[15:8] Rd[23:16] = UnsignedSat(Rn[23:16] Rd[31:24] = UnsignedSat(Rn[31:24] + + + + Rm[7:0], Rm[15:8], Rm[23:16], Rm[31:24], 8) 8) 8) 8)
Usage
Use UQADD8 in similar ways to UADD8, but for unsigned saturated arithmetic. UQADD8 does not set the GE bits for use with SEL. See UADD8 on page A4-233 for more details.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-254
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.132 UQADDSUBX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100110
Rn
Rd
SBO
0011
Rm
UQADDSUBX (Unsigned Saturating Add and Subtract with Exchange) performs one 16-bit integer addition and
one 16-bit subtraction. It saturates the results to the 16-bit unsigned integer range 0 x 216 1. It exchanges the two halfwords of the second operand before it performs the arithmetic. It has no effect on the GE flags.
Syntax
UQADDSUBX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15:0] = UnsignedSat(Rn[15:0] - Rm[31:16], 16) Rd[31:16] = UnsignedSat(Rn[31:16] + Rm[15:0], 16)
Usage
Use UQADDSUBX in similar ways to UADDSUBX, but for unsigned saturated arithmetic. UQADDSUBX does not set the GE bits for use with SEL. See UADDSUBX on page A4-235 for more details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-255
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-256
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.133 UQSUB16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100110
Rn
Rd
SBO
0111
Rm
UQSUB16 (Unsigned Saturating Subtract) performs two 16-bit subtractions. It saturates the results to the 16-bit
unsigned integer range 0 x 216 1. It has no effect on the GE flags.
Syntax
UQSUB16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15:0] = UnsignedSat(Rn[15:0] - Rm[15:0], 16) Rd[31:16] = UnsignedSat(Rn[31:16] - Rm[31:16], 16)
Usage
Use UQSUB16 in similar ways to USUB16, but for unsigned saturated arithmetic. UQSUB16 does not set the GE bits for use with SEL. See SSUB16 on page A4-180 for more details.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-257
ARM Instructions
A4.1.134 UQSUB8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100110
Rn
Rd
SBO
1111
Rm
UQSUB8 performs four 8-bit subtractions. It saturates the results to the 8-bit unsigned integer range
0 x 28 1. It has no effect on the GE flags.
Syntax
UQSUB8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[7:0] = UnsignedSat(Rn[7:0] Rd[15:8] = UnsignedSat(Rn[15:8] Rd[23:16] = UnsignedSat(Rn[23:16] Rd[31:24] = UnsignedSat(Rn[31:24] Rm[7:0], Rm[15:8], Rm[23:16], Rm[31:24], 8) 8) 8) 8)
Usage
Use UQSUB8 in similar ways to USUB8, but for unsigned saturated arithmetic. UQSUB8 does not set the GE bits for use with SEL. See SSUB8 on page A4-182 for more details.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-258
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.135 UQSUBADDX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100110
Rn
Rd
SBO
0101
Rm
UQSUBADDX (Unsigned Saturating Subtract and Add with Exchange) performs one 16-bit integer subtraction and one 16-bit integer addition. It saturates the results to the 16-bit unsigned integer range 0 x 216 1. It exchanges the two halfwords of the second operand before it performs the arithmetic. It has no effect on the GE flags.
Syntax
UQSUBADDX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[31:16] = UnsignedSat(Rn[31:16] - Rm[15:0], 16) Rd[15:0] = UnsignedSat(Rn[15:0] + Rm[31:16], 16)
Usage
You can use UQSUBADDX in similar ways to USUBADDX, but for unsigned saturated arithmetic. UQSUBADDX does not set the GE bits for use with SEL. See UADDSUBX on page A4-235 for more details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-259
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
A4-260
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.136 USAD8
31 28 27 26 25 24 23 22 21 20 19 16 15 14 13 12 11 87654 3 0
cond
01111000
Rd
1111
Rs
0001
Rm
USAD8 (Unsigned Sum of Absolute Differences) performs four unsigned 8-bit subtractions, and adds the
absolute values of the differences together.
Syntax
USAD8{<cond>} <Rd>, <Rm>, <Rs>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rm> <Rs>
Architecture version
ARMv6 and above.
Exceptions
None.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-261
ARM Instructions
Operation
if ConditionPassed(cond) then if Rm[7:0] < Rs[7:0] then diff1 = Rs[7:0] - Rm[7:0] else diff1 = Rm[7:0] - Rs[7:0] if Rm[15:8] < Rs[15:8] then diff2 = Rs[15:8] - Rm[15:8] else diff2 = Rm[15:8] - Rs[15:8] /* Unsigned comparison */
/* Unsigned comparison */
if Rm[23:16] < Rs[23:16] then /* Unsigned comparison */ diff3 = Rs[23:16] - Rm[23:16] else diff3 = Rm[23:16] - Rs[23:16] if Rm[31:24] < Rs[31:24] then /* Unsigned comparison */ diff4 = Rs[31:24] - Rm[31:24] else diff4 = Rm[31:24] - Rs[31:24] Rd = ZeroExtend(diff1) + ZeroExtend(diff2) + ZeroExtend(diff3) + ZeroExtend(diff4]
Usage
You can use USAD8 to process the first four bytes in a video motion estimation calculation.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results.
A4-262
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.137 USADA8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01111000
Rd
Rn
Rs
0001
Rm
USADA8 (Unsigned Sum of Absolute Differences and Accumulate) performs four unsigned 8-bit subtractions,
and adds the absolute values of the differences to a 32-bit accumulate operand.
Syntax
USADA8{<cond>} <Rd>, <Rm>, <Rs>, <Rn>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first main operand. Specifies the register that contains the second main operand. Specifies the register that contains the accumulate operand.
<Rd> <Rm> <Rs> <Rn>
Architecture version
ARMv6 and above.
Exceptions
None.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-263
ARM Instructions
Operation
if ConditionPassed(cond) then if Rm[7:0] < Rs[7:0] then diff1 = Rs[7:0] - Rm[7:0] else diff1 = Rm[7:0] - Rs[7:0] if Rm[15:8] < Rs[15:8] then diff2 = Rs[15:8] - Rm[15:8] else diff2 = Rm[15:8] - Rs[15:8] /* Unsigned comparison */
/* Unsigned comparison */
if Rm[23:16] < Rs[23:16] then /* Unsigned comparison */ diff3 = Rs[23:16] - Rm[23:16] else diff3 = Rm[23:16] - Rs[23:16] if Rm[31:24] < Rs[31:24] then /* Unsigned comparison */ diff4 = Rs[31:24] - Rm[31:24] else diff4 = Rm[31:24] - Rs[31:24] Rd = Rn + ZeroExtend(diff1) + ZeroExtend(diff2) + ZeroExtend(diff3) + ZeroExtend(diff4]
Usage
You can use USADA8 in video motion estimation calculations.
Notes
Use of R15 Encoding Specifying R15 for register <Rd>, <Rm>, or <Rs> has UNPREDICTABLE results. If the <Rn> field of the instruction contains 0b1111, the instruction is a USAD8 instruction instead, see USAD8 on page A4-261.
A4-264
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.138 USAT
31 28 27 26 25 24 23 22 21 20 16 15 12 11 76543 0
cond
0110111
sat_imm
Rd
shift_imm
sh 0 1
Rm
USAT (Unsigned Saturate) saturates a signed value to an unsigned range. You can choose the bit position at which saturation occurs.
You can apply a shift to the value before the saturation occurs. The Q flag is set if the operation saturates.
Syntax
USAT{<cond>} <Rd>, #<immed>, <Rm>{, <shift>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the bit position for saturation. This lies in the range 0 to 31. It is encoded in the sat_imm field of the instruction. Specifies the register that contains the signed value to be saturated. Specifies the optional shift. If present, it must be one of:
LSL #N. N must be in the range 0 to 31. This is encoded as sh == 0 and shift_imm == N. ASR #N. N must be in the range 1 to 32. This is encoded as sh == 1 and either shift_imm == 0 for N == 32, or shift_imm == N otherwise.
<Rd> <immed>
<Rm> <shift>
If <shift> is omitted, LSL #0 is used.
Return
The value returned in Rd is: 0 X 2n 1 if X is < 0 if 0 <= X < 2n if X > 2n 1
where n is <immed>, and X is the shifted value from Rm.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-265
ARM Instructions
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then if shift == 1 then if shift_imm == 0 then operand = (Rm Artihmetic_Shift_Right 32)[31:0] else operand = (Rm Artihmetic_Shift_Right shift_imm)[31:0] else operand = (Rm Logical_Shift_Left shift_imm)[31:0] Rd = UnsignedSat(operand, sat_imm) /* operand treated as signed */ if UnsignedDoesSat(operand, sat_imm) then Q Flag = 1
Usage
You can use USAT in various DSP algorithms, such as calculating a pixel color component, that require scaling and saturation of signed data to an unsigned destination.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
A4-266
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.139 USAT16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01101110
sat_imm
Rd
SBO
0011
Rm
USAT16 saturates two signed 16-bit values to an unsigned range. You can choose the bit position at which
saturation occurs. The Q flag is set if either halfword operation saturates.
Syntax
USAT16{<cond>} <Rd>, #<immed>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the bit position for saturation. This lies in the range 0 to 15. It is encoded in the sat_imm field of the instruction. Specifies the register that contains the signed value to be saturated.
<Rd> <immed>
<Rm>
Return
The value returned in each half of Rd is: 0 X 2n 1 if X is < 0 if 0 <= X < 2n if X > 2n 1
where n is <immed>, and X is the value from the corresponding half of Rm.
Architecture version
ARMv6 and above.
Exceptions
None.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-267
ARM Instructions
Operation
if ConditionPassed(cond) then Rd[15:0] = UnsignedSat(Rm[15:0], sat_imm) // Rm[15:0] treated as signed Rd[31:16] = UnsignedSat(Rm[31:16], sat_imm) // Rm[31:16] treated as signed if UnsignedDoesSat(Rm[15:0], sat_imm) OR UnsignedDoesSat(Rm[31:16], sat_imm) then Q Flag = 1
Usage
You can use USAT16 in various DSP algorithms, such as calculating a pixel color component, that require saturation of signed data to an unsigned destination.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
A4-268
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
A4.1.140 USUB16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
01100101
Rn
Rd
SBO
0111
Rm
USUB16 (Unsigned Subtract) performs two 16-bit unsigned integer subtractions. It sets the GE bits in the CPSR as borrow bits for the subtractions.
Syntax
USUB16{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[15:0] = Rn[15:0] - Rm[15:0] GE[1:0] = if BorrowFrom(Rn[15:0] - Rm[15:0]) then 0 else 0b11 Rd[31:16] = Rn[31:16] - Rm[31:16] GE[3:2] = if BorrowFrom(Rn[31:16] - Rm[31:16]) then 0 else 0b11
Usage
USUB16 produces the same result as SSUB16 (see SSUB16 on page A4-180), but produces GE bit values based
on unsigned arithmetic instead of signed arithmetic.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-269
ARM Instructions
A4.1.141 USUB8
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100101
Rn
Rd
SBO
1111
Rm
USUB8 performs four 8-bit unsigned integer subtractions. It sets the GE bits in the CPSR as borrow bits for
the subtractions.
Syntax
USUB8{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then Rd[7:0] = Rn[7:0] - Rm[7:0] GE[0] = NOT BorrowFrom(Rn[7:0] - Rm[7:0]) Rd[15:8] = Rn[15:8] - Rm[15:8] GE[1] = NOT BorrowFrom(Rn[15:8] - Rm[15:8]) Rd[23:16] = Rn[23:16] - Rm[23:16] GE[2] = NOT BorrowFrom(Rn[23:16] - Rm[23:16]) Rd[31:24] = Rn[31:24] - Rm[31:24] GE[3] = NOT BorrowFrom(Rn[31:24] - Rm[31:24])
Usage
USUB8 produces the same result as SSUB8 (see SSUB8 on page A4-182), but produces GE bit values based on unsigned arithmetic instead of signed arithmetic.
A4-270
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-271
ARM Instructions
A4.1.142 USUBADDX
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
01100101
Rn
Rd
SBO
0101
Rm
USUBADDX (Unsigned Subtract and Add with Exchange) performs one 16-bit unsigned integer subtraction and
one 16-bit unsigned integer addition. It exchanges the two halfwords of the second operand before it performs the arithmetic. It sets the GE bits in the CPSR as borrow and carry bits.
Syntax
USUBADDX{<cond>} <Rd>, <Rn>, <Rm>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand.
<Rd> <Rn> <Rm>
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if ConditionPassed(cond) then diff = Rn[31:16] - Rm[15:0] Rd[31:16] = diff[15:0] GE[3:2] = if BorrowFrom(Rn[31:16] sum = Rn[15:0] + Rm[31:16] Rd[15:0] = sum[15:0] GE[1:0] = if CarryFrom16(Rn[15:0] /* unsigned subtraction */ - Rm[15:0]) then 0b11 else 0 /* unsigned addition */ + Rm[31:16]) then 0b11 else 0
A4-272
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Usage
USUBADDX produces the same result as SSUBADDX (see SSUBADDX on page A4-184), but produces GE bit
values based on unsigned arithmetic instead of signed arithmetic.
Notes
Use of R15 Specifying R15 for register <Rd>, <Rm>, or <Rn> has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-273
ARM Instructions
A4.1.143 UXTAB
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 76543 0
cond
01101110
Rn
Rd
rotate SBZ 0 1 1 1
Rm
UXTAB extracts an 8-bit value from a register, zero extends it to 32 bits, and adds the result to the value in
another register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.
Syntax
UXTAB{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rn> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-274
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then operand2 = (Rm Rotate_Right(8 * rotate)) AND 0x000000ff Rd = Rn + operand2
Usage
You can use UXTAB to eliminate a separate sign-extension instruction in many instruction sequences that act on unsigned char values in C/C++.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
Note
Your assembler must fault the use of R15 for register <Rn>. Encoding If the <Rn> field of the instruction contains 0b1111, the instruction is an UXTB instruction instead, see UXTB on page A4-280.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-275
ARM Instructions
A4.1.144 UXTAB16
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 76543 0
cond
01101100
Rn
Rd
rotate SBZ 0 1 1 1
Rm
UXTAB16 extracts two 8-bit values from a register, zero extends them to 16 bits each, and adds the results to
the two values from another register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.
Syntax
UXTAB16{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rn> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-276
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then operand2 = (Rm Rotate_Right(8 * rotate)) AND 0x00ff00ff Rd[15:0] = Rn[15:0] + operand2[15:0] Rd[31:16] = Rn[31:16] + operand2[23:16]
Usage
Use UXTAB16 to keep intermediate values to higher precision while working on arrays of unsigned byte values.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
Note
Your assembler must fault the use of R15 for register <Rn>. Encoding If the <Rn> field of the instruction contains 0b1111, the instruction is a UXTB16 instruction instead, see UXTB16 on page A4-282.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-277
ARM Instructions
A4.1.145 UXTAH
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 76543 0
cond
01101111
Rn
Rd
rotate SBZ 0 1 1 1
Rm
UXTAH extracts a 16-bit value from a register, zero extends it to 32 bits, and adds the result to a value in
another register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.
Syntax
UXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the first operand. Specifies the register that contains the second operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rn> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-278
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then operand2 = (Rm Rotate_Right(8 * rotate)) AND 0x0000ffff Rd = Rn + operand2
Usage
You can use UXTAH to eliminate a separate zero-extension instruction in many instruction sequences that act on unsigned short values in C/C++.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results.
Note
Your assembler must fault the use of R15 for register <Rn>. Encoding If the <Rn> field of the instruction contains 0b1111, the instruction is a UXTH instruction instead, see UXTH on page A4-284.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-279
ARM Instructions
A4.1.146 UXTB
31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 76543 0
cond
011011101111
Rd
rotate SBZ 0 1 1 1
Rm
UXTB extracts an 8-bit value from a register and zero extends it to 32 bits. You can specify a rotation by 0, 8,
16, or 24 bits before extracting the 8-bit value.
Syntax
UXTB{<cond>} <Rd>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-280
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then Rd[31:0] = (Rm Rotate_Right(8 * rotate)) AND 0x000000ff
Usage
Use UXTB to zero extend a byte to a word, for example in instruction sequences acting on unsigned char values in C/C++.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-281
ARM Instructions
A4.1.147 UXTB16
31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 76543 0
cond
011011001111
Rd
rotate SBZ 0 1 1 1
Rm
UXTB16 extracts two 8-bit values from a register and zero extends them to 16 bits each. You can specify a
rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.
Syntax
UXTB16{<cond>} <Rd>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-282
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then Rd[31:0] = (Rm Rotate_Right(8 * rotate)) AND 0x00ff00ff
Usage
Use UXTB16 to zero extend a byte to a halfword, for example in instruction sequences acting on unsigned char values in C/C++.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-283
ARM Instructions
A4.1.148 UXTH
31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 8 76543 0
cond
011011111111
Rd
rotate SBZ 0 1 1 1
Rm
UXTH extracts a 16-bit value from a register and zero extends it to 32 bits. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.
Syntax
UXTH{<cond>} <Rd>, <Rm>{, <rotation>}
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used. Specifies the destination register. Specifies the register that contains the operand. This can be any one of:
ROR #8. This is encoded as 0b01 in the rotate field. ROR #16. This is encoded as 0b10 in the rotate field. ROR #24. This is encoded as 0b11 in the rotate field.
<Rd> <Rm> <rotation>
Omitted. This is encoded as 0b00 in the rotate field.
Note
If your assembler accepts shifts by #0 and treats them as equivalent to no shift or LSL #0, then it must accept ROR #0 here. It is equivalent to omitting
<rotation>.
Architecture version
ARMv6 and above.
Exceptions
None.
A4-284
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Operation
if ConditionPassed(cond) then Rd[31:0] = (Rm Rotate_Right(8 * rotate)) AND 0x0000ffff
Usage
Use UXTH to zero extend a halfword to a word, for example in instruction sequences acting on unsigned short values in C/C++.
Notes
Use of R15 Specifying R15 for register <Rd> or <Rm> has UNPREDICTABLE results
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-285
ARM Instructions
A4.2
ARM instructions and architecture versions
Table A4-2 shows which ARM instructions are present in each current ARM architecture version. Table A4-2 ARM instructions by architecture version Instruction
ADC ADD AND B BIC BKPT BL BLX (both forms) BX BXJ CDP CDP2 CLZ CMN CMP CPS CPY EOR LDC LDC2 LDM (all forms) LDR
v4 Yes Yes Yes Yes Yes No Yes No No No Yes No No Yes Yes No No Yes Yes No Yes Yes
v4T Yes Yes Yes Yes Yes No Yes No Yes No Yes No No Yes Yes No No Yes Yes No Yes Yes
v5T Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes
v5TE, v5TEJ, v5TExP Yes Yes Yes Yes Yes Yes Yes Yes Yes Only v5TEJ Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes
v6 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
A4-286
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Table A4-2 ARM instructions by architecture version (continued) Instruction
LDRB LDRD LDRBT LDREX LDRH LDRSB LDRSH LDRT MCR MCR2 MCRR MCRR2 MLA MOV MRC MRC2 MRRC MRRC2 MRS MSR MUL MVN ORR PKH (both forms)
v4 Yes No Yes No Yes Yes Yes Yes Yes No No No Yes Yes Yes No No No Yes Yes Yes Yes Yes No
v4T Yes No Yes No Yes Yes Yes Yes Yes No No No Yes Yes Yes No No No Yes Yes Yes Yes Yes No
v5T Yes No Yes No Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes Yes Yes Yes No
v5TE, v5TEJ, v5TExP Yes Only v5TE, v5TEJ Yes No Yes Yes Yes Yes Yes Yes Only v5TE, v5TEJ No Yes Yes Yes Yes Only v5TE, v5TEJ No Yes Yes Yes Yes Yes No
v6 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-287
ARM Instructions
Table A4-2 ARM instructions by architecture version (continued) Instruction
PLD QADD QADD16 QADD8 QADDSUBX QDADD QDSUB QSUB QSUB16 QSUB8 QSUBADDX REV (all forms) RFE RSB RSC SADD (all forms) SBC SEL SETEND SHADD (all forms) SHSUB (all forms) SMLAD SMLAL SMLALD
v4 No No No No No No No No No No No No No Yes Yes No Yes No No No No No Yes No
v4T No No No No No No No No No No No No No Yes Yes No Yes No No No No No Yes No
v5T No No No No No No No No No No No No No Yes Yes No Yes No No No No No Yes No
v5TE, v5TEJ, v5TExP Only v5TE, v5TEJ Yes No No No Yes Yes Yes No No No No No Yes Yes No Yes No No No No No Yes No
v6 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
A4-288
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Instructions
Table A4-2 ARM instructions by architecture version (continued) Instruction
SMLA<x><y> SMLAL<x><y> SMLAW<y> SMLSD SMLSLD SMMLA SMMLS SMMUL SMUAD SMULL SMUL<x><y> SMULW<y> SMUSD SRS SSAT (both forms) SSUB (all forms) STC STC2 STM (both forms) STR STRB STRBT STRD STREX
v4 No No No No No No No No No Yes No No No No No No Yes No Yes Yes Yes Yes No No
v4T No No No No No No No No No Yes No No No No No No Yes No Yes Yes Yes Yes No No
v5T No No No No No No No No No Yes No No No No No No Yes Yes Yes Yes Yes Yes No No
v5TE, v5TEJ, v5TExP Yes Yes Yes No No No No No No Yes Yes Yes No No No No Yes Yes Yes Yes Yes Yes Only v5TE, v5TEJ No
v6 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A4-289
ARM Instructions
Table A4-2 ARM instructions by architecture version (continued) Instruction
STRH STRT SUB SWI SWP SWPB SXT (all forms) TEQ TST UADD (all forms) UHADD (all forms) UMAAL UMLAL UMULL UQADD (all forms) UQSUB (all forms) USAD (both forms) USAT (both forms) USUB (all forms) UXT (all forms)
v4 Yes Yes Yes Yes Yes Yes No Yes Yes No No No Yes Yes No No No No No No
v4T Yes Yes Yes Yes Yes Yes No Yes Yes No No No Yes Yes No No No No No No
v5T Yes Yes Yes Yes Yes Yes No Yes Yes No No No Yes Yes No No No No No No
v5TE, v5TEJ, v5TExP Yes Yes Yes Yes Yes Yes No Yes Yes No No No Yes Yes No No No No No No
v6 Yes Yes Yes Yes Deprecated Deprecated Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
A4-290
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Chapter A5 ARM Addressing Modes
This chapter describes each of the five addressing modes used with ARM instructions. The chapter contains the following sections: Addressing Mode 1 - Data-processing operands on page A5-2 Addressing Mode 2 - Load and Store Word or Unsigned Byte on page A5-18 Addressing Mode 3 - Miscellaneous Loads and Stores on page A5-33 Addressing Mode 4 - Load and Store Multiple on page A5-41 Addressing Mode 5 - Load and Store Coprocessor on page A5-49.
Note
All valid architecture variants (from v4, see Architecture versions and variants on page xiii) support address modes 1 to 5 inclusive.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-1
ARM Addressing Modes
A5.1
Addressing Mode 1 - Data-processing operands
There are 11 formats used to calculate the <shifter_operand> in an ARM data-processing instruction. The general instruction syntax is:
<opcode>{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where <shifter_operand> is one of the following: 1.
#<immediate>
See Data-processing operands - Immediate on page A5-6. 2.
<Rm>
See Data-processing operands - Register on page A5-8. 3.
<Rm>, LSL #<shift_imm>
See Data-processing operands - Logical shift left by immediate on page A5-9. 4.
<Rm>, LSL <Rs>
See Data-processing operands - Logical shift left by register on page A5-10. 5.
<Rm>, LSR #<shift_imm>
See Data-processing operands - Logical shift right by immediate on page A5-11. 6.
<Rm>, LSR <Rs>
See Data-processing operands - Logical shift right by register on page A5-12. 7.
<Rm>, ASR #<shift_imm>
See Data-processing operands - Arithmetic shift right by immediate on page A5-13. 8.
<Rm>, ASR <Rs>
See Data-processing operands - Arithmetic shift right by register on page A5-14. 9.
<Rm>, ROR #<shift_imm>
See Data-processing operands - Rotate right by immediate on page A5-15. 10.
<Rm>, ROR <Rs>
See Data-processing operands - Rotate right by register on page A5-16. 11.
<Rm>, RRX
See Data-processing operands - Rotate right with extend on page A5-17.
A5-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.1.1
Encoding
The following diagrams show the encodings for this addressing mode:
32-bit immediate
31 28 27 26 25 24 21 20 19 16 15 12 11 87 0
cond
001
opcode
S
Rn
Rd
rotate_imm
immed_8
Immediate shifts
31 28 27 26 25 24 21 20 19 16 15 12 11 7654 3 0
cond
000
opcode
S
Rn
Rd
shift_imm
shift 0
Rm
Register shifts
31 28 27 26 25 24 21 20 19 16 15 12 11 87654 3 0
cond
000
opcode
S
Rn
Rd
Rs
0 shift 1
Rm
opcode S bit Rd Rn Bits[11:0] Bit[25]
Specifies the operation of the instruction. Indicates that the instruction updates the condition codes. Specifies the destination register. Specifies the first source operand register. The fields within bits[11:0] are collectively called a shifter operand. This is described in The shifter operand on page A5-4. Is referred to as the I bit, and is used to distinguish between an immediate shifter operand and a register-based shifter operand.
If all three of the following bits have the values shown, the instruction is not a data-processing instruction, but lies in the arithmetic or Load/Store instruction extension space:
bit[25] bit[4] bit[7] == 0 == 1 == 1
See Extending the instruction set on page A3-32 for more information. Addressing mode 3, MCRR{2}, MRRC{2}, STC{2} are examples of instructions that reside in this space.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-3
ARM Addressing Modes
A5.1.2
The shifter operand
As well as producing the shifter operand, the shifter produces a carry-out which some instructions write into the Carry Flag. The default register operand (register Rm specified with no shift) uses the form register shift left by immediate, with the immediate set to zero. The shifter operand takes one of the following three basic formats.
Immediate operand value
An immediate operand value is formed by rotating an 8-bit constant (in a 32-bit word) by an even number of bits (0,2,4,8...26,28,30). Therefore, each instruction contains an 8-bit constant and a 4-bit rotate to be applied to that constant. Some valid constants are:
0xFF,0x104,0xFF0,0xFF00,0xFF000,0xFF000000,0xF000000F
Some invalid constants are:
0x101,0x102,0xFF1,0xFF04,0xFF003,0xFFFFFFFF,0xF000001F
For example:
MOV ADD CMP BIC R0, R3, R7, R9, #0 R3, #1 #1000 R8, #0xFF00 ; ; ; ; Move zero to R0 Add one to the value of register 3 Compare value of R7 with 1000 Clear bits 8-15 of R8 and store in R9
Register operand value
A register operand value is simply the value of a register. The value of the register is used directly as the operand to the data-processing instruction. For example:
MOV ADD CMP R2, R0 R4, R3, R2 R7, R8 ; Move the value of R0 to R2 ; Add R2 to R3, store result in R4 ; Compare the value of R7 and R8
A5-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
Shifted register operand value
A shifted register operand value is the value of a register, shifted (or rotated) before it is used as the data-processing operand. There are five types of shift:
ASR LSL LSR ROR RRX
Arithmetic shift right Logical shift left Logical shift right Rotate right Rotate right with extend.
The number of bits to shift by is specified either as an immediate or as the value of a register. For example:
MOV ADD RSB SUB MOV R2, R9, R9, R10, R12, R0, R5, R5, R9, R4, LSL R5, R5, R8, ROR #2 LSL #3 LSL #3 LSR #4 R3 ; ; ; ; Shift R0 left by 2, write to R2, (R2=R0x4) R9 = R5 + R5 x 8 or R9 = R5 x 9 R9 = R5 x 8 - R5 or R9 = R5 x 7 R10 = R9 - R8 / 16 ; R12 = R4 rotated right by value of R3
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-5
ARM Addressing Modes
A5.1.3
Data-processing operands - Immediate
31 28 27 26 25 24 21 20 19 16 15 12 11 8 7 0
cond
001
opcode
S
Rn
Rd
rotate_imm
immed_8
This data-processing operand provides a constant (defined in the instruction) operand to a data-processing instruction. The <shifter_operand> value is formed by rotating (to the right) an 8-bit immediate value to any even bit position in a 32-bit word. If the rotate immediate is zero, the carry-out from the shifter is the value of the C flag, otherwise, it is set to bit[31] of the value of <shifter_operand>.
Syntax
#<immediate>
where:
<immediate>
Specifies the immediate constant wanted. It is encoded in the instruction as an 8-bit immediate (immed_8) and a 4-bit immediate (rotate_imm), so that <immediate> is equal to the result of rotating immed_8 right by (2 rotate_imm) bits.
Operation
shifter_operand = immed_8 Rotate_Right (rotate_imm * 2) if rotate_imm == 0 then shifter_carry_out = C flag else /* rotate_imm != 0 */ shifter_carry_out = shifter_operand[31]
A5-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
Notes
Legitimate immediates Not all 32-bit immediates are legitimate. Only those that can be formed by rotating an 8-bit immediate right by an even amount are valid 32-bit immediates for this format. Encoding Some values of <immediate> have more than one possible encoding. For example, a value of 0x3F0 could be encoded as: immed_8 == 0x3F, rotate_imm == 0xE or as: immed_8 == 0xFC, rotate_imm == 0xF When more than one encoding is available, an assembler must choose the correct one to use, as follows: If <immediate> lies in the range 0 to 0xFF, an encoding with rotate_imm == 0 is available. The assembler must choose that encoding. (Choosing another encoding would affect how some instructions set the C flag.) Otherwise, it is recommended that the encoding with the smallest value of rotate_imm is chosen. (This choice does not affect instruction functionality.) For more precise control of the encoding, the instruction fields can be specified directly by using the syntax:
#<immed_8>, <rotate_amount>
Use of R15
where <rotate_amount> = 2 * rotate_imm. If R15 is specified as register Rn, the value used is the address of the current instruction plus eight.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-7
ARM Addressing Modes
A5.1.4
Data-processing operands - Register
31 28 27 26 25 24 21 20 19 16 15 12 11 10 9 8 76543 0
cond
000
opcode
S
Rn
Rd
00000000
Rm
This data-processing operand provides the value of a register directly. The carry-out from the shifter is the C flag.
Syntax
<Rm>
where:
<Rm>
Specifies the register whose value is the instruction operand.
Operation
shifter_operand = Rm shifter_carry_out = C Flag
Notes
Encoding This instruction is encoded as a logical shift left by immediate (see Data-processing operands - Logical shift left by immediate on page A5-9) with a shift of zero (shift_imm == 0). If R15 is specified as register Rm or Rn, the value used is the address of the current instruction plus 8.
Use of R15
A5-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.1.5
Data-processing operands - Logical shift left by immediate
31 28 27 26 25 24 21 20 19 16 15 12 11 7654 3 0
cond
000
opcode
S
Rn
Rd
shift_imm
000
Rm
This data-processing operand is used to provide either the value of a register directly (lone register operand, as described in Data-processing operands - Register on page A5-8), or the value of a register shifted left (multiplied by a constant power of two). This instruction operand is the value of register Rm, logically shifted left by an immediate value in the range 0 to 31. Zeros are inserted into the vacated bit positions. The carry-out from the shifter is the last bit shifted out, or the C flag if no shift is specified.
Syntax
<Rm>, LSL #<shift_imm>
where:
<Rm> LSL <shift_imm>
Specifies the register whose value is to be shifted. Indicates a logical shift left. Specifies the shift. This is a value between 0 and 31.
Operation
if shift_imm == 0 then /* Register Operand */ shifter_operand = Rm shifter_carry_out = C Flag else /* shift_imm > 0 */ shifter_operand = Rm Logical_Shift_Left shift_imm shifter_carry_out = Rm[32 - shift_imm]
Notes
Default shift If the value of <shift_imm> == 0, the operand can be written as just <Rm> (see Data-processing operands - Register on page A5-8). Use of R15 If R15 is specified as register Rm or Rn, the value used is the address of the current instruction plus 8.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-9
ARM Addressing Modes
A5.1.6
Data-processing operands - Logical shift left by register
31 28 27 26 25 24 21 20 19 16 15 12 11 8 76543 0
cond
000
opcode
S
Rn
Rd
Rs
0001
Rm
This data-processing operand is used to provide the value of a register multiplied by a variable power of two. This instruction operand is the value of register Rm, logically shifted left by the value in the least significant byte of register Rs. Zeros are inserted into the vacated bit positions. The carry-out from the shifter is the last bit shifted out, which is zero if the shift amount is more than 32, or the C flag if the shift amount is zero.
Syntax
<Rm>, LSL <Rs>
where:
<Rm> LSL <Rs>
Specifies the register whose value is to be shifted. Indicates a logical shift left. Is the register containing the value of the shift.
Operation
if Rs[7:0] == 0 then shifter_operand = Rm shifter_carry_out = C Flag else if Rs[7:0] < 32 then shifter_operand = Rm Logical_Shift_Left Rs[7:0] shifter_carry_out = Rm[32 - Rs[7:0]] else if Rs[7:0] == 32 then shifter_operand = 0 shifter_carry_out = Rm[0] else /* Rs[7:0] > 32 */ shifter_operand = 0 shifter_carry_out = 0
Notes
Use of R15 Specifying R15 as register Rd, register Rm, register Rn, or register Rs has UNPREDICTABLE results.
A5-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.1.7
Data-processing operands - Logical shift right by immediate
31 28 27 26 25 24 21 20 19 16 15 12 11 7654 3 0
cond
000
opcode
S
Rn
Rd
shift_imm
010
Rm
This data-processing operand is used to provide the unsigned value of a register shifted right (divided by a constant power of two). This instruction operand is the value of register Rm, logically shifted right by an immediate value in the range 1 to 32. Zeros are inserted into the vacated bit positions. The carry-out from the shifter is the last bit shifted out.
Syntax
<Rm>, LSR #<shift_imm>
where:
<Rm> LSR <shift_imm>
Specifies the register whose value is to be shifted. Indicates a logical shift right. Specifies the shift. This is an immediate value between 1 and 32. (A shift by 32 is encoded by shift_imm == 0.)
Operation
if shift_imm == 0 then shifter_operand = 0 shifter_carry_out = Rm[31] else /* shift_imm > 0 */ shifter_operand = Rm Logical_Shift_Right shift_imm shifter_carry_out = Rm[shift_imm - 1]
Notes
Use of R15 If R15 is specified as register Rm or Rn, the value used is the address of the current instruction plus 8.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-11
ARM Addressing Modes
A5.1.8
Data-processing operands - Logical shift right by register
31 28 27 26 25 24 21 20 19 16 15 12 11 8 76543 0
cond
000
opcode
S
Rn
Rd
Rs
0011
Rm
This data-processing operand is used to provide the unsigned value of a register shifted right (divided by a variable power of two). It is produced by the value of register Rm, logically shifted right by the value in the least significant byte of register Rs. Zeros are inserted into the vacated bit positions. The carry-out from the shifter is the last bit shifted out, which is zero if the shift amount is more than 32, or the C flag if the shift amount is zero.
Syntax
<Rm>, LSR <Rs>
where:
<Rm> LSR <Rs>
Specifies the register whose value is to be shifted. Indicates a logical shift right. Is the register containing the value of the shift.
Operation
if Rs[7:0] == 0 then shifter_operand = Rm shifter_carry_out = C Flag else if Rs[7:0] < 32 then shifter_operand = Rm Logical_Shift_Right Rs[7:0] shifter_carry_out = Rm[Rs[7:0] - 1] else if Rs[7:0] == 32 then shifter_operand = 0 shifter_carry_out = Rm[31] else /* Rs[7:0] > 32 */ shifter_operand = 0 shifter_carry_out = 0
Notes
Use of R15 Specifying R15 as register Rd, register Rm, register Rn, or register Rs has UNPREDICTABLE results.
A5-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.1.9
Data-processing operands - Arithmetic shift right by immediate
31 28 27 26 25 24 21 20 19 16 15 12 11 7654 3 0
cond
000
opcode
S
Rn
Rd
shift_imm
100
Rm
This data-processing operand is used to provide the signed value of a register arithmetically shifted right (divided by a constant power of two). This instruction operand is the value of register Rm, arithmetically shifted right by an immediate value in the range 1 to 32. The sign bit of Rm (Rm[31]) is inserted into the vacated bit positions. The carry-out from the shifter is the last bit shifted out.
Syntax
<Rm>, ASR #<shift_imm>
where:
<Rm> ASR <shift_imm>
Specifies the register whose value is to be shifted. Indicates an arithmetic shift right. Specifies the shift. This is an immediate value between 1 and 32. (A shift by 32 is encoded by shift_imm == 0.)
Operation
if shift_imm == 0 then if Rm[31] == 0 then shifter_operand = 0 shifter_carry_out = Rm[31] else /* Rm[31] == 1 */ shifter_operand = 0xFFFFFFFF shifter_carry_out = Rm[31] else /* shift_imm > 0 */ shifter_operand = Rm Arithmetic_Shift_Right <shift_imm> shifter_carry_out = Rm[shift_imm - 1]
Notes
Use of R15 If R15 is specified as register Rm or Rn, the value used is the address of the current instruction plus 8.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-13
ARM Addressing Modes
A5.1.10 Data-processing operands - Arithmetic shift right by register
31 28 27 26 25 24 21 20 19 16 15 12 11 8765 43 0
cond
000
opcode
S
Rn
Rd
Rs
0101
Rm
This data-processing operand is used to provide the signed value of a register arithmetically shifted right (divided by a variable power of two). This instruction operand is the value of register Rm arithmetically shifted right by the value in the least significant byte of register Rs. The sign bit of Rm (Rm[31]) is inserted into the vacated bit positions. The carry-out from the shifter is the last bit shifted out, which is the sign bit of Rm if the shift amount is more than 32, or the C flag if the shift amount is zero.
Syntax
<Rm>, ASR <Rs>
where:
<Rm> ASR <Rs>
Specifies the register whose value is to be shifted. Indicates an arithmetic shift right. Is the register containing the value of the shift.
Operation
if Rs[7:0] == 0 then shifter_operand = Rm shifter_carry_out = C Flag else if Rs[7:0] < 32 then shifter_operand = Rm Arithmetic_Shift_Right Rs[7:0] shifter_carry_out = Rm[Rs[7:0] - 1] else /* Rs[7:0] >= 32 */ if Rm[31] == 0 then shifter_operand = 0 shifter_carry_out = Rm[31] else /* Rm[31] == 1 */ shifter_operand = 0xFFFFFFFF shifter_carry_out = Rm[31]
Notes
Use of R15 Specifying R15 as register Rd, register Rm, register Rn, or register Rs has UNPREDICTABLE results.
A5-14
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.1.11 Data-processing operands - Rotate right by immediate
31 28 27 26 25 24 21 20 19 16 15 12 11 7654 3 0
cond
000
opcode
S
Rn
Rd
shift_imm
110
Rm
This data-processing operand is used to provide the value of a register rotated by a constant value. This instruction operand is the value of register Rm rotated right by an immediate value in the range 1 to 31. As bits are rotated off the right end, they are inserted into the vacated bit positions on the left. The carry-out from the shifter is the last bit rotated off the right end.
Syntax
<Rm>, ROR #<shift_imm>
where:
<Rm> ROR <shift_imm>
Specifies the register whose value is to be rotated. Indicates a rotate right. Specifies the rotation. This is an immediate value between 1 and 31. When shift_imm == 0, an RRX operation (rotate right with extend) is performed. This is described in Data-processing operands - Rotate right with extend on page A5-17.
Operation
if shift_imm == 0 then See Data-processing operands - Rotate right with extend on page A5-17 else /* shift_imm > 0 */ shifter_operand = Rm Rotate_Right shift_imm shifter_carry_out = Rm[shift_imm - 1]
Notes
Use of R15 If R15 is specified as register Rm or Rn, the value used is the address of the current instruction plus 8.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-15
ARM Addressing Modes
A5.1.12 Data-processing operands - Rotate right by register
31 28 27 26 25 24 21 20 19 16 15 12 11 8 76543 0
cond
000
opcode
S
Rn
Rd
Rs
0111
Rm
This data-processing operand is used to provide the value of a register rotated by a variable value. This instruction operand is produced by the value of register Rm rotated right by the value in the least significant byte of register Rs. As bits are rotated off the right end, they are inserted into the vacated bit positions on the left. The carry-out from the shifter is the last bit rotated off the right end, or the C flag if the shift amount is zero.
Syntax
<Rm>, ROR <Rs>
where:
<Rm> ROR <Rs>
Specifies the register whose value is to be rotated. Indicates a rotate right. Is the register containing the value of the rotation.
Operation
if Rs[7:0] == 0 then shifter_operand = Rm shifter_carry_out = C Flag else if Rs[4:0] == 0 then shifter_operand = Rm shifter_carry_out = Rm[31] else /* Rs[4:0] > 0 */ shifter_operand = Rm Rotate_Right Rs[4:0] shifter_carry_out = Rm[Rs[4:0] - 1]
Notes
Use of R15 Specifying R15 as register Rd, register Rm, register Rn, or register Rs has UNPREDICTABLE results.
A5-16
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.1.13 Data-processing operands - Rotate right with extend
31 28 27 26 25 24 21 20 19 16 15 12 11 10 9 8765 4 3 0
cond
000
opcode
S
Rn
Rd
00000110
Rm
This data-processing operand can be used to perform a 33-bit rotate right using the Carry Flag as the 33rd bit. This instruction operand is the value of register Rm shifted right by one bit, with the Carry Flag replacing the vacated bit position. The carry-out from the shifter is the bit shifted off the right end.
Syntax
<Rm>, RRX
where:
<Rm> RRX
Specifies the register whose value is shifted right by one bit. Indicates a rotate right with extend.
Operation
shifter_operand = (C Flag Logical_Shift_Left 31) OR (Rm Logical_Shift_Right 1) shifter_carry_out = Rm[0]
Notes
Encoding Use of R15 ADC instruction The instruction encoding is in the space that would be used for ROR #0. If R15 is specified as register Rm or Rn, the value used is the address of the current instruction plus 8. A rotate left with extend can be performed with an ADC instruction.
ADC <Rd>, <Rm>
where <Rn> ==<Rm> for the modified operand to equal the result, or
ADC <Rd>, <Rn>, <Rm>, LSL #1
where the rotate left and extend is the second operand rather than the result.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-17
ARM Addressing Modes
A5.2
Addressing Mode 2 - Load and Store Word or Unsigned Byte
There are nine formats used to calculate the address for a Load and Store Word or Unsigned Byte instruction. The general instruction syntax is:
LDR|STR{<cond>}{B}{T} <Rd>, <addressing_mode>
where <addressing_mode> is one of the nine options listed below. All nine of the following options are available for LDR, LDRB, STR and STRB. For LDRBT, LDRT, STRBT and STRBT, only the post-indexed options (the last three in the list) are available. For the PLD instruction described in PLD on page A4-90, only the offset options (the first three in the list) are available. 1.
[<Rn>, #+/-<offset_12>]
See Load and Store Word or Unsigned Byte - Immediate offset on page A5-20. 2.
[<Rn>, +/-<Rm>]
See Load and Store Word or Unsigned Byte - Register offset on page A5-21. 3.
[<Rn>, +/-<Rm>, <shift> #<shift_imm>]
See Load and Store Word or Unsigned Byte - Scaled register offset on page A5-22. 4.
[<Rn>, #+/-<offset_12>]!
See Load and Store Word or Unsigned Byte - Immediate pre-indexed on page A5-24. 5.
[<Rn>, +/-<Rm>]!
See Load and Store Word or Unsigned Byte - Register pre-indexed on page A5-25. 6.
[<Rn>, +/-<Rm>, <shift> #<shift_imm>]!
See Load and Store Word or Unsigned Byte - Scaled register pre-indexed on page A5-26. 7.
[<Rn>], #+/-<offset_12>
See Load and Store Word or Unsigned Byte - Immediate post-indexed on page A5-28. 8.
[<Rn>], +/-<Rm>
See Load and Store Word or Unsigned Byte - Register post-indexed on page A5-30. 9.
[<Rn>], +/-<Rm>, <shift> #<shift_imm>
See Load and Store Word or Unsigned Byte - Scaled register post-indexed on page A5-31.
A5-18
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.2.1
Encoding
The following three diagrams show the encodings for this addressing mode:
Immediate offset/index
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
0 1 0 P UBWL
Rn
Rd
offset_12
Register offset/index
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 5 4 3 0
cond
0 1 1 P UBWL
Rn
Rd
00000000
Rm
Scaled register offset/index
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 7654 3 0
cond
0 1 1 P UBWL
Rn
Rd
shift_imm
shift 0
Rm
The P bit
Has two meanings: P == 0 Indicates the use of post-indexed addressing. The base register value is used for the memory address, and the offset is then applied to the base register value and written back to the base register. Indicates the use of offset addressing or pre-indexed addressing (the W bit determines which). The memory address is generated by applying the offset to the base register value.
P == 1
The U bit The B bit The W bit
Indicates whether the offset is added to the base (U == 1) or is subtracted from the base (U == 0). Distinguishes between an unsigned byte (B == 1) and a word (B == 0) access. Has two meanings: P == 0 If W == 0, the instruction is LDR, LDRB, STR or STRB and a normal memory access is performed. If W == 1, the instruction is LDRBT, LDRT, STRBT or STRT and an unprivileged (User mode) memory access is performed. If W == 0, the base register is not updated (offset addressing). If W == 1, the calculated memory address is written back to the base register (pre-indexed addressing).
P == 1
The L bit
Distinguishes between a Load (L == 1) and a Store (L == 0).
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-19
ARM Addressing Modes
A5.2.2
Load and Store Word or Unsigned Byte - Immediate offset
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
0 1 0 1UB0L
Rn
Rd
offset_12
This addressing mode calculates an address by adding or subtracting the value of an immediate offset to or from the value of the base register Rn.
Syntax
[<Rn>, #+/-<offset_12>]
where:
<Rn> <offset_12>
Specifies the register containing the base address. Specifies the immediate offset used with the value of Rn to form the address.
Operation
if U == 1 then address = Rn + offset_12 else /* U == 0 */ address = Rn - offset_12
Usage
This addressing mode is useful for accessing structure (record) fields, and accessing parameters and local variables in a stack frame. With an offset of zero, the address produced is the unaltered value of the base register Rn.
Notes
Offset of zero The syntax [<Rn>] is treated as an abbreviation for [<Rn>, #0], unless the instruction is one that only allows post-indexed addressing modes (LDRBT, LDRT, STRBT or STRT). The B bit The L bit Use of R15 This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access. This bit distinguishes between a Load (L==1) and a Store (L==0) instruction. If R15 is specified as register Rn, the value used is the address of the instruction plus eight.
A5-20
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.2.3
Load and Store Word or Unsigned Byte - Register offset
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 5 4 3 0
cond
0 1 1 1UB0L
Rn
Rd
00000000
Rm
This addressing mode calculates an address by adding or subtracting the value of the index register Rm to or from the value of the base register Rn.
Syntax
[<Rn>, +/-<Rm>]
where:
<Rn> <Rm>
Specifies the register containing the base address. Specifies the register containing the value to add to or subtract from Rn.
Operation
if U == 1 then address = Rn + Rm else /* U == 0 */ address = Rn - Rm
Usage
This addressing mode is used for pointer plus offset arithmetic, and accessing a single element of an array of bytes.
Notes
Encoding The B bit The L bit Use of R15 This addressing mode is encoded as an LSL scaled register offset, scaled by zero. This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access. This bit distinguishes between a Load (L==1) and a Store (L==0) instruction. If R15 is specified as register Rn, the value used is the address of the instruction plus eight. Specifying R15 as register Rm has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-21
ARM Addressing Modes
A5.2.4
Load and Store Word or Unsigned Byte - Scaled register offset
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 76543 0
cond
0 1 1 1UB0L
Rn
Rd
shift_imm
shift 0
Rm
These five addressing modes calculate an address by adding or subtracting the shifted or rotated value of the index register Rm to or from the value of the base register Rn.
Syntax
One of:
[<Rn>, [<Rn>, [<Rn>, [<Rn>, [<Rn>, +/-<Rm>, +/-<Rm>, +/-<Rm>, +/-<Rm>, +/-<Rm>, LSL #<shift_imm>] LSR #<shift_imm>] ASR #<shift_imm>] ROR #<shift_imm>] RRX]
where:
<Rn> <Rm> LSL LSR ASR ROR RRX <shift_imm>
Specifies the register containing the base address. Specifies the register containing the offset to add to or subtract from Rn. Specifies a logical shift left. Specifies a logical shift right. Specifies an arithmetic shift right. Specifies a rotate right. Specifies a rotate right with extend. Specifies the shift or rotation.
LSL LSR ASR ROR
0 to 31, encoded directly in the shift_imm field. 1 to 32. A shift amount of 32 is encoded as shift_imm == 0. Other shift amounts are encoded directly. 1 to 32. A shift amount of 32 is encoded as shift_imm == 0. Other shift amounts are encoded directly. 1 to 31, encoded directly in the shift_imm field. (The shift_imm == 0 encoding is used to specify the RRX option.)
A5-22
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
Operation
case shift of 0b00 /* LSL */ index = Rm Logical_Shift_Left shift_imm 0b01 /* LSR */ if shift_imm == 0 then /* LSR #32 */ index = 0 else index = Rm Logical_Shift_Right shift_imm 0b10 /* ASR */ if shift_imm == 0 then /* ASR #32 */ if Rm[31] == 1 then index = 0xFFFFFFFF else index = 0 else index = Rm Arithmetic_Shift_Right shift_imm 0b11 /* ROR or RRX */ if shift_imm == 0 then /* RRX */ index = (C Flag Logical_Shift_Left 31) OR (Rm Logical_Shift_Right 1) else /* ROR */ index = Rm Rotate_Right shift_imm endcase if U == 1 then address = Rn + index else /* U == 0 */ address = Rn - index
Usage
These addressing modes are used for accessing a single element of an array of values larger than a byte.
Notes
The B bit The L bit Use of R15 This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access. This bit distinguishes between a Load (L==1) and a Store (L==0) instruction. If R15 is specified as register Rn, the value used is the address of the instruction plus eight. Specifying R15 as register Rm has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-23
ARM Addressing Modes
A5.2.5
Load and Store Word or Unsigned Byte - Immediate pre-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
0 1 0 1UB1L
Rn
Rd
offset_12
This addressing mode calculates an address by adding or subtracting the value of an immediate offset to or from the value of the base register Rn. If the condition specified in the instruction matches the condition code status, the calculated address is written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
[<Rn>, #+/-<offset_12>]!
where:
<Rn> <offset_12> !
Specifies the register containing the base address. Specifies the immediate offset used with the value of Rn to form the address. Sets the W bit, causing base register update.
Operation
if U == 1 then address = Rn + offset_12 else /* if U == 0 */ address = Rn - offset_12 if ConditionPassed(cond) then Rn = address
Usage
This addressing mode is used for pointer access to arrays with automatic update of the pointer value.
Notes
Offset of zero The syntax [<Rn>] must never be treated as an abbreviation for [<Rn>, #0]!. The B bit The L bit Use of R15 This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access. This bit distinguishes between a Load (L==1) and a Store (L==0) instruction. Specifying R15 as register Rn has UNPREDICTABLE results.
A5-24
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.2.6
Load and Store Word or Unsigned Byte - Register pre-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 5 4 3 0
cond
0 1 1 1UB1L
Rn
Rd
00000000
Rm
This addressing mode calculates an address by adding or subtracting the value of an index register Rm to or from the value of the base register Rn. If the condition specified in the instruction matches the condition code status, the calculated address is written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
[<Rn>, +/-<Rm>]!
where:
<Rn> <Rm> !
Specifies the register containing the base address. Specifies the register containing the offset to add to or subtract from Rn. Sets the W bit, causing base register update.
Operation
if U == 1 then address = Rn + Rm else /* U == 0 */ address = Rn - Rm if ConditionPassed(cond) then Rn = address
Notes
Encoding The B bit The L bit Use of R15 This addressing mode is encoded as an LSL scaled register offset, scaled by zero. This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access. This bit distinguishes between a Load (L==1) and a Store (L==0) instruction. Specifying R15 as register Rm or Rn has UNPREDICTABLE results.
Operand restriction There are no operand restrictions in ARMv6 and above. In earlier versions of the architecture, if the same register is specified for Rn and Rm, the result is
UNPREDICTABLE.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-25
ARM Addressing Modes
A5.2.7
Load and Store Word or Unsigned Byte - Scaled register pre-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 76543 0
cond
0 1 1 1UB1L
Rn
Rd
shift_imm
shift 0
Rm
These five addressing modes calculate an address by adding or subtracting the shifted or rotated value of the index register Rm to or from the value of the base register Rn. If the condition specified in the instruction matches the condition code status, the calculated address is written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
One of:
[<Rn>, [<Rn>, [<Rn>, [<Rn>, [<Rn>, +/-<Rm>, +/-<Rm>, +/-<Rm>, +/-<Rm>, +/-<Rm>, LSL #<shift_imm>]! LSR #<shift_imm>]! ASR #<shift_imm>]! ROR #<shift_imm>]! RRX]!
where:
<Rn> <Rm> LSL LSR ASR ROR RRX <shift_imm>
Specifies the register containing the base address. Specifies the register containing the offset to add to or subtract from Rn. Specifies a logical shift left. Specifies a logical shift right. Specifies an arithmetic shift right. Specifies a rotate right. Specifies a rotate right with extend. Specifies the shift or rotation.
LSL LSR ASR ROR
0 to 31, encoded directly in the shift_imm field. 1 to 32. A shift amount of 32 is encoded as shift_imm == 0. Other shift amounts are encoded directly. 1 to 32. A shift amount of 32 is encoded as shift_imm == 0. Other shift amounts are encoded directly. 1 to 31, encoded directly in the shift_imm field. (The shift_imm == 0 encoding is used to specify the RRX option.)
!
Sets the W bit, causing base register update.
A5-26
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
Operation
case shift of 0b00 /* LSL */ index = Rm Logical_Shift_Left shift_imm 0b01 /* LSR */ if shift_imm == 0 then /* LSR #32 */ index = 0 else index = Rm Logical_Shift_Right shift_imm 0b10 /* ASR */ if shift_imm == 0 then /* ASR #32 */ if Rm[31] == 1 then index = 0xFFFFFFFF else index = 0 else index = Rm Arithmetic_Shift_Right shift_imm 0b11 /* ROR or RRX */ if shift_imm == 0 then /* RRX */ index = (C Flag Logical_Shift_Left 31) OR (Rm Logical_Shift_Right 1) else /* ROR */ index = Rm Rotate_Right shift_imm endcase if U == 1 then address = Rn + index else /* U == 0 */ address = Rn - index if ConditionPassed(cond) then Rn = address
Notes
The B bit The L bit Use of R15 This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access. This bit distinguishes between a Load (L==1) and a Store (L==0) instruction. Specifying R15 as register Rm or Rn has UNPREDICTABLE results.
Operand restriction There are no operand restrictions in ARM v6 and above. In earlier versions of the architecture, if the same register is specified for Rn and Rm, the result is
UNPREDICTABLE.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-27
ARM Addressing Modes
A5.2.8
Load and Store Word or Unsigned Byte - Immediate post-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond
0 1 0 0UB0L
Rn
Rd
offset_12
This addressing mode uses the value of the base register Rn as the address for the memory access. If the condition specified in the instruction matches the condition code status, the value of the immediate offset is added to or subtracted from the value of the base register Rn and written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
[<Rn>], #+/-<offset_12>
where:
<Rn> <offset_12>
Specifies the register containing the base address. Specifies the immediate offset used with the value of Rn to form the address.
Operation
address = Rn if ConditionPassed(cond) then if U == 1 then Rn = Rn + offset_12 else /* U == 0 */ Rn = Rn - offset_12
Usage
This addressing mode is used for pointer access to arrays with automatic update of the pointer value.
A5-28
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
Notes
Post-indexed addressing modes
LDRBT, LDRT, STRBT, and STRT only support post-indexed addressing modes. They use a minor modification of the above bit pattern, where bit[21] (the W bit) is 1, not 0 as shown.
Offset of zero The syntax [<Rn>] is treated as an abbreviation for [<Rn>],#0 for instructions that only support post-indexed addressing modes (LDRBT, LDRT, STRBT, STRT), but not for other instructions. The B bit The L bit Use of R15 This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access. This bit distinguishes between a Load (L==1) and a Store (L==0) instruction. Specifying R15 as register Rn has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-29
ARM Addressing Modes
A5.2.9
Load and Store Word or Unsigned Byte - Register post-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 76543 0
cond
0 1 1 0UB0L
Rn
Rd
00000000
Rm
This addressing mode uses the value of the base register Rn as the address for the memory access. If the condition specified in the instruction matches the condition code status, the value of the index register Rm is added to or subtracted from the value of the base register Rn and written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
[<Rn>], +/-<Rm>
where:
<Rn> <Rm>
Specifies the register containing the base address. Specifies the register containing the offset to add to or subtract from Rn.
Operation
address = Rn if ConditionPassed(cond) then if U == 1 then Rn = Rn + Rm else /* U == 0 */ Rn = Rn - Rm
Notes
Encoding This addressing mode is encoded as an LSL scaled register offset, scaled by zero.
Post-indexed addressing modes
LDRBT, LDRT, STRBT, and STRT only support post-indexed addressing modes. They use a minor modification of the above bit pattern, where bit[21] (the W bit) is 1, not 0 as shown.
The B bit The L bit Use of R15
This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access. This bit distinguishes between a Load (L==1) and a Store (L==0) instruction. Specifying R15 as register Rn or Rm has UNPREDICTABLE results.
Operand restriction There are no operand restrictions in ARMv6 and above. In earlier versions of the architecture, if the same register is specified for Rn and Rm, the result is
UNPREDICTABLE.
A5-30
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.2.10 Load and Store Word or Unsigned Byte - Scaled register post-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 7654 3 0
cond
0 1 1 0UB0L
Rn
Rd
shift_imm
shift 0
Rm
This addressing mode uses the value of the base register Rn as the address for the memory access. If the condition specified in the instruction matches the condition code status, the shifted or rotated value of index register Rm is added to or subtracted from the value of the base register Rn and written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
One of:
[<Rn>], [<Rn>], [<Rn>], [<Rn>], [<Rn>], +/-<Rm>, +/-<Rm>, +/-<Rm>, +/-<Rm>, +/-<Rm>, LSL LSR ASR ROR RRX #<shift_imm> #<shift_imm> #<shift_imm> #<shift_imm>
where:
<Rn> <Rm> LSL LSR ASR ROR RRX <shift_imm>
Specifies the register containing the base address. Specifies the register containing the offset to add to or subtract from Rn. Specifies a logical shift left. Specifies a logical shift right. Specifies an arithmetic shift right. Specifies a rotate right. Specifies a rotate right with extend. Specifies the shift or rotation.
LSL LSR ASR ROR
0 to 31, encoded directly in the shift_imm field. 1 to 32. A shift amount of 32 is encoded as shift_imm == 0. Other shift amounts are encoded directly. 1 to 32. A shift amount of 32 is encoded as shift_imm == 0. Other shift amounts are encoded directly. 1 to 31, encoded directly in the shift_imm field. (The shift_imm == 0 encoding is used to specify the RRX option.)
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-31
ARM Addressing Modes
Operation
address = Rn case shift of 0b00 /* LSL */ index = Rm Logical_Shift_Left shift_imm 0b01 /* LSR */ if shift_imm == 0 then /* LSR #32 */ index = 0 else index = Rm Logical_Shift_Right shift_imm 0b10 /* ASR */ if shift_imm == 0 then /* ASR #32 */ if Rm[31] == 1 then index = 0xFFFFFFFF else index = 0 else index = Rm Arithmetic_Shift_Right shift_imm 0b11 /* ROR or RRX */ if shift_imm == 0 then /* RRX */ index = (C Flag Logical_Shift_Left 31) OR (Rm Logical_Shift_Right 1) else /* ROR */ index = Rm Rotate_Right shift_imm endcase if ConditionPassed(cond) then if U == 1 then Rn = Rn + index else /* U == 0 */ Rn = Rn - index
Notes
The W bit
LDRBT, LDRT, STRBT, and STRT only support post-indexed addressing modes. They use a minor modification of the above bit pattern, where bit[21] (the W bit) is 1, not 0 as shown.
The B bit The L bit Use of R15
This bit distinguishes between an unsigned byte (B == 1) and a word (B == 0) access. This bit distinguishes between a Load (L == 1) and a Store (L == 0) instruction. Specifying R15 as register Rm or Rn has UNPREDICTABLE results.
Operand restriction There are no operand restrictions in ARMv6 and above. In earlier versions of the architecture, if the same register is specified for Rn and Rm, the result is
UNPREDICTABLE.
A5-32
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.3
Addressing Mode 3 - Miscellaneous Loads and Stores
There are six formats used to calculate the address for load and store (signed or unsigned) halfword, load signed byte, or load and store doubleword instructions. The general instruction syntax is:
LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
where <addressing_mode> is one of the following six options: 1.
[<Rn>, #+/-<offset_8>]
See Miscellaneous Loads and Stores - Immediate offset on page A5-35. 2.
[<Rn>, +/-<Rm>]
See Miscellaneous Loads and Stores - Register offset on page A5-36. 3.
[<Rn>, #+/-<offset_8>]!
See Miscellaneous Loads and Stores - Immediate pre-indexed on page A5-37. 4.
[<Rn>, +/-<Rm>]!
See Miscellaneous Loads and Stores - Register pre-indexed on page A5-38. 5.
[<Rn>], #+/-<offset_8>
See Miscellaneous Loads and Stores - Immediate post-indexed on page A5-39. 6.
[<Rn>], +/-<Rm>
See Miscellaneous Loads and Stores - Register post-indexed on page A5-40.
A5.3.1
Encoding
The following diagrams show the encodings for this addressing mode:
Immediate offset/index
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
0 0 0 PU 1WL
Rn
Rd
immedH
1SH1
ImmedL
Register offset/index
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
0 0 0 PU 0WL
Rn
Rd
SBZ
1SH1
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-33
ARM Addressing Modes
The P bit
Has two meanings: P == 0 Indicates the use of post-indexed addressing. The base register value is used for the memory address, and the offset is then applied to the base register value and written back to the base register. Indicates the use of offset addressing or pre-indexed addressing (the W bit determines which). The memory address is generated by applying the offset to the base register value.
P == 1
The U bit The W bit
Indicates whether the offset is added to the base (U == 1) or subtracted from the base (U == 0). Has two meanings: P == 0 P == 1 The W bit must be 0 or the instruction is UNPREDICTABLE. W == 1 indicates that the memory address is written back to the base register (pre-indexed addressing), and W == 0 that the base register is unchanged (offset addressing).
The L, S and H bits These bits combine to specify signed or unsigned loads or stores, and doubleword, halfword, or byte accesses: L=0, S=0, H=1 L=0, S=1, H=0 L=0, S=1, H=1 L=1, S=0, H=1 L=1, S=1, H=0 L=1, S=1, H=1 Store halfword. Load doubleword. Store doubleword. Load unsigned halfword. Load signed byte. Load signed halfword.
Prior to v5TE, the bits were denoted as Load/!Store (L), Signed/!Unsigned (S) and halfword/!Byte (H) bits. Signed bytes and halfwords can be stored with the same STRB and STRH instructions as are used for unsigned quantities, so no separate signed store instructions are provided. Unsigned bytes If S == 0 and H == 0, apparently indicating an unsigned byte, the instruction is not one that uses this addressing mode. Instead, it is a multiply instruction, a SWP or SWPB instruction, an LDREX or STREX instruction, or an unallocated instruction in the arithmetic or load/store instruction extension space (see Extending the instruction set on page A3-32). Unsigned bytes are accessed by the LDRB, LDRBT, STRB and STRBT instructions, which use addressing mode 2 rather than addressing mode 3. Signed stores If S ==1 and L == 0, apparently indicating a signed store instruction, the encoding along with the H-bit is used to support the LDRD (H == 0) and STRD (H == 1) instructions.
A5-34
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.3.2
Miscellaneous Loads and Stores - Immediate offset
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
0001U10L
Rn
Rd
immedH
1SH1
immedL
This addressing mode calculates an address by adding or subtracting the value of an immediate offset to or from the value of the base register Rn.
Syntax
[<Rn>, #+/-<offset_8>]
where:
<Rn> <offset_8>
Specifies the register containing the base address. Specifies the immediate offset used with the value of Rn to form the address. The offset is encoded in immedH (top 4 bits) and immedL (bottom 4 bits).
Operation
offset_8 = (immedH << 4) OR immedL if U == 1 then address = Rn + offset_8 else /* U == 0 */ address = Rn - offset_8
Usage
This addressing mode is used for accessing structure (record) fields, and accessing parameters and locals variable in a stack frame. With an offset of zero, the address produced is the unaltered value of the base register Rn.
Notes
Zero offset The syntax [<Rn>] is treated as an abbreviation for [<Rn>,#0].
The L, S and H bits The L, S and H bits are defined in Encoding on page A5-33. Use of R15 If R15 is specified as register Rn, the value used is the address of the instruction plus eight.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-35
ARM Addressing Modes
A5.3.3
Miscellaneous Loads and Stores - Register offset
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0001U00L
Rn
Rd
SBZ
1SH1
Rm
This addressing mode calculates an address by adding or subtracting the value of the index register Rm to or from the value of the base register Rn.
Syntax
[<Rn>, +/-<Rm>]
where:
<Rn> <Rm>
Specifies the register containing the base address. Specifies the register containing the offset to add to or subtract from Rn.
Operation
if U == 1 then address = Rn + Rm else /* U == 0 */ address = Rn - Rm
Usage
This addressing mode is useful for pointer plus offset arithmetic and for accessing a single element of an array.
Notes
The L, S and H bits Unsigned bytes The L, S and H bits are defined in Encoding on page A5-33. If S == 0 and H == 0, apparently indicating an unsigned byte, the instruction is not one that uses this addressing mode. Instead, it is a multiply instruction, a SWP or SWPB instruction, or an unallocated instruction in the arithmetic or load/store instruction extension space (see Extending the instruction set on page A3-32). Unsigned bytes are accessed by the LDRB, LDRBT, STRB and STRBT instructions, which use addressing mode 2 rather than addressing mode 3. Use of R15 If R15 is specified as register Rn, the value used is the address of the instruction plus eight. Specifying R15 as register Rm has UNPREDICTABLE results.
A5-36
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.3.4
Miscellaneous Loads and Stores - Immediate pre-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
0001U11L
Rn
Rd
immedH
1SH1
ImmedL
This addressing mode calculates an address by adding or subtracting the value of an immediate offset to or from the value of the base register Rn. If the condition specified in the instruction matches the condition code status, the calculated address is written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
[<Rn>, #+/-<offset_8>]!
where:
<Rn> <offset_8>
Specifies the register containing the base address. Specifies the immediate offset used with the value of Rn to form the address. The offset is encoded in immedH (top 4 bits) and immedL (bottom 4 bits). Sets the W bit, causing base register update.
!
Operation
offset_8 = (immedH << 4) OR immedL if U == 1 then address = Rn + offset_8 else /* U == 0 */ address = Rn - offset_8 if ConditionPassed(cond) then Rn = address
Usage
This addressing mode gives pointer access to arrays, with automatic update of the pointer value.
Notes
Offset of zero The L, S and H bits Use of R15 The syntax [<Rn>] must not be treated as an abbreviation for [<Rn>,#0]!. The L, S and H bits are defined in Encoding on page A5-33. Specifying R15 as register Rn has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-37
ARM Addressing Modes
A5.3.5
Miscellaneous Loads and Stores - Register pre-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0001U01L
Rn
Rd
SBZ
1SH1
Rm
This addressing mode calculates an address by adding or subtracting the value of the index register Rm to or from the value of the base register Rn. If the condition specified in the instruction matches the condition code status, the calculated address is written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
[<Rn>, +/-<Rm>]!
where:
<Rn> <Rm> !
Specifies the register containing the base address. Specifies the register containing the offset to add to or subtract from Rn. Sets the W bit, causing base register update.
Operation
if U == 1 then address = Rn + Rm else /* U == 0 */ address = Rn - Rm if ConditionPassed(cond) then Rn = address
Notes
The L, S and H bits Use of R15 The L, S and H bits are defined in Encoding on page A5-33. Specifying R15 as register Rm or Rn has UNPREDICTABLE results.
Operand restriction There are no operand restrictions in ARMv6 and above. In earlier versions of the architecture, if the same register is specified for Rn and Rm, the result is
UNPREDICTABLE.
A5-38
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.3.6
Miscellaneous Loads and Stores - Immediate post-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87654 3 0
cond
0000U10L
Rn
Rd
immedH
1SH1
ImmedL
This addressing mode uses the value of the base register Rn as the address for the memory access. If the condition specified in the instruction matches the condition code status, the value of the immediate offset is added to or subtracted from the value of the base register Rn and written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
[<Rn>], #+/-<offset_8>
where:
<Rn> <offset_8>
Specifies the register containing the base address. Specifies the immediate offset used with the value of Rn to form the address. The offset is encoded in immedH (top 4 bits) and immedL (bottom 4 bits).
Operation
address = Rn offset_8 = (immedH << 4) OR immedL if ConditionPassed(cond) then if U == 1 then Rn = Rn + offset_8 else /* U == 0 */ Rn = Rn - offset_8
Usage
This addressing mode gives pointer access to arrays, with automatic update of the pointer value.
Notes
Offset of zero The L, S and H bits Use of R15 The syntax [<Rn>] must not be treated as an abbreviation for [<Rn>],#0. The L, S and H bits are defined in Encoding on page A5-33. Specifying R15 as register Rn has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-39
ARM Addressing Modes
A5.3.7
Miscellaneous Loads and Stores - Register post-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 76543 0
cond
0000U00L
Rn
Rd
SBZ
1SH1
Rm
This addressing mode uses the value of the base register Rn as the address for the memory access. If the condition specified in the instruction matches the condition code status, the value of the index register Rm is added to or subtracted from the value of the base register Rn and written back to the base register Rn. The conditions are defined in The condition field on page A3-3.
Syntax
[<Rn>], +/-<Rm>
where:
<Rn> <Rm>
Specifies the register containing the base address. Specifies the register containing the offset to add to or subtract from Rn.
Operation
address = Rn if ConditionPassed(cond) then if U == 1 then Rn = Rn + Rm else /* U == 0 */ Rn = Rn - Rm
Notes
The L, S and H bits Use of R15 The L, S and H bits are defined in Encoding on page A5-33. Specifying R15 as register Rm or Rn has UNPREDICTABLE results.
Operand restriction There are no operand restrictions in ARMv6 and above. In earlier versions of the architecture, if the same register is specified for Rn and Rm, the result is
UNPREDICTABLE.
A5-40
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.4
Addressing Mode 4 - Load and Store Multiple
Load Multiple instructions load a subset (possibly all) of the general-purpose registers from memory. Store Multiple instructions store a subset (possibly all) of the general-purpose registers to memory. Load and Store Multiple addressing modes produce a sequential range of addresses. The lowest-numbered register is stored at the lowest memory address and the highest-numbered register at the highest memory address. The general instruction syntax is:
LDM|STM{<cond>}<addressing_mode> <Rn>{!}, <registers>{^}
where <addressing_mode> is one of the following four addressing modes: 1.
IA (Increment After)
See Load and Store Multiple - Increment after on page A5-43. 2.
IB (Increment Before)
See Load and Store Multiple - Increment before on page A5-44. 3.
DA (Decrement After)
See Load and Store Multiple - Decrement after on page A5-45. 4.
DB (Decrement Before)
See Load and Store Multiple - Decrement before on page A5-46. There are also alternative mnemonics for these addressing modes, useful when LDM and STM are being used to access a stack, see Load and Store Multiple addressing modes (alternative names) on page A5-47.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-41
ARM Addressing Modes
A5.4.1
Encoding
The following diagram shows the encoding for this addressing mode:
31 28 27 26 25 24 23 22 21 20 19 16 15 0
cond
1 0 0 PUSWL
Rn
register list
The P bit
Has two meanings: P==0 P==1 indicates that the word addressed by Rn is included in the range of memory locations accessed, lying at the top (U==0) or bottom (U==1) of that range. indicates that the word addressed by Rn is excluded from the range of memory locations accessed, and lies one word beyond the top of the range (U==0) or one word below the bottom of the range (U==1).
The U bit The S bit
Indicates that the transfer is made upwards (U==1) or downwards (U==0) from the base register. For LDMs that load the PC, the S bit indicates that the CPSR is loaded from the SPSR. For LDMs that do not load the PC and all STMs, the S bit indicates that when the processor is in a privileged mode, the User mode banked registers are transferred instead of the registers of the current mode.
LDM with the S bit set is UNPREDICTABLE in User or System mode.
The W bit The L bit Register list
Indicates that the base register is updated after the transfer. The base register is incremented (U==1) or decremented (U==0) by four times the number of registers in the register list. Distinguishes between Load (L==1) and Store (L==0) instructions. The register_list field of the instruction has one bit for each general-purpose register: bit[0] for register zero through to bit[15] for register 15 (the PC). If no bits are set, the result is
UNPREDICTABLE.
The instruction syntax specifies the registers to load or store in <registers>, which is a comma-separated list of registers, surrounded by { and }.
A5-42
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.4.2
Load and Store Multiple - Increment after
31 28 27 26 25 24 23 22 21 20 19 16 15 0
cond
1 0 0 0 1 SWL
Rn
register list
This addressing mode is for Load and Store Multiple instructions, and forms a range of addresses. The first address formed is the <start_address>, and is the value of the base register Rn. Subsequent addresses are formed by incrementing the previous address by four. One address is produced for each register that is specified in <registers>. The last address produced is the <end_address>. Its value is four less than the sum of the value of the base register and four times the number of registers specified in <registers>. If the condition specified in the instruction matches the condition code status and the W bit is set, Rn is incremented by four times the number of registers in <registers>. The conditions are defined in The condition field on page A3-3.
Syntax
IA
See also the alternative syntax described in Load and Store Multiple addressing modes (alternative names) on page A5-47.
Operation
start_address = Rn end_address = Rn + (Number_Of_Set_Bits_In(register_list) * 4) - 4 if ConditionPassed(cond) and W == 1 then Rn = Rn + (Number_Of_Set_Bits_In(register_list) * 4)
Notes
The L bit The S bit This bit distinguishes between a Load Multiple and a Store Multiple. For LDMs that load the PC, the S bit indicates that the CPSR is loaded from the SPSR. For LDMs that do not load the PC and all STMs, the S bit indicates that when the processor is in a privileged mode, the User mode banked registers are transferred instead of the registers of the current mode.
LDM with the S bit set is UNPREDICTABLE in User or System mode.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-43
ARM Addressing Modes
A5.4.3
Load and Store Multiple - Increment before
31 28 27 26 25 24 23 22 21 20 19 16 15 0
cond
1 0 0 1 1 SWL
Rn
register list
This addressing mode is for Load and Store Multiple instructions, and forms a range of addresses. The first address formed is the <start_address>, and is the value of the base register Rn plus four. Subsequent addresses are formed by incrementing the previous address by four. One address is produced for each register that is specified in <registers>. The last address produced is the <end_address>. Its value is the sum of the value of the base register and four times the number of registers specified in <registers>. If the condition specified in the instruction matches the condition code status and the W bit is set, Rn is incremented by four times the number of registers in <registers>. The conditions are defined in The condition field on page A3-3.
Syntax
IB
See also the alternative syntax described in Load and Store Multiple addressing modes (alternative names) on page A5-47.
Operation
start_address = Rn + 4 end_address = Rn + (Number_Of_Set_Bits_In(register_list) * 4) if ConditionPassed(cond) and W == 1 then Rn = Rn + (Number_Of_Set_Bits_In(register_list) * 4)
Notes
The L bit The S bit This bit distinguishes between a Load Multiple and a Store Multiple. For LDMs that load the PC, the S bit indicates that the CPSR is loaded from the SPSR. For LDMs that do not load the PC and all STMs, the S bit indicates that when the processor is in a privileged mode, the User mode banked registers are transferred instead of the registers of the current mode.
LDM with the S bit set is UNPREDICTABLE in User or System mode.
A5-44
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.4.4
Load and Store Multiple - Decrement after
31 28 27 26 25 24 23 22 21 20 19 16 15 0
cond
1 0 0 0 0 SWL
Rn
register list
This addressing mode is for Load and Store Multiple instructions, and forms a range of addresses. The first address formed is the <start_address>, and is the value of the base register minus four times the number of registers specified in <registers>, plus 4. Subsequent addresses are formed by incrementing the previous address by four. One address is produced for each register that is specified in <registers>. The last address produced is the <end_address>. Its value is the value of the base register Rn. If the condition specified in the instruction matches the condition code status and the W bit is set, Rn is decremented by four times the number of registers in <registers>. The conditions are defined in The condition field on page A3-3.
Syntax
DA
See also the alternative syntax described in Load and Store Multiple addressing modes (alternative names) on page A5-47.
Operation
start_address = Rn - (Number_Of_Set_Bits_In(register_list) * 4) + 4 end_address = Rn if ConditionPassed(cond) and W == 1 then Rn = Rn - (Number_Of_Set_Bits_In(register_list) * 4)
Notes
The L bit The S bit This bit distinguishes between a Load Multiple and a Store Multiple. For LDMs that load the PC, the S bit indicates that the CPSR is loaded from the SPSR. For LDMs that do not load the PC and all STMs, the S bit indicates that when the processor is in a privileged mode, the User mode banked registers are transferred instead of the registers of the current mode.
LDM with the S bit set is UNPREDICTABLE in User or System mode.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-45
ARM Addressing Modes
A5.4.5
Load and Store Multiple - Decrement before
31 28 27 26 25 24 23 22 21 20 19 16 15 0
cond
1 0 0 1 0 SWL
Rn
register list
This addressing mode is for Load and Store multiple instructions, and forms a range of addresses. The first address formed is the <start_address>, and is the value of the base register minus four times the number of registers specified in <registers>. Subsequent addresses are formed by incrementing the previous address by four. One address is produced for each register that is specified in <registers>. The last address produced is the <end_address>. Its value is the value of the base register Rn minus four. If the condition specified in the instruction matches the condition code status and the W bit is set, Rn is decremented by four times the number of registers in <registers>. The conditions are defined in The condition field on page A3-3.
Syntax
DB
See also the alternative syntax described in Load and Store Multiple addressing modes (alternative names) on page A5-47.
Architecture version
All
Operation
start_address = Rn - (Number_Of_Set_Bits_In(register_list) * 4) end_address = Rn - 4 if ConditionPassed(cond) and W == 1 then Rn = Rn - (Number_Of_Set_Bits_In(register_list) * 4)
Notes
The L bit The S bit This bit distinguishes between a Load Multiple and a Store Multiple. For LDMs that load the PC, the S bit indicates that the CPSR is loaded from the SPSR. For LDMs that do not load the PC and all STMs, the S bit indicates that when the processor is in a privileged mode, the User mode banked registers are transferred instead of the registers of the current mode.
LDM with the S bit set is UNPREDICTABLE in User or System mode.
A5-46
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.4.6
Load and Store Multiple addressing modes (alternative names)
The four addressing mode names given in Addressing Mode 4 - Load and Store Multiple on page A5-41 (IA, IB, DA, DB) are most useful when a load and Store Multiple instruction is being used for block data transfer, as it is likely that the Load Multiple and Store Multiple have the same addressing mode, so that the data is stored in the same way that it was loaded. However, if Load Multiple and Store Multiple are being used to access a stack, the data is not loaded with the same addressing mode that was used to store the data, because the load (pop) and store (push) operations must adjust the stack in opposite directions.
Stack operations
Load Multiple and Store Multiple addressing modes can be specified with an alternative syntax, which is more applicable to stack operations: Full stacks Empty stacks Descending stacks Ascending stacks Have stack pointers that point to the last used (full) location. Have stack pointers that point to the first unused (empty) location. Grow towards decreasing memory addresses (towards the bottom of memory). Grow towards increasing memory addresses (towards the top of memory).
Two attributes allow four types of stack to be defined: Full Descending, with the syntax FD Empty Descending, with the syntax ED Full Ascending, with the syntax FA Empty Ascending, with the syntax EA.
Note
When defining stacks on which coprocessor data is to be placed (or might be placed in the future), programmers are advised to use the FD or EA stack types. This is because coprocessor data can be pushed to these types of stack with a single STC instruction and popped from them with a single LDC instruction. Multi-instruction sequences are required for coprocessor access to FA or ED stacks. Table A5-1 on page A5-48 and Table A5-2 on page A5-48 show the relationship between the four types of stack, the four types of addressing mode shown above, and the L, U, and P bits in the instruction format.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-47
ARM Addressing Modes
Table A5-1 shows the relationship for LDM instructions. Table A5-1 LDM addressing modes Non-stack addressing mode
LDMDA (Decrement After) LDMIA (Increment After) LDMDB (Decrement Before) LDMIB (Increment Before)
Stack addressing mode
LDMFA (Full Ascending) LDMFD (Full Descending) LDMEA (Empty Ascending) LDMED (Empty Descending)
L bit 1 1 1 1
P bit 0 0 1 1
U bit 0 1 0 1
Table A5-2 shows the relationship for STM instructions. Table A5-2 STM addressing modes Non-stack addressing mode
STMDA (Decrement After) STMIA (Increment After) STMDB (Decrement Before) STMIB (Increment Before)
Stack addressing mode
STMED (Empty Descending) STMEA (Empty Ascending) STMFD (Full Descending) STMFA (Full Ascending)
L bit 0 0 0 0
P bit 0 0 1 1
U bit 0 1 0 1
A5-48
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.5
Addressing Mode 5 - Load and Store Coprocessor
There are four addressing modes which are used to calculate the address of a Load or Store Coprocessor instruction. The general instruction syntax is:
<opcode>{<cond>}{L} <coproc>,<CRd>,<addressing_mode>
where <addressing_mode> is one of the following four options: 1.
[<Rn>,#+/-<offset_8>*4]
See Load and Store Coprocessor - Immediate offset on page A5-51. 2.
[<Rn>,#+/-<offset_8>*4]!
See Load and Store Coprocessor - Immediate pre-indexed on page A5-52. 3.
[<Rn>],#+/-<offset_8>*4
See Load and Store Coprocessor - Immediate post-indexed on page A5-53. 4.
[<Rn>],<option>
See Load and Store Coprocessor - Unindexed on page A5-54.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-49
ARM Addressing Modes
A5.5.1
Encoding
The following diagram shows the encoding for this addressing mode:
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 0
cond
1 1 0 P UNWL
Rn
CRd
cp_num
offset_8
The P bit
Has two meanings: P == 0 P == 1 Indicates the use of post-indexed addressing or unindexed addressing (the W bit determines which). The base register value is used for the memory address. Indicates the use of offset addressing or pre-indexed addressing (the W bit determines which). The memory address is generated by applying the offset to the base register value.
The U bit
Has two meanings: U == 1 Indicates that the offset is added to the base. U == 0 Indicates that the offset is subtracted from the base The meaning of this bit is coprocessor-dependent. Its recommended use is to distinguish between different-sized values to be transferred. Has two meanings: W == 1 Indicates that the memory address is written back to the base register. W == 0 Indicates that the base register value is unchanged. Also: If P == 0, this distinguishes unindexed addressing (W == 0) from post-indexed addressing (W == 1). For unindexed addressing, U must equal 1 or the result is either UNDEFINED or UNPREDICTABLE (see Coprocessor instruction extension space on page A3-40). If P == 1, this distinguishes offset addressing (W == 0) from pre-indexed addressing (W == 1).
The N bit The W bit
The L bit
Distinguishes between Load (L == 1) and Store (L == 0) instructions.
A5-50
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.5.2
Load and Store Coprocessor - Immediate offset
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87 0
cond
1 1 0 1UN0L
Rn
CRd
cp_num
offset_8
This addressing mode produces a sequence of consecutive addresses. The first address is calculated by adding or subtracting four times the value of an immediate offset to or from the value of the base register Rn. The subsequent addresses in the sequence are produced by incrementing the previous address by four until the coprocessor signals the end of the instruction. This allows a coprocessor to access data whose size is coprocessor-defined. The coprocessor must not request a transfer of more than 16 words.
Syntax
[<Rn>, #+/-<offset_8>*4]
where:
<Rn> <offset_8>
Specifies the register containing the base address. Specifies the immediate offset that is multiplied by 4, then added to or subtracted from the value of Rn to form the address.
Operation
if ConditionPassed(cond) then if U == 1 then address = Rn + offset_8 * 4 else /* U == 0 */ address = Rn - offset_8 * 4 start_address = address while (NotFinished(coprocessor[cp_num])) address = address + 4 end_address = address
Notes
The N bit The L bit Use of R15 Is coprocessor-dependent. Distinguishes between Load (L==1) and Store (L==0) instructions. If R15 is specified as register Rn, the value used is the address of the instruction plus eight.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-51
ARM Addressing Modes
A5.5.3
Load and Store Coprocessor - Immediate pre-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 0
cond
1 1 0 1UN1L
Rn
CRd
cp_num
offset_8
This addressing mode produces a sequence of consecutive addresses. The first address is calculated by adding or subtracting four times the value of an immediate offset to or from the value of the base register Rn. If the condition specified in the instruction matches the condition code status, the first address is written back to the base register Rn. The subsequent addresses in the sequence are produced by incrementing the previous address by four until the coprocessor signals the end of the instruction. This allows a coprocessor to access data whose size is coprocessor-defined. The coprocessor must not request a transfer of more than 16 words.
Syntax
[<Rn>, #+/-<offset_8>*4]!
where:
<Rn> <offset_8>
Specifies the register containing the base address. Specifies the immediate offset that is multiplied by 4, then added to or subtracted from the value of Rn to form the address. Sets the W bit, causing base register update.
!
Operation
if ConditionPassed(cond) then if U == 1 then Rn = Rn + offset_8 * 4 else /* U == 0 */ Rn = Rn - offset_8 * 4 start_address = Rn address = start_address while (NotFinished(coprocessor[cp_num])) address = address + 4 end_address = address
Notes
The N bit The L bit Use of R15 Is coprocessor-dependent. Distinguishes between Load (L==1) and Store (L==0) instructions. Specifying R15 as register Rn has UNPREDICTABLE results.
A5-52
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
ARM Addressing Modes
A5.5.4
Load and Store Coprocessor - Immediate post-indexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 87 0
cond
1 1 0 0UN1L
Rn
CRd
cp_num
offset_8
This addressing mode produces a sequence of consecutive addresses. The first address is the value of the base register Rn. The subsequent addresses in the sequence are produced by incrementing the previous address by four until the coprocessor signals the end of the instruction. This allows a coprocessor to access data whose size is coprocessor-defined. If the condition specified in the instruction matches the condition code status, the base register Rn is updated by adding or subtracting four times the value of an immediate offset to or from the value of the base register Rn. The coprocessor must not request a transfer of more than 16 words.
Syntax
[<Rn>], #+/-<offset_8>*4
where:
<Rn> <offset_8>
Specifies the register containing the base address. Specifies the immediate offset that is multiplied by 4, then added to or subtracted from the value of Rn to form the address.
Operation
if ConditionPassed(cond) then start_address = Rn if U == 1 then Rn = Rn + offset_8 * 4 else /* U == 0 */ Rn = Rn - offset_8 * 4 address = start_address while (NotFinished(coprocessor[cp_num])) address = address + 4 end_address = address
Notes
The N bit The L bit Use of R15 Is coprocessor-dependent. Distinguishes between Load (L==1) and Store (L==0) instructions. Specifying R15 as register Rn has UNPREDICTABLE results.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A5-53
ARM Addressing Modes
A5.5.5
Load and Store Coprocessor - Unindexed
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 0
cond
1 1 0 0UN0L
Rn
CRd
cp_num
option
This addressing mode produces a sequence of consecutive addresses. The first address is the value of the base register Rn. The subsequent addresses in the sequence are produced by incrementing the previous address by four until the coprocessor signals the end of the instruction. This allows a coprocessor to access data whose size is coprocessor-defined. The base register Rn is not updated. Bits[7:0] of the instruction are therefore not used by the ARM, either for the address calculation or to calculate a new value for the base register, and so can be used to specify additional instruction options to the coprocessor. The coprocessor must not request a transfer of more than 16 words.
Syntax
[<Rn>], <option>
where:
<Rn> <option>
Specifies the register containing the base address. Specifies additional instruction options to the coprocessor. The <option> is specified in the instruction syntax as an integer in the range 0-255, surrounded by { and }.
Operation
if ConditionPassed(cond) then start_address = Rn address = start_address while (NotFinished(coprocessor[cp_num])) address = address + 4 end_address = address
Notes
The N bit The L bit Use of R15 The U bit Option bits Is coprocessor-dependent. Distinguishes between Load (L==1) and Store (L==0) instructions. If R15 is specified as register Rn, the value used is the address of the instruction plus eight. If bit[23] (the Up/down bit) is not set, the result is either UNDEFINED or UNPREDICTABLE (see Coprocessor instruction extension space on page A3-40). Are unused by the ARM in this addressing mode, and therefore can be used to request additional instruction options in a coprocessor-dependent fashion.
A5-54
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Chapter A6 The Thumb Instruction Set
This chapter introduces the Thumb instruction set and describes how Thumb uses the ARM programmers model. It contains the following sections: About the Thumb instruction set on page A6-2 Instruction set encoding on page A6-4 Branch instructions on page A6-6 Data-processing instructions on page A6-8 Load and Store Register instructions on page A6-15 Load and Store Multiple instructions on page A6-18 Exception-generating instructions on page A6-20 Undefined Instruction space on page A6-21.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-1
The Thumb Instruction Set
A6.1
About the Thumb instruction set
The Thumb instruction set is a re-encoded subset of the ARM instruction set. Thumb is designed to increase the performance of ARM implementations that use a 16-bit or narrower memory data bus and to allow better code density than provided by the ARM instruction set. T variants of the ARM architecture incorporate both a full 32-bit ARM instruction set and the 16-bit Thumb instruction set. Every Thumb instruction is encoded in 16 bits. Thumb support is mandatory in ARMv6. Thumb does not alter the underlying programmers model of the ARM architecture. It merely presents restricted access to it. All Thumb data-processing instructions operate on full 32-bit values, and full 32-bit addresses are produced by both data-access instructions and instruction fetches. When the processor is executing Thumb instructions, eight general-purpose integer registers are available, R0 to R7, which are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access the Program Counter (ARM register 15), the Link Register (ARM register 14) and the Stack Pointer (ARM register 13). Further instructions allow limited access to ARM registers 8 to 15, which are known as the high registers. When R15 is read, bit[0] is zero and bits[31:1] contain the PC. When R15 is written, bit[0] is IGNORED and bits[31:1] are written to the PC. Depending on how it is used, the value of the PC is either the address of the instruction plus 4 or is UNPREDICTABLE. Thumb execution is flagged by the T bit (bit[5]) in the CPSR: T == 0 T == 1 32-bit instructions are fetched (and the PC is incremented by four) and are executed as ARM instructions. 16-bit instructions are fetched (and the PC is incremented by two) and are executed as Thumb instructions.
In ARMv6, the Thumb instruction set provides limited access to the CPSR with the CPS instruction. There is no direct access to the SPSRs. Earlier versions provided no direct access to the CPSR. (In the ARM instruction set, the MSR and MRS instructions, and CPS in ARMv6, do this.)
A6.1.1
Entering Thumb state
Thumb execution is normally entered by executing an ARM BX instruction (Branch and Exchange). This instruction branches to the address held in a general-purpose register, and if bit[0] of that register is 1, Thumb execution begins at the branch target address. If bit[0] of the target register is 0, ARM execution continues from the branch target address. On ARMv5T and above, BLX instructions and LDR/LDM instructions that load the PC can be used similarly. Thumb execution can also be initiated by setting the T bit in the SPSR and executing an ARM instruction which restores the CPSR from the SPSR (a data-processing instruction with the S bit set and the PC as the destination, or a Load Multiple with Restore CPSR instruction). This allows an operating system to automatically restart a process independent of whether that process is executing Thumb code or ARM code. The result is UNPREDICTABLE if the T bit is altered directly by writing the CPSR.
A6-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
A6.1.2
Exceptions
Exceptions generated during Thumb execution switch to ARM execution before executing the exception handler (whose first instruction is at the hardware vector). The state of the T bit is preserved in the SPSR, and the LR of the exception mode is set so that the normal return instruction performs correctly, regardless of whether the exception occurred during ARM or Thumb execution. Table A6-1 lists the values of the exception mode LR for exceptions generated during Thumb execution. Table A6-1 Exception return instructions Exception Reset Undefined SWI Prefetch Abort Data Abort IRQ FIQ Exception link register value
UNPREDICTABLE
Return instruction MOVS PC, R14 MOVS PC, R14 SUBS PC, R14, #4 SUBS PC, R14, #8 SUBS PC, R14, #4 SUBS PC, R14, #4
value
Address of Undefined instruction + 2 Address of SWI instruction + 2 Address of aborted instruction fetch + 4 Address of the instruction that generated the abort + 8 Address of the next instruction to be executed + 4 Address of the next instruction to be executed + 4
Note
For each exception, the return instruction indicated by Table 6-1 is the same as the return instruction required if the exception occurred during ARM execution, for the primary or only method of return from that instruction listed in Exceptions on page A2-16. However, the following two types of exception have a secondary return method, for which different return instructions are needed depending on whether the exception occurred during ARM or Thumb execution: For the Data Abort exception, the primary method of return causes execution to resume at the aborted instruction, which causes it to be re-executed. As described in Data Abort (data access memory abort) on page A2-21, it is also possible to return to the next instruction after the aborted instruction, using a SUBS PC,R14,#4 instruction. If this type of return is required for a Data Abort caused by a Thumb instruction, use SUBS PC,R14,#6 for the return instruction. For the Undefined Instruction exception, the primary method of return causes execution to resume at the next instruction after the Undefined instruction. As described in Undefined Instruction exception on page A2-19, it is also possible to return to the Undefined instruction itself, using the instruction SUBS PC,R14,#4. If this type of return is required for a Thumb Undefined instruction, use SUBS PC,R14,#2 for the return instruction. However, the main use of this type of return is for some types of coprocessor instruction, and as the Thumb instruction set does not contain any coprocessor instructions, you are unlikely to need this secondary method of return for Thumb instructions. When these secondary methods of return are used, the exception handler code must test the SPSR T bit to determine which of the two return instructions to use.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-3
The Thumb Instruction Set
A6.2
Instruction set encoding
Figure A6-1 shows the Thumb instruction set encoding. An entry in square brackets, for example [1], indicates a note on the following page.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Shift by immediate Add/subtract register Add/subtract immediate Add/subtract/compare/move immediate Data-processing register Special data processing Branch/exchange instruction set [3] Load from literal pool Load/store register offset Load/store word/byte immediate offset Load/store halfword immediate offset Load/store to/from stack Add to SP or PC Miscellaneous: See Figure 6-2 Load/store multiple Conditional branch Undefined instruction Software interrupt Unconditional branch BLX suffix [4] Undefined instruction BL/BLX prefix BL suffix
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1
opcode [1] 1 1 1 1 0 1
immediate opc opc Rd / Rn 0 1 1 opcode opcode [1] 1 Rd opcode Rm offset offset Rd Rd x x Rn cond [2] x x x x 1 H1 L H2 H2 Rm immediate
Rm Rn Rn immediate Rm / Rs Rm Rm PC-relative offset Rn Rn Rn SP-relative offset immediate x x x
Rd Rd Rd
opcode 0 0 0 0 1 B 0 1 0 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 1 x L L L SP x L 0 0 0 1
Rd / Rn Rd / Rn SBZ
Rd Rd Rd
x
x
register list offset 0 1 offset offset 0 x x x x 1 x x x x x x x x
1 1
1 1
immediate
x
x
x
x
x offset offset
Figure A6-1 Thumb instruction set overview
A6-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
1. 2. 3. 4.
The opc field is not allowed to be 11 in this line. Other lines deal with the case that the opc field is 11. The cond field is not allowed to be 1110 or 1111 in this line. Other lines deal with the cases where the cond field is 1110 or 1111. The form with L==1 is UNPREDICTABLE prior to ARMv5T. This is an Undefined instruction prior to ARMv5T.
A6.2.1
Miscellaneous instructions
Figure A6-2 lists miscellaneous Thumb instructions. An entry in square brackets, for example [1], indicates a note below the figure.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Adjust stack pointer Sign/zero extend [2] Push/pop register list UNPREDICTABLE Set Endianness [2] Change Processor State [2] UNPREDICTABLE UNPREDICTABLE Reverse bytes [2] Software breakpoint [1]
1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
0 0 L 0 0 0 0 0 1 1
0 0 1 1 1 1 1 1 0 1
0 1 0 1 1 1 1 1 1 1
0 0 R 0 0 0 0 0 0 0
opc opc
immediate Rm register list Rd
0 0 0 0 0 opc
1 1 1 1 1
0 0 1 1 1
0 1 imod 0 1 Rn
x E 0 1 1
x
x SBZ
x
A x x
I x x Rd
F x x
immediate
Figure A6-2 Miscellaneous Thumb instructions 1. 2. This is an Undefined instruction prior to ARMv5. These are Undefined instructions prior to ARMv6.
Note
Any instruction with bits[15:12] = 1011, and which is not shown in Figure A6-2, is an Undefined instruction.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-5
The Thumb Instruction Set
A6.3
Branch instructions
Thumb supports six types of branch instruction: a conditional branch to allow forward and backward branches of up to 256 bytes (-256 to + 254) an unconditional branch that allows a forward or backward branch of up to 2KB (-2048 to +2046) a Branch with Link (subroutine call) is supported with a pair of instructions that allow forward and backward branches of up to 4MB (-222 <= offset <= +222 - 2) a Branch with Link and Exchange uses a pair of instructions, similar to Branch with Link, but additionally switches to ARM code execution. a Branch and Exchange instruction branches to an address in a register and optionally switches to ARM code execution a second form of Branch with Link and Exchange instruction performs a subroutine call to an address in a register and optionally switches to ARM code execution
The encoding for these instructions is given below.
A6.3.1
Conditional branch
B<cond> <target_address>
15
14
13
12
11
8
7
0
1
1
0
1
cond
8_bit_signed_offset
A6.3.2
Unconditional branch
B BL BLX <target_address> <target_address> <target_address> ; Produces two 16-bit instructions ; Produces two 16-bit instructions
15
14
13
12
11
10
0
1
1
1
H
offset_11
A6.3.3
Branch with exchange
BX BLX <Rm> <Rm>
15
14
13
12
11
10
9
8
7
6
5
3
2
0
0
1
0
0
0
1
1
1
L
H2
Rm
SBZ
A6-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
A6.3.4
Examples
B BCC BEQ BL func ... ... MOV BX PC, LR R12 label label label func ; unconditionally branch to label ; branch to label if carry flag is clear ; branch to label if zero flag is set ; subroutine call to function
; Include body of function here ; R15=R14, return to instruction after the BL ; branch to address in R12; begin ARM execution if ; bit 0 of R12 is zero; otherwise continue executing ; Thumb code
A6.3.5
List of branch instructions
The following instructions follow the formats shown above.
B B BL BX BLX
Conditional Branch. See B (1) on page A7-19. Unconditional Branch. See B (2) on page A7-21. Branch with Link. See BL, BLX (1) on page A7-26. Branch and Exchange instruction set. See BX on page A7-32. Branch with Link and Exchange instruction set. See BL, BLX (1) on page A7-26 and BLX (2) on page A7-30.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-7
The Thumb Instruction Set
A6.4
Data-processing instructions
Thumb data-processing instructions are a subset of the ARM data-processing instructions. They are divided into two sets. The first set can only operate on the low registers, r0-r7. The second set can operate on the high registers, r8-r15, or on a mixture of low and high registers.
A6.4.1
Low register data-processing instructions
The low register data processing instructions are shown in Table A6-2. Some of these instructions also appear in the high register data processing instruction list. When operating on low registers, all instructions in this table, except CPY, set the condition codes. Table A6-2 Low register data-processing instructions Mnemonic
ADC Rd, Rm ADD Rd, Rn, Rm ADD Rd, Rn, #0 to 7 ADD Rd, #0 to 255 AND Rd, Rm ASR Rd, Rm, #1 to 32 ASR Rd, Rs BIC Rd, Rm CMN Rn, Rm CMP Rn, #0 to 255 CMP Rn, Rm CPY Rd, Rn EOR Rd, Rm LSL Rd, Rm, #0 to 31 LSL Rd, Rs LSR Rd, Rm, #1 to 32 LSR Rd, Rs MOV Rd, #0 to 255
Operation Add with Carry Add Add Add Logical AND Arithmetic Shift Right Arithmetic Shift Right Bit Clear Compare Negated Compare Compare Copy Logical Exclusive OR Logical Shift Left Logical Shift Left Logical Shift Right Logical Shift Right Move
Action Rd := Rd + Rm + Carry flag Rd := Rn + Rm Rd := Rn + 3-bit immediate Rd := Rd + 8-bit immediate Rd := Rd AND Rm Rd := Rm ASR 5-bit immediate Rd := Rd ASR Rs Rd := Rd AND NOT Rm Update flags after Rn + Rm Update flags after Rn - 8-bit immediate Update flags after Rn - Rm Rd := Rn Rd := Rd EOR Rm Rd := Rm LSL 5-bit immediate Rd := Rd LSL Rs Rd := Rm LSR 5-bit immediate Rd := Rd LSR Rs Rd := 8-bit immediate
A6-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
Table A6-2 Low register data-processing instructions (continued) Mnemonic
MOV Rd, Rn MUL Rd, Rm MVN Rd, Rm NEG Rd, Rm ORR Rd, Rm ROR Rd, Rs SBC Rd, Rm SUB Rd, Rn, Rm SUB Rd, Rn, #0 to 7 SUB Rd, #0 to 255 TST Rn, Rm
Operation Move Multiply Move Not Negate Logical (inclusive) OR Rotate Right Subtract with Carry Subtract Subtract Subtract Test
Action Rd := Rn Rd := Rm x Rd Rd := NOT Rm Rd := 0 - Rm Rd := Rd OR Rm Rd := Rd ROR Rs Rd := Rd - Rm - NOT(Carry Flag) Rd := Rn - Rm Rd := Rn - 3-bit immediate Rd := Rd - 8-bit immediate Update flags after Rn AND Rm
For example:
ADD SUB ADD ADD NEG AND EOR CMP CMP MOV R0, R6, R0, R1, R3, R2, R1, R2, R7, R0, R4, R7 R1, R2 #255 R4, #4 R1 R5 R6 R3 #100 #200 ; ; ; ; ; ; ; ; ; ; R0 = R4 + R7 R6 = R1 - R2 R0 = R0 + 255 R1 = R4 + 4 R3 = 0 - R1 R2 = R2 AND R5 R1 = R1 EOR R6 update flags after R2 - R3 update flags after R7 - 100 R0 = 200
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-9
The Thumb Instruction Set
A6.4.2
High registers
There are eight types of data-processing instruction which operate on ARM registers 8 to 14 and the PC as shown in Table A6-3. Apart from CMP, instructions in this table do not change the condition code flags. Table A6-3 High register data-processing instructions Mnemonic
MOV Rd, Rn CPY Rd, Rn ADD Rd, Rm CMP Rn, Rm ADD SP, #0 to 508 SUB SP, #0 to 508 ADD Rd, SP, #0 to 1020 ADD Rd, PC, #0 to 1020
Operation Move Copy Add Compare Increment stack pointer Decrement stack pointer Form Stack address Form PC address
Action Rd := Rn Rd := Rn Rd := Rd + Rm Update flags after Rn - Rm R13 = R13 + 4* (7-bit immediate) R13 = R13 - 4* (7-bit immediate) Rd = R13 + 4* (8-bit immediate) Rd = PC + 4* (8-bit immediate)
For example:
MOV ADD MOV CMP SUB ADD ADD ADD R0, R12 R10, R1 PC, LR R10, R11 SP, #12 SP, #16 R2, SP, #20 R0, PC, #500 ; ; ; ; ; ; ; ; R0 = R12 R10 = R10 + R1 PC = R14 update flags after R10 - R11 increase stack size by 12 bytes decrease stack size by 16 bytes R2 = SP + 20 R0 = PC + 500
A6-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
A6.4.3
Formats
Data-processing instructions use the following eight instruction formats:
Format 1
<opcode1> <Rd>, <Rn>, <Rm> <opcode1> := ADD | SUB
15
14
13
12
11
10
9
8
6
5
3
2
0
0
0
0
1
1
0
op_1
Rm
Rn
Rd
Format 2
<opcode2> <Rd>, <Rn>, #<3_bit_immed> <opcode2> := ADD | SUB
15
14
13
12
11
10
9
8
6
5
3
2
0
0
0
0
1
1
1
op_2 3_bit_immediate
Rn
Rd
Format 3
<opcode3> <Rd>|<Rn>, #<8_bit_immed> <opcode3> := ADD | SUB | MOV | CMP
15
14
13
12
11
10
8
7
0
0
0
1
op_3
Rd|Rn
8_bit_immediate
Format 4
<opcode4> <Rd>, <Rm>, #<shift_imm> <opcode4> := LSL | LSR | ASR
15
14
13
12
11
10
6
5
3
2
0
0
0
0
op_4
shift_immediate
Rm
Rd
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-11
The Thumb Instruction Set
Format 5
<opcode5> <Rd>|<Rn>, <Rm>|<Rs> <opcode5> := MVN | CMP | CMN | TST | ADC | SBC | NEG | MUL | LSL | LSR | ASR | ROR | AND | EOR | ORR | BIC
15
14
13
12
11
10
9
6
5
3
2
0
0
1
0
0
0
0
op_5
Rm|Rs
Rd|Rn
Format 6
ADD <Rd>, <reg>, #<8_bit_immed> <reg> := SP | PC
15
14
13
12
11
10
8
7
0
1
0
1
0
reg
Rd
8_bit_immediate
Format 7
<opcode6> SP, SP, #<7_bit_immed> <opcode6> := ADD | SUB
15
14
13
12
11
10
9
8
7
6
0
1
0
1
1
0
0
0
0
op_6
7_bit_immediate
Format 8
<opcode7> <Rd>|<Rn>, <Rm> <opcode7> := MOV | ADD | CMP | CPY
15
14
13
12
11
10
9
8
7
6
5
3
2
0
0
1
0
0
0
1
opcode
H1
H2
Rm
Rd|Rn
A6-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
A6.4.4
List of data-processing instructions
The following instructions follow the formats shown above.
ADC ADD ADD ADD ADD ADD ADD ADD AND ASR ASR BIC CMN CMP CMP CMP CPY EOR LSL LSL LSR LSR MOV MOV MOV MUL
Add with Carry. See ADC on page A7-4. Add (immediate). See ADD (1) on page A7-5. Add (large immediate). See ADD (2) on page A7-6. Add (register). See ADD (3) on page A7-7. Add high registers. See ADD (4) on page A7-8. Add (immediate to program counter). See ADD (5) on page A7-10. Add (immediate to stack pointer). See ADD (6) on page A7-11. Increment stack pointer. See ADD (7) on page A7-12. Logical AND. See AND on page A7-14. Arithmetic Shift Right (immediate). See ASR (1) on page A7-15. Arithmetic Shift Right (register). See ASR (2) on page A7-17. Bit Clear. See BIC on page A7-23. Compare Negative (register). See CMN on page A7-34. Compare (immediate). See CMP (1) on page A7-35. Compare (register). See CMP (2) on page A7-36. Compare high registers. See CMP (3) on page A7-37. Copy high or low registers. See CPY on page A7-41. Exclusive OR. See EOR on page A7-43. Logical Shift Left (immediate). See LSL (1) on page A7-64. Logical Shift Left (register). See LSL (2) on page A7-66. Logical Shift Right (immediate). See LSR (1) on page A7-68. Logical Shift Right (register). See LSR (2) on page A7-70. Move (immediate). See MOV (1) on page A7-72. Move a low register to another low register. See MOV (2) on page A7-73. Move high registers. See MOV (3) on page A7-75. Multiply. See MUL on page A7-77.
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. A6-13
ARM DDI 0100I
The Thumb Instruction Set
MVN NEG ORR ROR SBC SUB SUB SUB SUB TST
Move NOT (register). See MVN on page A7-79. Negate (register). See NEG on page A7-80. Logical OR. See ORR on page A7-81. Rotate Right (register). See ROR on page A7-92. Subtract with Carry (register). See SBC on page A7-94. Subtract (immediate). See SUB (1) on page A7-113. Subtract (large immediate). See SUB (2) on page A7-114. Subtract (register). See SUB (3) on page A7-115. Decrement stack pointer. See SUB (4) on page A7-116. Test (register). See TST on page A7-122.
A6-14
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
A6.5
Load and Store Register instructions
Thumb supports eight types of Load and Store Register instructions. Two basic addressing modes are available. These allow the load and store of words, halfwords and bytes, and also the load of signed halfwords and bytes: register plus register register plus 5-bit immediate (not available for signed halfword and signed byte loads). If an immediate offset is used, it is scaled by 4 for word access and 2 for halfword accesses. In addition, three special instructions allow: words to be loaded using the PC as a base with a 1KB (word-aligned) immediate offset words to be loaded and stored with the stack pointer (R13) as the base and a 1KB (word-aligned) immediate offset.
A6.5.1
Formats
Load and Store Register instructions have the following formats:
Format 1
<opcode1> <Rd>, [<Rn>, #<5_bit_offset>] <opcode1> := LDR|LDRH|LDRB|STR|STRH|STRB
15
11
10
6
5
3
2
0
opcode1
5_bit_offset
Rn
Rd
Format 2
<opcode2> <Rd>, [<Rn>, <Rm>] <opcode2> := LDR|LDRH|LDRSH|LDRB|LDRSB|STR|STRH|STRB
15
9
8
6
5
3
2
0
opcode2
Rm
Rn
Rd
Format 3
LDR <Rd>, [PC, #<8_bit_offset>]
15
14
13
12
11
10
8
7
0
0
1
0
0
1
Rd
8_bit_immediate
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-15
The Thumb Instruction Set
Format 4
<opcode3> <opcode3> <Rd>, [SP, #<8_bit_offset>] := LDR | STR
15
14
13
12
11
10
8
7
0
1
0
0
1
L
Rd
8_bit_immediate
For example:
LDR LDR STR STRB STRH LDRH LDRB LDR LDR STR R4, R4, R0, R1, R4, R3, R2, R6, R5, R4, [R2, [R2, [R7, [R5, [R2, [R6, [R1, [PC, [SP, [SP, #4] R1] #0x7C] #31] R3] R5] #5] #0x3FC] #64] #0x260] ; ; ; ; ; ; ; ; ; ; Load word into R4 from address R2 + 4 Load word into R4 from address R2 + R1 Store word from R0 to address R7 + 124 Store byte from R1 to address R5 + 31 Store halfword from R4 to R2 + R3 Load word into R3 from R6 + R5 Load byte into R2 from R1 + 5 Load R6 from PC + 0x3FC Load R5 from SP + 64 Load R5 from SP + 0x260
A6-16
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
A6.5.2
List of Load and Store Register instructions
The following instructions follow the formats shown above.
LDR LDR LDR LDR LDRB LDRB LDRH LDRH LDRSB LDRSH STR STR STR STRB STRB STRH STRH
Load Word (immediate offset). See LDR (1) on page A7-47. Load Word (register offset). See LDR (2) on page A7-49. Load Word (PC-relative). See LDR (3) on page A7-51. Load Word (SP-relative). See LDR (4) on page A7-53. Load Unsigned Byte (immediate offset). See LDRB (1) on page A7-55. Load Unsigned Byte (register offset). See LDRB (2) on page A7-56. Load Unsigned Halfword (immediate offset). See LDRH (1) on page A7-57. Load Unsigned Halfword (register offset). See LDRH (2) on page A7-59. Load Signed Byte (register offset). See LDRSB on page A7-61. Load Signed Halfword (register offset). See LDRSH on page A7-62. Store Word (immediate offset). See STR (1) on page A7-99. Store Word (register offset). See STR (2) on page A7-101. Store Word (SP-relative). See STR (3) on page A7-103. Store Byte (immediate offset). See STRB (1) on page A7-105. Store Byte (register offset). See STRB (2) on page A7-107. Store Halfword (immediate offset). See STRH (1) on page A7-109. Store Halfword (register offset). See STRH (2) on page A7-111.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-17
The Thumb Instruction Set
A6.6
Load and Store Multiple instructions
Thumb supports four types of Load and Store Multiple instructions: Two instructions, LDMIA and STMIA, are designed to support block copy. They have a fixed Increment After addressing mode from a base register. The other two instructions, PUSH and POP, also have a fixed addressing mode. They implement a full descending stack and the stack pointer (R13) is used as the base register.
All four instructions update the base register after transfer and all can transfer any or all of the lower 8 registers. PUSH can also stack the return address, and POP can load the PC.
A6.6.1
Formats
Load and Store Multiple instructions have the following formats:
Format 1
<opcode1> <opcode1> <Rn>!, <registers> := LDMIA | STMIA
15
14
13
12
11
10
8
7
0
1
1
0
0
L
Rn
register_list
Format 2
PUSH POP {<registers>} {<registers>}
15
14
13
12
11
10
9
8
7
0
1
0
1
1
L
1
0
R
register_list
A6.6.2
Examples
LDMIA STMIA function PUSH ... ... POP {R0-R7, PC} R7!, {R0-R3, R5} R0!, {R3, R4, R5} ; Load R0 to R3-R5 from R7, add 20 to R7 ; Store R3-R5 to R0: add 12 to R0
{R0-R7, LR}
; push onto the stack (R13) R0-R7 and ; the return address ; code of the function body ; restore R0-R7 from the stack ; and the program counter, and return
A6-18
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
A6.6.3
List of Load and Store Multiple instructions
The following instructions follow the formats shown above.
LDMIA POP PUSH STMIA
Load Multiple. See LDMIA on page A7-44. Pop Multiple. See POP on page A7-82. Push Multiple. See PUSH on page A7-85. Store Multiple. See STMIA on page A7-96.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-19
The Thumb Instruction Set
A6.7
Exception-generating instructions
The Thumb instruction set provides two types of instruction whose main purpose is to cause a processor exception to occur: The Software Interrupt (SWI) instruction is used to cause a SWI exception to occur (see Software Interrupt exception on page A2-20). This is the main mechanism in the Thumb instruction set by which User mode code can make calls to privileged Operating System code. The Breakpoint (BKPT) instruction is used for software breakpoints in ARMv5T and above. Its default behavior is to cause a Prefetch Abort exception to occur (see Prefetch Abort (instruction fetch memory abort) on page A2-20). A debug monitor program that has previously been installed on the Prefetch Abort vector can handle this exception. If debug hardware is present in the system, it is allowed to override this default behavior. See Notes in BKPT on page A7-24 for more details.
A6.7.1
Instruction encodings
SWI <immed_8>
15
14
13
12
11
10
9
8
7
0
1
1
0
1
1
1
1
1
immed_8
BKPT
<immed_8>
15
14
13
12
11
10
9
8
7
0
1
0
1
1
1
1
1
0
immed_8
In both SWI and BKPT, the immed_8 field of the instruction is ignored by the ARM processor. The SWI or Prefetch Abort handler can optionally be written to load the instruction that caused the exception and extract these fields. This allows them to be used to communicate extra information about the Operating System call or breakpoint to the handler.
A6.7.2
List of exception-generating instructions
BKPT SWI
Breakpoint. See BKPT on page A7-24. Software Interrupt. See SWI on page A7-118.
A6-20
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The Thumb Instruction Set
A6.8
Undefined Instruction space
The following instructions are UNDEFINED in the Thumb instruction set:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1
0 0 0 0 0 0 1
1 1 1 1 1 1 0
1 1 1 1 1 1 1
0 0 1 1 1 1 1
0 x 0 0 0 1 1
0 1 0 1 1 1 1
1 1 x 0 1 1 0
x x x 1 x x x
x x x 0 x x x
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
In general, these instructions can be used to extend the Thumb instruction set in the future. However, it is intended that the following group of instructions will not be used in this manner:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
1
0
1
1
1
1
0
x
x
x
x
x
x
x
x
Use one of these instructions if you want to use an Undefined instruction for software purposes, with minimal risk that future hardware will treat it as a defined instruction.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A6-21
The Thumb Instruction Set
A6-22
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Chapter A7 Thumb Instructions
This chapter describes the syntax and usage of every Thumb instruction, in the sections: Alphabetical list of Thumb instructions on page A7-2 Thumb instructions and architecture versions on page A7-125.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-1
Thumb Instructions
A7.1
Alphabetical list of Thumb instructions
Every Thumb instruction is listed on the following pages. Each instruction description shows: the instruction encoding the instruction syntax the versions of the ARM architecture where the instruction is valid any exceptions that might apply a pseudo-code specification of how the instruction operates notes on usage and special cases the equivalent ARM instruction encoding.
A7.1.1
General notes
These notes explain the types of information and abbreviations used on the instruction pages.
Syntax abbreviations
The following abbreviations are used in the instruction pages:
immed_<n>
This is an <n>-bit immediate value. For example, an 8-bit immediate value is represented by:
immed_8
signed_immed_<n>
This is a signed immediate. For example, an 8-bit signed immediate is represented by:
signed_immed_8
Architecture version
For the convenience of the reader, this section describes the version of the ARM architecture that the instruction is associated with, not the version of the Thumb instruction set. There have been three versions of the Thumb instruction set architecture to date: THUMBv1 THUMBv2 THUMBv3 This is used in T variants of version 4 of the ARM instruction set architecture. This is used in T variants of version 5 of the ARM instruction set architecture. This is used in version 6 and above of the ARM instruction set architecture.
Instructions which are described as being in all T variants are therefore present in THUMBv1, THUMBv2, and THUMBv3. and those that are described as being in T variants of version 6 and above are in THUMBv3 only.
A7-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
This section shows the syntax and encoding of an equivalent ARM instruction. When no precise equivalent is available, a close equivalent is shown and the reasons why it is not a precise equivalent are explained. A common reason for the instruction not being a precise equivalent is that it reads the value of the PC. This produces the instruction's own address plus N, where N is 8 for ARM instructions and 4 for Thumb instructions. This difference can often be compensated for by adjusting an immediate constant in the equivalent ARM instruction. In the equivalent instruction encodings, named fields and bits must be filled in with the corresponding fields and bits from the Thumb instruction, or in a few cases with values derived from the Thumb instruction as described in the text. The ARM instruction fields are normally the same length as the corresponding Thumb instruction fields, with one important exception. Thumb register fields are normally 3 bits long, whereas ARM register fields are normally 4 bits long. In these cases, the Thumb register field must be extended with a high-order 0 when substituted into the ARM register field, so that the ARM instruction refers to the correct one of R0 to R7.
Information on usage
Usage information is only given for Thumb instructions where it differs significantly from ARM instruction usage. If no Usage section appears for a Thumb instruction, see the equivalent ARM instruction page in Chapter A4 ARM Instructions for usage information.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-3
Thumb Instructions
A7.1.2
ADC
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
0
1
0
1
Rm
Rd
ADC (Add with Carry) adds two values and the Carry flag.
Use ADC to synthesize multi-word addition.
ADC updates the condition code flags, based on the result.
Syntax
ADC <Rd>, <Rm>
where:
<Rd> <Rm>
Holds the first value for the addition, and is the destination register for the operation. Specifies the register that contains the second operand for the addition.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rd + Rm + C Flag N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = CarryFrom(Rd + Rm + C Flag) V Flag = OverflowFrom(Rd + Rm + C Flag)
Equivalent ARM syntax and encoding
ADCS <Rd>, <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111000001011
Rd
Rd
00000000
Rm
A7-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.3
ADD (1)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
0
0
1
1
1
0
immed_3
Rn
Rd
ADD (1) adds a small constant value to the value of a register and stores the result in a second register.
It updates the condition code flags, based on the result.
Syntax
ADD <Rd>, <Rn>, #<immed_3>
where:
<Rd> <Rn> <immed_3>
Is the destination register for the completed operation. Specifies the register that contains the operand for the addition. Specifies a 3-bit immediate value that is added to the value of <Rn>.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rn + immed_3 N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = CarryFrom(Rn + immed_3) V Flag = OverflowFrom(Rn + immed_3)
Equivalent ARM syntax and encoding
ADDS <Rd>, <Rn>, #<immed_3>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7 6 5 4
32
0
111000101001
Rn
Rd
0 0 0 0 0 0 0 0 0 immed_3
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-5
Thumb Instructions
A7.1.4
ADD (2)
15 14 13 12 11 10 8 7 0
0
0
1
1
0
Rd
immed_8
ADD (2) adds a large immediate value to the value of a register and stores the result back in the same register.
The condition code flags are updated, based on the result.
Syntax
ADD <Rd>, #<immed_8>
where:
<Rd>
Holds the first operand for the addition, and is the destination register for the completed operation. Specifies an 8-bit immediate value that is added to the value of <Rd>.
<immed_8>
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rd + immed_8 N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = CarryFrom(Rd + immed_8) V Flag = OverflowFrom(Rd + immed_8)
Equivalent ARM syntax and encoding
ADDS <Rd>, <Rd>, #<immed_8>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
7
0
111000101001
Rd
Rd
0000
immed_8
A7-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.5
ADD (3)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
0
0
1
1
0
0
Rm
Rn
Rd
ADD (3) adds the value of one register to the value of a second register, and stores the result in a third register.
It updates the condition code flags, based on the result.
Syntax
ADD <Rd>, <Rn>, <Rm>
where:
<Rd> <Rn> <Rm>
Is the destination register for the completed operation. Specifies the register containing the first value for the addition. Specifies the register containing the second value for the addition.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rn + Rm N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = CarryFrom(Rn + Rm) V Flag = OverflowFrom(Rn + Rm)
Equivalent ARM syntax and encoding
ADDS <Rd>, <Rn>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7 6 5 4
3
0
111000001001
Rn
Rd
00000000
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-7
Thumb Instructions
A7.1.6
ADD (4)
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
1
0
0
H1
H2
Rm
Rd
ADD (4) adds the values of two registers, one or both of which are high registers.
Unlike the low-register only ADD instruction (ADD (3) on page A7-7), this instruction does not change the flags.
Syntax
ADD <Rd>, <Rm>
where:
<Rd>
Specifies the register containing the first value, and is also the destination register. It can be any of R0 to R15. The register number is encoded in the instruction in H1 (most significant bit) and Rd (remaining three bits). Specifies the register containing the second value. It can be any of R0 to R15. Its number is encoded in the instruction in H2 (most significant bit) and Rm (remaining three bits).
<Rm>
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rd + Rm
Notes
Operand restriction If a low register is specified for <Rd> and Rm (H1==0 and H2==0), the result is
UNPREDICTABLE.
A7-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
A close equivalent is:
ADD <Rd>, <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18
16 15 14
12 11 10 9 8 7 6 5 4
32
0
1 1 1 0 0 0 0 0 1 0 0 0 H1
Rd
H1
Rd
0 0 0 0 0 0 0 0 H2
Rm
There are slight differences when the instruction accesses the PC, because of the different definitions of the PC when executing ARM and Thumb code.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-9
Thumb Instructions
A7.1.7
ADD (5)
15 14 13 12 11 10 8 7 0
1
0
1
0
0
Rd
immed_8
ADD (5) adds an immediate value to the PC and writes the resulting PC-relative address to a destination
register. The immediate can be any multiple of 4 in the range 0 to 1020. The condition codes are not affected.
Syntax
ADD <Rd>, PC, #<immed_8> * 4
where:
<Rd> PC <immed_8>
Is the destination register for the completed operation. Indicates PC-relative addressing. Specifies an 8-bit immediate value that is quadrupled and added to the value of the PC.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = (PC AND 0xFFFFFFFC) + (immed_8 * 4)
Equivalent ARM syntax and encoding
A close equivalent is:
ADD <Rd>, PC, #<immed_8> * 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
12 11 10 9 8
7
0
1110001010001111
Rd
1111
immed_8
The definitions of the PC differ between ARM and Thumb code. This makes a difference between the precise results of the instructions.
A7-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.8
ADD (6)
15 14 13 12 11 10 8 7 0
1
0
1
0
1
Rd
immed_8
ADD (6) adds an immediate value to the SP and writes the resulting SP-relative address to a destination
register. The immediate can be any multiple of 4 in the range 0 to 1020. The condition codes are not affected.
Syntax
ADD <Rd>, SP, #<immed_8> * 4
where:
<Rd> SP <immed_8>
Is the destination register for the completed operation. Indicates SP-relative addressing. Specifies an 8-bit immediate value that is quadrupled and added to the value of the SP.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = SP + (immed_8 << 2)
Equivalent ARM syntax and encoding
ADD <Rd>, SP, #<immed_8> * 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
12 11 10 9 8 7
0
1110001010001101
Rd
1111
immed_8
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-11
Thumb Instructions
A7.1.9
ADD (7)
15 14 13 12 11 10 9 8 7 6 0
1
0
1
1
0
0
0
0
0
immed_7
ADD (7) increments the SP by four times a 7-bit immediate (that is, by a multiple of 4 in the range 0 to 508).
The condition codes are not affected.
Syntax
ADD SP, #<immed_7> * 4
where:
SP
Contains the first operand for the addition. SP is also the destination register for the operation. Specifies the immediate value that is quadrupled and added to the value of the SP.
<immed_7>
Architecture version
All T variants.
Exceptions
None.
Operation
SP = SP + (immed_7 << 2)
Usage
For the Full Descending stack which the Thumb instruction set is designed to use, incrementing the SP is used to discard data on the top of the stack.
Notes
Alternative syntax This instruction can also be written as ADD SP, SP, #(<immed_7> * 4).
A7-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
ADD SP, SP, #<immed_7> * 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
0
1110001010001101110111110
immed_7
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-13
Thumb Instructions
A7.1.10 AND
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
0
0
0
0
Rm
Rd
AND (Logical AND) performs a bitwise AND of the values in two registers. AND updates the condition code flags, based on the result.
Syntax
AND <Rd>, <Rm>
where:
<Rd> <Rm>
Specifies the register containing the first operand, and is also the destination register. Specifies the register containing the second operand.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rd AND Rm N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = unaffected V Flag = unaffected
Equivalent ARM syntax and encoding
ANDS <Rd>, <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111000000001
Rd
Rd
00000000
Rm
A7-14
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.11 ASR (1)
15 14 13 12 11 10 6 5 3 2 0
0
0
0
1
0
immed_5
Rm
Rd
ASR (1) (Arithmetic Shift Right) provides the signed value of the contents of a register divided by a constant
power of 2. It updates the condition code flags, based on the result.
Syntax
ASR <Rd>, <Rm>, #<immed_5>
where:
<Rd> <Rm> <immed_5>
Is the destination register for the completed operation. Specifies the register that contains the value to be shifted. Specifies the shift amount, in the range 1 to 32. Shifts by 1 to 31 are encoded directly in immed_5. A shift by 32 is encoded as immed_5 == 0.
Architecture version
All T variants.
Exceptions
None.
Operation
if immed_5 == 0 C Flag = Rm[31] if Rm[31] == 0 then Rd = 0 else /* Rm[31] == 1 */] Rd = 0xFFFFFFFF else /* immed_5 > 0 */ C Flag = Rm[immed_5 - 1] Rd = Rm Arithmetic_Shift_Right immed_5 N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 V Flag = unaffected
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-15
Thumb Instructions
Equivalent ARM syntax and encoding
MOVS <Rd>, <Rm>, ASR #<immed_5>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
76543
0
111000011011
SBZ
Rd
immed_5
100
Rm
A7-16
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.12 ASR (2)
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
0
1
0
0
Rs
Rd
ASR (2) provides the signed value of the contents of a register divided by a variable power of 2.
It updates the condition code flags, based on the result.
Syntax
ASR <Rd>, <Rs>
where:
<Rd>
Contains the value to be shifted, and is also the destination register for the completed operation. Specifies the register that contains the value of the shift.
<Rs>
Architecture version
All T variants.
Exceptions
None.
Operation
if Rs[7:0] == 0 then C Flag = unaffected Rd = unaffected else if Rs[7:0] < 32 then C Flag = Rd[Rs[7:0] - 1] Rd = Rd Arithmetic_Shift_Right Rs[7:0] else /* Rs[7:0] >= 32 */ C Flag = Rd[31] if Rd[31] == 0 then Rd = 0 else /* Rd[31] == 1 */ Rd = 0xFFFFFFFF N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 V Flag = unaffected
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-17
Thumb Instructions
Equivalent ARM syntax and encoding
MOVS <Rd>, <Rd>, ASR <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
8
76543
0
111000011011
SBZ
Rd
Rs
0101
Rd
A7-18
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.13 B (1)
15 14 13 12 11 8 7 0
1
1
0
1
cond
signed_immed_8
B (1) (Branch) provides a conditional branch to a target address.
Syntax
B<cond> <target_address>
where:
<cond>
Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3.
<target_address>
Specifies the address to branch to. The branch target address is calculated by: 1. Shifting the 8-bit signed offset field of the instruction left by one bit. 2. Sign-extending the result to 32 bits. 3. Adding this to the contents of the PC (which contains the address of the branch instruction plus 4). The instruction can therefore specify a branch of 256 to +254 bytes, relative to the current value of the PC (R15).
Architecture version
All T variants.
Exceptions
None.
Operation
if ConditionPassed(cond) then PC = PC + (SignExtend(signed_immed_8) << 1)
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-19
Thumb Instructions
Usage
To calculate the correct value of signed_immed_8, the assembler (or other toolkit component) must: 1. Form the base address for the branch. This is the address of the branch instruction, plus 4. In other words, the base address is equal to the PC value read by that instruction. 2. Subtract the base address from the target address to form a byte offset. This offset is always even, because all Thumb instructions are halfword-aligned. 3. If the byte offset is outside the range -256 to +254, use an alternative code-generation strategy or produce an error as appropriate. 4. Otherwise, set the signed_immed_8 field of the instruction to the byte offset divided by 2.
Notes
Memory bounds AL condition Branching backwards past location zero and forwards over the end of the 32-bit address space is UNPREDICTABLE. If the condition field indicates AL (0b1110), the instruction is instead UNDEFINED. When an unconditional branch is required, use the unconditional Branch instruction described in B (2) on page A7-21. If the condition field indicates NV (0b1111), the instruction is a SWI instead (see SWI on page A7-118).
NV condition
Equivalent ARM syntax and encoding
A close equivalent is:
B<cond> <target_address>
31
28 27 26 25 24 23
8
7
0
cond
1010
sign extension of signed_immed_8
signed_immed_8
This differs from the Thumb instruction, because the offset in the ARM instruction is shifted left by 2 before being added to the PC, whereas the offset in the Thumb instruction is shifted left by 1. Also, the PC values read by the ARM and Thumb instructions are different.
A7-20
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.14 B (2)
15 14 13 12 11 10 0
1
1
1
0
0
signed_immed_11
B (2) provides an unconditional branch to a target address.
Syntax
B <target_address>
where:
<target_address>
Specifies the address to branch to. The branch target address is calculated by: 1. Shifting the 11-bit signed offset of the instruction left one bit. 2. Sign-extending the result to 32 bits. 3. Adding this to the contents of the PC (which contains the address of the branch instruction plus 4). The instruction can therefore specify a branch of 2048 to +2046 bytes, relative to the current value of the PC (R15).
Architecture version
All T variants.
Exceptions
None.
Operation
PC = PC + (SignExtend(signed_immed_11) << 1)
Usage
To calculate the correct value of signed_immed_11, the assembler (or other toolkit component) must: 1. Form the base address for the branch. This is the address of the branch instruction, plus 4. In other words, the base address is equal to the PC value read by that instruction. 2. Subtract the base address from the target address to form a byte offset. This offset is always even, because all Thumb instructions are halfword-aligned. 3. If the byte offset is outside the range -2048 to +2046, use an alternative code-generation strategy or produce an error as appropriate. 4. Otherwise, set the signed_immed_11 field of the instruction to the byte offset divided by 2.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-21
Thumb Instructions
Notes
Memory bounds Branching backwards past location zero and forwards over the end of the 32-bit address space is UNPREDICTABLE.
Equivalent ARM syntax and encoding
A close equivalent is:
B <target_address>
31
28 27 26 25 24 23
11 10
0
11101010
sign extension of signed_immed_11
signed_immed_11
This differs from the Thumb instruction, because the offset in the ARM instruction is shifted left by 2 before being added to the PC, whereas the offset in the Thumb instruction is shifted left by 1. Also, the PC values read by the ARM and Thumb instructions are different.
A7-22
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.15 BIC
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
1
1
1
0
Rm
Rd
BIC (Bit Clear) performs a bitwise AND of the value of one register and the bitwise inverse of the value of another register. BIC updates the condition code flags, based on the result.
Syntax
BIC <Rd>, <Rm>
where:
<Rd>
Is the register containing the value to be ANDed, and is also the destination register for the completed operation. Specifies the register that contains the value whose complement is ANDed with the value in
<Rd>.
<Rm>
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rd AND NOT Rm N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = unaffected V Flag = unaffected
Equivalent ARM syntax and encoding
BICS <Rd>, <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7 6 5 4
3
0
111000011101
Rd
Rd
00000000
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-23
Thumb Instructions
A7.1.16 BKPT
15 14 13 12 11 10 9 8 7 0
1
0
1
1
1
1
1
0
immed_8
BKPT (Breakpoint) causes a software breakpoint to occur. This breakpoint can be handled by an exception handler installed on the Prefetch Abort vector. In implementations which also include debug hardware, the hardware can optionally override this behavior and handle the breakpoint itself. When this occurs, the Prefetch Abort vector is not entered.
Syntax
BKPT <immed_8>
where:
<immed_8>
Is an 8-bit immediate value, which is placed in bits[7:0] of the instruction. This value is ignored by the ARM hardware, but can be used by a debugger to store additional information about the breakpoint.
Architecture version
T variants of ARMv5 and above.
Exceptions
Prefetch Abort.
Operation
if (not overridden by debug hardware) R14_abt = address of BKPT instruction + 4 SPSR_abt = CPSR CPSR[4:0] = 0b10111 /* Enter Abort mode */ CPSR[5] =0 /* Execute in ARM state */ /* CPSR[6] is unchanged */ CPSR[7] =1 /* Disable normal interrupts */ CPSR[8] = 1 /* Disable imprecise aborts - v6 only*/ CPSR[9] = CP15_reg1_EEbit if high vectors configured then PC = 0xFFFF000C else PC = 0x0000000C
A7-24
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Usage
The exact usage of BKPT depends on the debug system being used. A debug system can use BKPT in two ways: Debug hardware (if present) does not override the normal behavior of BKPT, and so the Prefetch Abort vector is entered. If the system also allows real Prefetch Aborts to occur, the Prefetch Abort handler determines (in a system-dependent manner) whether the vector entry occurred as a result of a BKPT instruction or as a result of a real Prefetch Abort, and branches to debug code or Prefetch Abort code accordingly. Otherwise, the Prefetch Abort handler just branches straight to debug code. When used in this manner, BKPT must be avoided within abort handlers, as it corrupts R14_abt and SPSR_abt. For the same reason, it must also be avoided within FIQ handlers, as an FIQ interrupt can occur within an abort handler. Debug hardware overrides the normal behavior of BKPT and handles the software breakpoint itself. When finished, it typically either resumes execution at the instruction following the BKPT, or replaces it with another instruction and resumes execution at that instruction. When BKPT is used in this manner, R14_abt and SPSR_abt are not corrupted, and so the above restrictions about its use in abort and FIQ handlers do not apply.
Notes
Hardware override Debug hardware in an implementation is specifically permitted to override the normal behavior of BKPT. Because of this, software must not use this instruction for purposes other than those permitted by the debug system being used (if any). In particular, software cannot rely on the Prefetch Abort exception occurring, unless either there is guaranteed to be no debug hardware in the system or the debug system specifies that it occurs. For ARMv6, the Debug Status and Control Register (DSCR) provides a debug hardware enable bit, and Method of Entry status field indicating when a BKPT instruction is executed; see Register 1, Debug Status and Control Register (DSCR) on page D3-10.
Equivalent ARM syntax and encoding
BKPT <immed_8>
31 30 29 28 27 26 25 24 23 22 21 10 19 18 17 6 15 14 13 12 11
87
4
3
0
11100001001000000000
immed_8 [7:4]
0111
immed_8 [3:0]
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-25
Thumb Instructions
A7.1.17 BL, BLX (1)
15 14 13 12 11 10 0
1
1
1
H
offset_11
BL (Branch with Link) provides an unconditional subroutine call to another Thumb routine. The return from
subroutine is typically performed by one of the following: MOV PC,LR BX LR a POP instruction that loads the PC.
BLX (1) (Branch with Link and Exchange) provides an unconditional subroutine call to an ARM routine. The return from subroutine is typically performed by a BX LR instruction, or an LDR or LDM instruction that loads
the PC. To allow for a reasonably large offset to the target subroutine, the BL or BLX instruction is automatically translated by the assembler into a sequence of two 16-bit Thumb instructions: The first Thumb instruction has H == 10 and supplies the high part of the branch offset. This instruction sets up for the subroutine call and is shared between the BL and BLX forms. The second Thumb instruction has H == 11 (for BL) or H == 01 (for BLX). It supplies the low part of the branch offset and causes the subroutine call to take place.
Syntax
BL BLX <target_addr> <target_addr>
where:
<target_addr>
Specifies the address to branch to. The branch target address is calculated by: 1. Shifting the offset_11 field of the first instruction left twelve bits. 2. Sign-extending the result to 32 bits. 3. Adding this to the contents of the PC (which contains the address of the first instruction plus 4). 4. Adding twice the offset_11 field of the second instruction. For BLX, the resulting address is forced to be word-aligned by clearing bit[1]. The instruction can therefore specify a branch of approximately 4MB, see Usage on page A7-27 for the exact range.
Architecture version
BL (H == 10 and H == 11 forms) is in all T variants. BLX (H == 01 form) is in T variants of ARMv5 and above.
A7-26
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Exceptions
None.
Operation
if H == 10 then LR = PC + (SignExtend(offset_11) << 12) else if H == 11 then PC = LR + (offset_11 << 1) LR = (address of next instruction) | 1 else if H == 01 then PC = (LR + (offset_11 << 1)) AND 0xFFFFFFFC LR = (address of next instruction) | 1 CPSR T bit = 0
Usage
To generate the correct pair of instructions, the assembler (or other toolkit component) must first generate the branch offset, as follows: 1. Form the base address for the branch. This is the address of the first of the two Thumb instructions (the one with H == 10), plus 4. In other words, the base address is equal to the PC value read by that instruction. 2. If the instruction is BLX, set bit[1] of the target address to be equal to bit[1] of the base address. This is an exception to the normal rule that bits[1:0] of the address of an ARM instruction are 0b00. This adjustment is required to ensure that the restrictions associated with the H == 01 form of the instruction are obeyed. 3. Subtract the base address from the target address to form the offset. The resulting offset is always even. If the offset lies outside the range:
-222 <= offset <= +222 - 2
the target address lies outside the addressing range of these instructions. This results in alternative code or an error, as appropriate. If the offset is in range, a sequence of two Thumb instructions must be generated, both using the above form: The first with H == 10 and offset_11 = offset[22:12]. The second with H == 11 (for BL) or H== 01 (for BLX) and offset_11 = offset[11:1].
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-27
Thumb Instructions
Notes
Encoding Bit[0] for BLX If H == 00, the instruction is an unconditional branch instruction instead (see the Thumb instruction B (2) on page A7-21). If H == 01, then bit[0] of the instruction must be zero, or the instruction is The offset calculation method described in Usage above ensures that the offset calculated for a BLX instruction is a multiple of four, and that this restriction is obeyed.
UNDEFINED.
Memory bounds Instruction pairs
Branching backwards past location zero and forwards over the end of the 32-bit address space is UNPREDICTABLE. These Thumb instructions must always occur in the pairs described above. Specifically: If a Thumb instruction at address A is the H==10 form of this instruction, the Thumb instruction at address A+2 must be either the H==01 or the H==11 form of this instruction. If a Thumb instruction at address A is either the H==01 or the H==11 form of this instruction, the Thumb instruction at address A-2 must be the H==10 form of this instruction.
Also, except as noted below under Exceptions, the second instruction of the pair must not be the target of any branch, whether as the result of a branch instruction or of some other instruction that changes the PC. Failure to adhere to any of these restrictions can result in UNPREDICTABLE behavior. Exceptions It is IMPLEMENTATION DEFINED whether processor exceptions can occur between the two instructions of a BL or BLX pair. If they can, the ARM instructions designed for use for exception returns must be capable of returning correctly to the second instruction of the pair. So, exception handlers need take no special precautions about returning to the second instruction of a BL or BLX pair.
A7-28
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
Close equivalents to these instruction pairs are as follows. To call a Thumb subroutine:
BLX <target_addr>
31 30 29 28 27 26 25 24 23 22 21 20
0
1 1 1 1 1 0 1 L offset sign
offset[22:2]
where L == offset[1]. To call an ARM routine:
BL <target_addr>
31 30 29 28 27 26 25 24 23 22 21 20
0
1 1 1 0 1 0 1 1 offset sign
offset[22:2]
These differ slightly from the Thumb instruction pairs because of the different values of the PC in ARM and Thumb code. This can be compensated for by adjusting the offset by 4.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-29
Thumb Instructions
A7.1.18 BLX (2)
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
1
1
1
1
H2
Rm
SBZ
BLX (2) calls an ARM or Thumb subroutine from the Thumb instruction set, at an address specified in a
register. This instruction branches and selects the instruction decoder to use to decode the instructions at the branch destination. The CPSR T bit is updated with bit[0] of the value of register Rm. To return from the subroutine to the caller, use BX R14.
Syntax
BLX <Rm>
where:
<Rm>
Is the register that contains the branch target address. It can be any of R0 to R14. The register number is encoded in the instruction in H2 (most significant bit) and Rm (remaining three bits). If R15 is specified for <Rm>, the results are UNPREDICTABLE.
Architecture version
T variants of ARMv5 and above.
Exceptions
None.
Operation
target = Rm LR = (address of the instruction after this BLX) | 1 CPSR T bit = target[0] PC = target AND 0xFFFFFFFE
Notes
Encoding Bit 7 is the H1 bit for some of the other instructions that access the high registers. If it is 0 for this instruction, rather than 1 as shown, the instruction is a BX instruction instead (see BX on page A7-32).
ARM/Thumb state transfers If Rm[1:0] == 0b10, the result is UNPREDICTABLE, as branches to non word-aligned addresses are impossible in ARM state.
A7-30
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
BLX <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
87654
32
0
111000010010
SBO
SBO
SBO
0 0 1 1 H2
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-31
Thumb Instructions
A7.1.19 BX
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
1
1
1
0
H2
Rm
SBZ
BX (Branch and Exchange) branches between ARM code and Thumb code.
Syntax
BX <Rm>
where:
<Rm>
Is the register that contains the branch target address. It can be any of R0 to R15. The register number is encoded in the instruction in H2 (most significant bit) and Rm (remaining three bits).
Architecture version
All T variants.
Exceptions
None.
Operation
CPSR T bit = Rm[0] PC = Rm[31:1] << 1
Usage
The normal subroutine return instruction in Thumb code is BX R14. The following subroutine call instructions leave a suitable return value in R14: ARM BLX instructions (See BLX (1) on page A4-16 and BLX (2) on page A4-18) Thumb BL and BLX instructions (see BL, BLX (1) on page A7-26 and BLX (2) on page A7-30).
In T variants of ARMv4, a subroutine call to an ARM routine can be performed by a code sequence of the form:
<Put address of routine to call in Ra> MOV LR,PC ; Return to second following instruction BX Ra
In T variants of ARM architecture 5 and above, a subroutine call to an ARM routine can be performed more efficiently with a BLX instruction (see BL, BLX (1) on page A7-26 and BLX (2) on page A7-30).
A7-32
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Notes
Encoding Bit 7 is the H1 bit for some of the other instructions that access the high registers. If it is 1 for this instruction, rather than 0 as shown, the instruction is: a BLX instruction instead in ARMv5 and above (see BLX (2) on page A7-30)
UNPREDICTABLE
prior to ARMv5.
ARM/Thumb state transfers If Rm[1:0] == 0b10, the result is UNPREDICTABLE, as branches to non word-aligned addresses are impossible in ARM state. Use of R15 Register 15 can be specified for <Rm>. If this is done, R15 is read as normal for Thumb code, that is, it is the address of the BX instruction itself plus 4. If the BX instruction is at a word-aligned address, this results in a branch to the next word, executing in ARM state. However, if the BX instruction is not at a word-aligned address, this means that the results of the instruction are UNPREDICTABLE (because the value read for R15 has bits[1:0]==0b10).
Equivalent ARM syntax and encoding
A close equivalent is:
BX <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
87654
3
0
111000010010
SBO
SBO
SBO
0 0 0 1 H2
Rm
This ARM instruction is not quite equivalent to the Thumb instruction, because their specified behavior differs when <Rm> is R15.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-33
Thumb Instructions
A7.1.20 CMN
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
1
0
1
1
Rm
Rn
CMN (Compare Negative) compares a register value with the negation of another register value. The condition
flags are updated, based on the result of adding the two register values, so that subsequent instructions can be conditionally executed (using a conditional branch).
Syntax
CMN <Rn>, <Rm>
where:
<Rn> <Rm>
Is the register containing the first value for comparison. Is the register containing the second value for comparison.
Architecture version
All T variants.
Exceptions
None.
Operation
alu_out = Rn + Rm N Flag = alu_out[31] Z Flag = if alu_out == 0 then 1 else 0 C Flag = CarryFrom(Rn + Rm) V Flag = OverflowFrom(Rn + Rm)
Equivalent ARM syntax and encoding
CMN <Rn>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111000010111
Rn
SBZ
00000000
Rm
A7-34
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.21 CMP (1)
15 14 13 12 11 10 8 7 0
0
0
1
0
1
Rn
immed_8
CMP (1) (Compare) compares a register value with a large immediate value. The condition flags are updated, based on the result of subtracting the constant from the register value, so that subsequent instructions can be conditionally executed (using a conditional branch).
Syntax
CMP <Rn>, #<immed_8>
where:
<Rn> <immed_8>
Is the register containing the first value for comparison. Is the 8-bit second value for comparison.
Architecture version
All T variants.
Exceptions
None.
Operation
alu_out = Rn - immed_8 N Flag = alu_out[31] Z Flag = if alu_out == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rn - immed_8) V Flag = OverflowFrom(Rn - immed_8)
Equivalent ARM syntax and encoding
CMP <Rn>, #<immed_8>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7
0
111000110101
Rn
SBZ
0000
immed_8
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-35
Thumb Instructions
A7.1.22 CMP (2)
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
1
0
1
0
Rm
Rn
CMP (2) compares two register values. The condition code flags are updated, based on the result of subtracting the second register value from the first, so that subsequent instructions can be conditionally executed (using a conditional branch).
Syntax
CMP <Rn>, <Rm>
where:
<Rn> <Rm>
Is the register containing the first value for comparison. Is the register containing the second value for comparison.
Architecture version
All T variants.
Exceptions
None.
Operation
alu_out = Rn - Rm N Flag = alu_out[31] Z Flag = if alu_out == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rn - Rm) V Flag = OverflowFrom(Rn - Rm)
Equivalent ARM syntax and encoding
CMP <Rn>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111000010101
Rn
SBZ
00000000
Rm
A7-36
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.23 CMP (3)
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
1
0
1
H1
H2
Rm
Rn
CMP (3) compares the values of two registers, one or both of which are high registers. The condition flags are updated, based on the result of subtracting the second register value from the first, so that subsequent instructions can be conditionally executed (using a conditional branch).
Syntax
CMP <Rn>, <Rm>
where:
<Rn>
Is the register containing the first value. It can be any of R0 to R14. Its number is encoded in the instruction in H1 (most significant bit) and Rn (remaining three bits). If H1 == 1 and Rn == 0b1111, apparently encoding R15, the results of the instruction are UNPREDICTABLE. Is the register containing the second value. It can be any of R0 to R15. Its number is encoded in the instruction in H2 (most significant bit) and Rm (remaining three bits).
<Rm>
Architecture version
All T variants.
Exceptions
None.
Operation
alu_out = Rn - Rm N Flag = alu_out[31] Z Flag = if alu_out == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rn - Rm) V Flag = OverflowFrom(Rn - Rm)
Notes
Operand restriction If a low register is specified for both <Rn> and <Rm> (H1==0 and H2==0), the result is UNPREDICTABLE.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-37
Thumb Instructions
Equivalent ARM syntax and encoding
A close equivalent is:
CMP <Rn>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18
16 15
12 11 10 9 8
765432
0
1 1 1 0 0 0 0 1 0 1 0 1 H1
Rn
SBZ
0 0 0 0 0 0 0 0 H2
Rm
There are slight differences when the instruction accesses the PC, because of the different definitions of the PC when executing ARM and Thumb code.
A7-38
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.24 CPS
15 12 11 10 9 8 7 6 5 4 3 2 1 0
1
0
1
1
0
1
1
0
0
1
1
imod
0
A
I
F
CPS (Change Processor State) changes one or more of the A, I, and F bits of the CPSR, without changing
other CPSR bits.
Syntax
CPS<effect> <iflags>
where:
<effect>
Specifies what effect is wanted on the interrupt disable bits A, I, and F in the CPSR. This is either:
IE ID
Interrupt Enable, encoded by imod == 0b0. This sets the specified bits to 0. Interrupt Disable, encoded by imod == 0b1. This sets the specified bits to 1.
<iflags>
Is a sequence of one or more of the following, specifying which interrupt disable flags are affected:
a i f
Sets the A bit (bit[2]), causing the specified effect on the CPSR A bit. Sets the I bit (bit[1]), causing the specified effect on the CPSR I bit. Sets the F bit (bit[0]), causing the specified effect on the CPSR F bit.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
if InAPrivilegedMode() then if A == 1 then CPSR[8] = imod if I == 1 then CPSR[7] = imod if F == 1 then CPSR[6] = imod /* else no change to interrupt disable bits */
Notes
User mode This instruction has no effect in User mode.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-39
Thumb Instructions
Equivalent ARM syntax and encoding
CPS <effect>, <flags>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
98
765
4
0
1 1 1 1 0 0 0 1 0 0 0 0 imoda 0 0
SBZ
AIF0
SBZ
a. imod is strictly a 2-bit field in the ARM syntax, with the most significant bit set (bit[19] ==1).
A7-40
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.25 CPY
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
1
1
0
H1
H2
Rm
Rd
CPY (Copy) moves a value from one high or low register to another high or low register, without changing
the flags.
Syntax
CPY <Rd>, <Rm>
where:
<Rd>
Is the destination register for the operation. It can be any of R0 to R15, and its number is encoded in the instruction in H1 (most significant bit) and Rd (remaining three bits). Is the register containing the value to be copied. It can be any of R0 to R15, and its number is encoded in the instruction in H2 (most significant bit) and Rm (remaining three bits).
<Rm>
Architecture version
T variants of ARMv6 and above.
Exceptions
None.
Operation
Rd = Rm
Usage
CPY PC,R14 can be used as a subroutine return instruction if it is known that the caller is also a Thumb routine. However, it is more usual to use BX R14 (see BX on page A7-32), which works regardless of whether the caller is an ARM routine or a Thumb routine.
Notes
Encoding
CPY has the same functionality as MOV (3) on page A7-75, and uses the same instruction
encoding, but has an assembler syntax that allows both operands to be low registers.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-41
Thumb Instructions
Equivalent ARM syntax and encoding
A close equivalent is:
CPY <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15 14
12 11 10 9 8
765432
0
111000011010
SBZ
H1
Rd
0 0 0 0 0 0 0 0 H2
Rm
There are slight differences when the instruction accesses the PC, because of the different definitions of the PC when executing ARM and Thumb code.
A7-42
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.26 EOR
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
0
0
0
1
Rm
Rd
EOR (Exclusive OR) performs a bitwise EOR of the values from two registers. EOR updates the condition code flags, based on the result.
Syntax
EOR <Rd>, <Rm>
where:
<Rd> <Rm>
Specifies the register containing the first operand, and is also the destination register. Specifies the register containing the second operand.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rd EOR Rm N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = unaffected V Flag = unaffected
Equivalent ARM syntax and encoding
EORS <Rd>, <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7 6 5 4
3
0
111000000011
Rd
Rd
00000000
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-43
Thumb Instructions
A7.1.27 LDMIA
15 14 13 12 11 10 8 7 0
1
1
0
0
1
Rn
register_list
LDMIA (Load Multiple Increment After) loads a non-empty subset, or possibly all, of the general-purpose
registers R0 to R7 from sequential memory locations.
Syntax
LDMIA <Rn>!, <registers>
where:
<Rn> ! <registers>
Is the register containing the start address for the instruction. Causes base register write-back, and is not optional. Is a list of registers to be loaded, separated by commas and surrounded by { and }. The list is encoded in the register_list field of the instruction, by setting bit[i] to 1 if register Ri is included in the list and to 0 otherwise, for each of i=0 to 7. At least one register must be loaded. If bits[7:0] are all zero, the result is
UNPREDICTABLE.
The registers are loaded in sequence, the lowest-numbered register from the lowest memory address (start_address), through to the highest-numbered register from the highest memory address (end_address). The start_address is the value of the base register <Rn>. Subsequent addresses are formed by incrementing the previous address by four. One address is produced for each register that is specified in <registers>. The end_address value is four less than the sum of the value of the base register and four times the number of registers specified in <registers>. Finally, when <Rn> is not a member of <registers>, the base register <Rn> is incremented by four times the number of registers in <registers>. See operand restrictions.
Architecture version
All T variants.
Exceptions
Data Abort.
A7-44
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Operation
MemoryAccess(B-bit, E-bit) start_address = Rn end_address = Rn + (Number_Of_Set_Bits_In(register_list) * 4) - 4 address = start_address for i = 0 to 7 if register_list[i] == 1 Ri = Memory[address,4] address = address + 4 assert end_address == address - 4 Rn = Rn + (Number_Of_Set_Bits_In(register_list) * 4)
Usage
Use LDMIA as a block load instruction. Combined with STMIA (Store Multiple), it allows efficient block copy.
Notes
Operand restrictions If the base register <Rn> is specified in <registers>, the final value of <Rn> is the loaded value (not the written-back value). Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor) and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception. From ARMv6, an alignment checking option is supported: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, the instruction ignores the least significant two bits of the address. and CP15_reg1_Ubit == 1, unaligned accesses cause a Data Abort (Alignment fault).
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38. Time order The time order of the accesses to individual words of memory generated by this instruction is only defined in some circumstances. See Memory access restrictions on page B2-13 for details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-45
Thumb Instructions
Equivalent ARM syntax and encoding
If <Rn> is not in the register list (W == 1):
LDMIA <Rn>!, <registers>
If <Rn> is in the register list (W == 0):
LDMIA <Rn>, <registers>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15 14 13 12 11 10 9 8
7
0
1 1 1 0 1 0 0 0 1 0W1
Rn
00000000
register_list
A7-46
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.28 LDR (1)
15 14 13 12 11 10 6 5 3 2 0
0
1
1
0
1
immed_5
Rn
Rd
LDR (1) (Load Register) allows 32-bit memory data to be loaded into a general-purpose register. The addressing mode is useful for accessing structure (record) fields. With an offset of zero, the address produced is the unaltered value of the base register <Rn>.
Syntax
LDR <Rd>, [<Rn>, #<immed_5> * 4]
where:
<Rd> <Rn> <immed_5>
Is the destination register for the word loaded from memory. Is the register containing the base address for the instruction. Is a 5-bit value that is multiplied by 4 and added to the value of <Rn> to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) address = Rn + (immed_5 * 4) if (CP15_reg1_Ubit == 0) if address[1:0] == 0b00 then data = Memory[address,4] else data = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ data = Memory[address,4] Rd = data
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-47
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not word-aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort when address[1:0] != 0b00), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 76 2 10
111001011001
Rn
Rd
00000
immed_5
00
A7-48
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.29 LDR (2)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
1
0
1
1
0
0
Rm
Rn
Rd
LDR (2) loads 32-bit memory data into a general-purpose register. The addressing mode is useful for pointer+large offset arithmetic and for accessing a single element of an array.
Syntax
LDR <Rd>, [<Rn>, <Rm>]
where:
<Rd> <Rn> <Rm>
Is the destination register for the word loaded from memory. Is the register containing the first value used in forming the memory address. Is the register containing the second value used in forming the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) address = Rn + Rm if (CP15_reg1_Ubit == 0) if address[1:0] == 0b00 then data = Memory[address,4] else data = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ data = Memory[address,4] Rd = data
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-49
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not word-aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort when address[1:0] != 0b00), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
LDR <Rd>, [<Rn>, <Rm>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111001111001
Rn
Rd
00000000
Rm
A7-50
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.30 LDR (3)
15 14 13 12 11 10 8 7 0
0
1
0
0
1
Rd
immed_8
LDR (3) loads 32-bit memory data into a general-purpose register. The addressing mode is useful for
accessing PC-relative data.
Syntax
LDR <Rd>, [PC, #<immed_8> * 4]
where:
<Rd> PC
Is the destination register for the word loaded from memory. Is the program counter. Its value is used to calculate the memory address. Bit 1 of the PC value is forced to zero for the purpose of this calculation, so the address is always word-aligned. Is an 8-bit value that is multiplied by 4 and added to the value of the PC to form the memory address.
<immed_8>
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) address = (PC & 0xFFFFFFFC) + (immed_8 * 4) Rd = Memory[address, 4]
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-51
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not word-aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort when address[1:0] != 0b00), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
A close equivalent is:
LDR <Rd>, [PC, #<immed_8> * 4]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
12 11 10 9
2
10
1110010110011111
Rd
00
immed_8
00
There are slight differences caused by the different definitions of the PC and the fact that the Thumb instruction ignores bit[1] of the PC.
A7-52
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.31 LDR (4)
15 14 13 12 11 10 8 7 0
1
0
0
1
1
Rd
immed_8
LDR (4) loads 32-bit memory data into a general-purpose register. The addressing mode is useful for
accessing stack data.
Syntax
LDR <Rd>, [SP, #<immed_8> * 4]
where:
<Rd> SP <immed_8>
Is the destination register for the word loaded from memory. Is the stack pointer. Its value is used to calculate the memory address. Is an 8-bit value that is multiplied by 4 and added to the value of the SP to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) address = SP + (immed_8 * 4) if (CP15_reg1_Ubit == 0) if address[1:0] == 0b00 then data = Memory[address,4] else data = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ data = Memory[address,4] Rd = data
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-53
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not word-aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort when address[1:0] != 0b00), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
LDR <Rd>, [SP, #<immed_8> * 4]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
12 11 10 9
2
10
1110010110011101
Rd
00
immed_8
00
A7-54
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.32 LDRB (1)
15 14 13 12 11 10 6 5 3 2 0
0
1
1
1
1
immed_5
Rn
Rd
LDRB (1) (Load Register Byte) loads a byte from memory, zero-extends it to form a 32-bit word, and writes the result to a general-purpose register. The addressing mode is useful for accessing structure (record) fields. With an offset of zero, the address produced is the unaltered value of the base register <Rn>.
Syntax
LDRB <Rd>, [<Rn>, #<immed_5>]
where:
<Rd> <Rn> <immed_5>
Is the destination register for the byte loaded from memory. Is the register containing the base address for the instruction. Is a 5-bit value that is added to the value of <Rn> to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
address = Rn + immed_5 Rd = Memory[address,1]
Notes
Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Equivalent ARM syntax and encoding
LDRB <Rd>, [<Rn>, #<immed_5>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7 6 5 4
0
111001011101
Rn
Rd
0000000
immed_5
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-55
Thumb Instructions
A7.1.33 LDRB (2)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
1
0
1
1
1
0
Rm
Rn
Rd
LDRB (2) loads a byte from memory, zero-extends it to form a 32-bit word, and writes the result to a general-purpose register. The addressing mode is useful for pointer+large offset arithmetic and for accessing a single element of an array.
Syntax
LDRB <Rd>, [<Rn>, <Rm>]
where:
<Rd> <Rn> <Rm>
Is the destination register for the byte loaded from memory. Is the register containing the first value used in forming the memory address. Is the register containing the second value used in forming the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
address = Rn + Rm Rd = Memory[address,1]
Notes
Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Equivalent ARM syntax and encoding
LDRB <Rd>, [<Rn>, <Rm>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111001111101
Rn
Rd
00000000
Rm
A7-56
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.34 LDRH (1)
15 14 13 12 11 10 6 5 3 2 0
1
0
0
0
1
immed_5
Rn
Rd
LDRH (1) (Load Register Halfword) loads a halfword (16 bits) from memory, zero-extends it to form a 32-bit word, and writes the result to a general-purpose register. The addressing mode is useful for accessing structure (record) fields. With an offset of zero, the address produced is the unaltered value of the base register <Rn>.
Syntax
LDRH <Rd>, [<Rn>, #<immed_5> * 2]
where:
<Rd> <Rn> <immed_5>
Is the destination register for the halfword loaded from memory. Is the register containing the base address for the instruction. Is a 5-bit value that is multiplied by 2, then added to the value of <Rn> to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) address = Rn + (immed_5 * 2) if (CP15_reg1_Ubit == 0) if address[0] == 0b0 then data = Memory[address,2] else data = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ data = Memory[address,2] Rd = ZeroExtend(data[15:0])
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-57
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not halfword-aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort when address[0] != 0), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
LDRH <Rd>, [<Rn>, #<immed_5> * 2]
31 30 29 28 27 26 25 24 23 22 21 10 19
16 15
12 11 10 9
8
76543
10
111000011101
Rn
Rd
00
immed immed 1011 [4:3] [2:0]
0
A7-58
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.35 LDRH (2)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
1
0
1
1
0
1
Rm
Rn
Rd
LDRH (2) loads a halfword (16 bits) from memory, zero-extends it to form a 32-bit word, and writes the result
to a general-purpose register. The addressing mode is useful for pointer + large offset arithmetic and for accessing a single element of an array.
Syntax
LDRH <Rd>, [<Rn>, <Rm>]
where:
<Rd> <Rn> <Rm>
Is the destination register for the halfword loaded from memory. Is the register containing the first value used in forming the memory address. Is the register containing the second value used in forming the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) address = Rn + Rm if (CP15_reg1_Ubit == 0) if address[0] == 0b0 then data = Memory[address,2] else data = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ data = Memory[address,2] Rd = ZeroExtend(data[15:0])
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-59
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not halfword-aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort when address[0] != 0), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
LDRH <Rd>, [<Rn>, <Rm>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
8
76543
0
111000011001
Rn
Rd
SBZ
1011
Rm
A7-60
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.36 LDRSB
15 14 13 12 11 10 9 8 6 5 3 2 0
0
1
0
1
0
1
1
Rm
Rn
Rd
LDRSB (Load Register Signed Byte) loads a byte from memory, sign-extends it to form a 32-bit word, and writes the result to a general-purpose register.
Syntax
LDRSB <Rd>, [<Rn>, <Rm>]
where:
<Rd> <Rn> <Rm>
Is the destination register for the byte loaded from memory. Is the register containing the first value used in forming the memory address. Is the register containing the second value used in forming the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
address = Rn + Rm Rd = SignExtend(Memory[address,1])
Notes
Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Equivalent ARM syntax and encoding
LDRSB <Rd>, [<Rn>, <Rm>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
87654
3
0
111000011001
Rn
Rd
SBZ
1101
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-61
Thumb Instructions
A7.1.37 LDRSH
15 14 13 12 11 10 9 8 6 5 3 2 0
0
1
0
1
1
1
1
Rm
Rn
Rd
LDRSH (Load Register Signed Halfword) loads a halfword from memory, sign-extends it to form a 32-bit
word, and writes the result to a general-purpose register.
Syntax
LDRSH <Rd>, [<Rn>, <Rm>]
where:
<Rd> <Rn> <Rm>
Is the destination register for the halfword loaded from memory. Is the register containing the first value used in forming the memory address. Is the register containing the second value used in forming the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) address = Rn + Rm if (CP15_reg1_Ubit == 0) if address[0] == 0b0 then data = Memory[address,2] else data = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ data = Memory[address,2] Rd = SignExtend(data[15:0])
A7-62
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not halfword-aligned, the data read from memory is UNPREDICTABLE. Alignment checking (taking a data abort when address[0] != 0), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
LDRSH <Rd>, [<Rn>, <Rm>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
87654
3
0
111000011001
Rn
Rd
SBZ
1111
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-63
Thumb Instructions
A7.1.38 LSL (1)
15 14 13 12 11 10 6 5 3 2 0
0
0
0
0
0
immed_5
Rm
Rd
LSL (1) (Logical Shift Left) provides the value of the contents of a register multiplied by a constant power
of two. It inserts zeroes into the bit positions vacated by the shift, and updates the condition code flags, based on the result.
Syntax
LSL <Rd>, <Rm>, #<immed_5>
where:
<Rd> <Rm> <immed_5>
Is the register that stores the result of the operation. Is the register containing the value to be shifted. Specifies the shift amount, in the range 0 to 31.
Architecture version
All T variants.
Exceptions
None.
Operation
if immed_5 == 0 C Flag = unaffected Rd = Rm else /* immed_5 > 0 */ C Flag = Rm[32 - immed_5] Rd = Rm Logical_Shift_Left immed_5 N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 V Flag = unaffected
A7-64
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
MOVS <Rd>, <Rm>, LSL #<immed_5>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
7654
3
0
111000011011
SBZ
Rd
immed_5
000
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-65
Thumb Instructions
A7.1.39 LSL (2)
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
0
0
1
0
Rs
Rd
LSL (2) provides the value of a register multiplied by a variable power of two. It inserts zeroes into the
vacated bit positions. It updates the condition code flags, based on the result.
Syntax
LSL <Rd>, <Rs>
where:
<Rd> <Rs>
Contains the value to be shifted, and is the destination register for the result of the operation. Is the register containing the shift value. The value is held in the least significant byte.
Architecture version
All T variants.
Exceptions
None.
Operation
if Rs[7:0] == 0 C Flag = unaffected Rd = unaffected else if Rs[7:0] < 32 then C Flag = Rd[32 - Rs[7:0]] Rd = Rd Logical_Shift_Left Rs[7:0] else if Rs[7:0] == 32 then C Flag = Rd[0] Rd = 0 else /* Rs[7:0] > 32 */ C Flag = 0 Rd = 0 N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 V Flag = unaffected
A7-66
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
MOVS <Rd>, <Rd>, LSL <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
87654
3
0
111000011011
SBZ
Rd
Rs
0001
Rd
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-67
Thumb Instructions
A7.1.40 LSR (1)
15 14 13 12 11 10 6 5 3 2 0
0
0
0
0
1
immed_5
Rm
Rd
LSR (1) (Logical Shift Right) provides the unsigned value of a register, divided by a constant power of two.
It inserts zeroes into the vacated bit positions. It updates the condition code flags, based on the result.
Syntax
LSR <Rd>, <Rm>, #<immed_5>
where:
<Rd> <Rm> <immed_5>
Is the destination register for the operation. Is the register containing the value to be shifted. Specifies the shift amount, in the range 1 to 32. Shifts by 1 to 31 are encoded directly in immed_5. A shift by 32 is encoded as immed_5 == 0.
Architecture version
All T variants.
Exceptions
None.
Operation
if immed_5 == 0 C Flag = Rm[31] Rd = 0 else /* immed_5 > 0 */ C Flag = Rm[immed_5 - 1] Rd = Rm Logical_Shift_Right immed_5 N Flag = Rd[31] /* 0b0 */ Z Flag = if Rd == 0 then 1 else 0 V Flag = unaffected
A7-68
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
MOVS <Rd>, <Rm>, LSR #<immed_5>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
7654
3
0
111000011011
SBZ
Rd
immed_5
010
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-69
Thumb Instructions
A7.1.41 LSR (2)
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
0
0
1
1
Rs
Rd
LSR (2) provides the unsigned value of a register divided by a variable power of two. It inserts zeroes into
the vacated bit positions. It updates the condition code flags, based on the result.
Syntax
LSR <Rd>, <Rs>
where:
<Rd> <Rs>
Contains the value to be shifted, and is the destination register for the result of the operation. Is the register containing the shift value. The value is held in the least significant byte.
Architecture version
All T variants.
Exceptions
None.
Operation
if Rs[7:0] == 0 then C Flag = unaffected Rd = unaffected else if Rs[7:0] < 32 then C Flag = Rd[Rs[7:0] - 1] Rd = Rd Logical_Shift_Right Rs[7:0] else if Rs[7:0] == 32 then C Flag = Rd[31] Rd = 0 else /* Rs[7:0] > 32 */ C Flag = 0 Rd = 0 N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 V Flag = unaffected
A7-70
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
MOVS <Rd>, <Rd>, LSR <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
87654
3
0
111000011011
SBZ
Rd
Rs
0011
Rd
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-71
Thumb Instructions
A7.1.42 MOV (1)
15 14 13 12 11 10 8 7 0
0
0
1
0
0
Rd
immed_8
MOV (1) (Move) moves a large immediate value to a register.
It updates the condition code flags, based on the result.
Syntax
MOV <Rd>, #<immed_8>
where:
<Rd> <immed_8>
Is the destination register for the operation. Is an 8-bit immediate value, in the range 0 to 255, to move into <Rd>.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = immed_8 N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = unaffected V Flag = unaffected
Equivalent ARM syntax and encoding
MOVS <Rd>, #<immed_8>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
7
0
111000111011
SBZ
Rd
0000
immed_8
A7-72
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.43 MOV (2)
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
0
0
1
1
1
0
0
0
0
Rn
Rd
MOV (2) moves a value from one low register to another.
It updates the condition code flags, based on the value.
Syntax
MOV <Rd>, <Rn>
where:
<Rd> <Rn>
Is the destination register for the operation. Is the register containing the value to be copied.
Architecture Version
All T variants.
Exceptions
None.
Operation
Rd = Rn N Flag = Z Flag = C Flag = V Flag = Rd[31] if Rd == 0 then 1 else 0 0 0
Notes
Encoding This instruction is encoded as ADD Rd, Rn, #0. See also ADD (1) on page A7-5.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-73
Thumb Instructions
Equivalent ARM syntax and encoding
ADDS <Rd>, <Rn>, #0
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
765432
10
111000101001
Rn
Rd
000000000000
A7-74
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.44 MOV (3)
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
1
1
0
H1
H2
Rm
Rd
MOV (3) moves a value to, from, or between high registers.
Unlike the low register MOV instruction described in MOV (2) on page A7-73, this instruction does not change the flags.
Syntax
MOV <Rd>, <Rm>
where:
<Rd>
Is the destination register for the operation. It can be any of R0 to R15, and its number is encoded in the instruction in H1 (most significant bit) and Rd (remaining three bits). Is the register containing the value to be copied. It can be any of R0 to R15, and its number is encoded in the instruction in H2 (most significant bit) and Rm (remaining three bits).
<Rm>
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rm
Usage
The instruction MOV PC,R14 can be used as a subroutine return instruction if it is known that the caller is also a Thumb routine. However, you are strongly recommended to use BX R14 (see BX on page A7-32). The BX R14 instruction works regardless of whether the caller is an ARM routine or a Thumb routine, and has performance advantages on some processors.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-75
Thumb Instructions
Notes
Assembler syntax Both registers low If a low register is specified for both <Rd> and <Rm>, the assembler syntax MOV <Rd>, <Rm> is assembled to the MOV (2) instruction described on page A7-73. If H1==0 and H2==0 in the encoding, the instruction specifies a non-flag-setting copy move from one low register to another low register. This instruction cannot be written using the MOV syntax, because MOV <Rd>, <Rm> generates a flag-setting copy. However, you can write it using the CPY mnemonic, see CPY on page A7-41.
Note
Prior to ARMv6, specifying a low register for <Rd> and <Rm> (H1 == 0 and H2 == 0), the result is UNPREDICTABLE.
Equivalent ARM syntax and encoding
A close equivalent is:
MOV <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15 14
12 11 10 9 8
765432
0
111000011010
SBZ
H1
Rd
0 0 0 0 0 0 0 0 H2
Rm
There are slight differences when the instruction accesses the PC, because of the different definitions of the PC when executing ARM and Thumb code.
A7-76
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.45 MUL
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
1
1
0
1
Rm
Rd
MUL (Multiply) multiplies signed or unsigned variables to produce a 32-bit result. MUL updates the condition code flags, based on the result.
Syntax
MUL <Rd>, <Rm>
where:
<Rd>
Contains the value to be multiplied with the value of <Rm>, and is also the destination register for the operation. Is the register containing the value to be multiplied with the value of <Rd>.
<Rm>
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = (Rm N Flag = Z Flag = C Flag = V Flag = * Rd)[31:0] Rd[31] if Rd == 0 then 1 else 0 unaffected /* See "C flag" note */ unaffected
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-77
Thumb Instructions
Notes
Early termination If the multiplier implementation supports early termination, it must be implemented on the value of the <Rd> operand. The type of early termination used (signed or unsigned) is IMPLEMENTATION DEFINED.
Signed and unsigned As MUL produces only the lower 32 bits of the 64-bit product, MUL gives the same answer for multiplication of both signed and unsigned numbers. C flag The MUL instruction is defined to leave the C flag unchanged in ARMv5 and above. In earlier versions of the architecture, the value of the C flag was UNPREDICTABLE after a MUL instruction.
Operand restriction Prior to ARMv6, specifying the same register for <Rd> and <Rm> had UNPREDICTABLE results.
Equivalent ARM syntax and encoding
MULS <Rd>, <Rm>, <Rd>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
8
76543
0
111000000001
Rd
SBZ
Rd
1001
Rm
Note
The following instruction is not a suitable alternative, as it violates the operand restriction on the ARM instruction (see MUL on page A4-80) and might have the wrong early termination behavior:
MULS <Rd>, <Rd>, <Rm>
A7-78
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.46 MVN
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
1
1
1
1
Rm
Rd
MVN (Move NOT) complements a register value. This is often used to form a bit mask. MVN updates the condition code flags, based on the result.
Syntax
MVN <Rd>, <Rm>
where:
<Rd> <Rm>
Is the destination register for the operation. Is the register containing the value whose ones complement is written to <Rd>.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = NOT N Flag = Z Flag = C Flag = V Flag = Rm Rd[31] if Rd == 0 then 1 else 0 unaffected unaffected
Equivalent ARM syntax and encoding
MVNS <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7 6 5 4
3
0
111000011111
SBZ
Rd
00000000
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-79
Thumb Instructions
A7.1.47 NEG
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
1
0
0
1
Rm
Rd
NEG (Negate) negates the value of one register and stores the result in a second register. NEG updates the condition code flags, based on the result.
Syntax
NEG <Rd>, <Rm>
where:
<Rd> <Rm>
Is the destination register for the operation. Is the register containing the value is that subtracted from zero.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = 0 N Flag Z Flag C Flag V Flag = = = = Rm Rd[31] if Rd == 0 then 1 else 0 NOT BorrowFrom(0 - Rm) OverflowFrom(0 - Rm)
Equivalent ARM syntax and encoding
RSBS <Rd>, <Rm>, #0
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
765432
10
111000100111
Rm
Rd
000000000000
A7-80
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.48 ORR
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
1
1
0
0
Rm
Rd
ORR (Logical OR) performs a bitwise OR of the values from two registers. ORR updates the condition code flags, based on the result.
Syntax
ORR <Rd>, <Rm>
where:
<Rd> <Rm>
Is the destination register for the operation. Is the register containing the value that is ORed with the value of <Rd>. The operation is a bitwise inclusive OR.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rd OR Rm N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = unaffected V Flag = unaffected
Equivalent ARM syntax and encoding
ORRS <Rd>, <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7 6 5 4
3
0
111000011001
Rd
Rd
00000000
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-81
Thumb Instructions
A7.1.49 POP
15 14 13 12 11 10 9 8 7 0
1
0
1
1
1
1
0
R
register_list
POP (Pop Multiple Registers) loads a subset (or possibly all) of the general-purpose registers R0-R7 and the
PC from the stack. The general-purpose registers loaded can include the PC. If they do, the word loaded for the PC is treated as an address and a branch occurs to that address. In ARMv5 and above, bit[0] of the loaded value determines whether execution continues after this branch in ARM state or in Thumb state, as though the following instruction had been executed:
BX (loaded_value)
In T variants of ARMv4, bit[0] of the loaded value is ignored and execution continues in Thumb state, as though the following instruction had been executed:
MOV PC,(loaded_value)
Syntax
POP <registers>
where:
<registers>
Is the list of registers, separated by commas and surrounded by { and }. The list is encoded in the register_list field of the instruction, by setting bit[i] to 1 if register Ri is included in the list and to 0 otherwise, for each of i=0 to 7. The R bit (bit[8]) is set to 1 if the PC is in the list and to 0 otherwise. At least one register must be loaded. If bits[8:0] are all zero, the result is
UNPREDICTABLE.
The registers are loaded in sequence, the lowest-numbered register from the lowest memory address (start_address), through to the highest-numbered register from the highest memory address (end_address). If the PC is specified in the register list (opcode bit[8] is set), the instruction causes a branch to the address (data) loaded into the PC. The <start_address> is the value of the SP. Subsequent addresses are formed by incrementing the previous address by four. One address is produced for each register that is specified in <registers>. The end_address value is four less than the sum of the value of the SP and four times the number of registers specified in <registers>. The SP register is incremented by four times the numbers of registers in
<registers>.
A7-82
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) start_address = SP end_address = SP + 4*(R + Number_Of_Set_Bits_In(register_list)) address = start_address for i = 0 to 7 if register_list[i] == 1 then Ri = Memory[address,4] address = address + 4 if R == 1 then value = Memory[address,4] PC = value AND 0xFFFFFFFE if (architecture version 5 or above) then T Bit = value[0] address = address + 4 assert end_address = address SP = end_address
Usage
Use POP for stack operations. A POP instruction with the PC in the register list can be used for an efficient procedure exit, as it restores saved registers, loads the PC with the return address, and updates the stack pointer with a single instruction.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-83
Thumb Instructions
Notes
Data Abort CPSR Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Only the T-bit in the CPSR can be updated by the POP instruction. All other bits are unaffected. If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor) and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception. From ARMv6, an alignment checking option is supported: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, the instruction ignores the least significant two bits of the address. and CP15_reg1_Ubit == 1, unaligned accesses cause a Data Abort (Alignment fault).
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38. ARM/Thumb state transfers In ARM architecture 5 and above, if bits[1:0] of a value loaded for R15 are 0b10, the result is UNPREDICTABLE, as branches to non word-aligned addresses are not possible in ARM state. Time order The time order of the accesses to individual words of memory generated by this instruction is only defined in some circumstances. See Memory access restrictions on page B2-13 for details.
Equivalent ARM syntax and encoding
LDMIA SP!, <registers>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7
0
1110100010111101R0000000
register_list
A7-84
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.50 PUSH
15 14 13 12 11 10 9 8 7 0
1
0
1
1
0
1
0
R
register_list
PUSH (Push Multiple Registers) stores a subset (or possibly all) of the general-purpose registers R0-R7 and the LR to the stack.
Syntax
PUSH <registers>
where:
<registers>
Is the list of registers to be stored, separated by commas and surrounded by { and }. The list is encoded in the register_list field of the instruction, by setting bit[i] to 1 if register Ri is included in the list and to 0 otherwise, for each of i=0 to 7. The R bit (bit[8]) is set to 1 if the LR is in the list and to 0 otherwise. At least one register must be stored. If bits[8:0] are all zero, the result is
UNPREDICTABLE.
The registers are stored in sequence, the lowest-numbered register to the lowest memory address (start_address), through to the highest-numbered register to the highest memory address (end_address) The start_address is the value of the SP minus 4 times the number of registers to be stored. Subsequent addresses are formed by incrementing the previous address by four. One address is produced for each register that is specified in <registers>. The end_address value is four less than the original value of SP. The SP register is decremented by four times the numbers of registers in
<registers>.
Architecture version
All T variants.
Exceptions
Data Abort.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-85
Thumb Instructions
Operation
MemoryAccess(B-bit, E-bit) start_address = SP - 4*(R + Number_Of_Set_Bits_In(register_list)) end_address = SP - 4 address = start_address for i = 0 to 7 if register_list[i] == 1 Memory[address,4] = Ri address = address + 4 if R == 1 Memory[address,4] = LR address = address + 4 assert end_address == address - 4 SP = SP - 4*(R + Number_Of_Set_Bits_In(register_list)) if (CP15_reg1_Ubit == 1) /* ARMv6 */ if Shared(address then /* from ARMv6 */ physical_address = TLB(address ClearExclusiveByAddress(physical_address, size)
For details on shared memory and synchronization primitives, see Synchronization primitives on page A2-44.
Usage
Use PUSH for stack operations. A PUSH instruction with the LR in the register list can be used for an efficient procedure entry, as it saves registers (including the return address) on the stack and updates the stack pointer with a single instruction. A matching POP instruction can be used later to return from the procedure.
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
PUSH instructions ignore the least significant two bits of address.
If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor) and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception. From ARMv6, an alignment checking option is supported: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, the instruction ignores the least significant two bits of the address. and CP15_reg1_Ubit == 1, unaligned accesses cause a Data Abort (Alignment fault).
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
A7-86
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Time order
The time order of the accesses to individual words of memory generated by this instruction is only defined in some circumstances. See Memory access restrictions on page B2-13 for details.
Equivalent ARM syntax and encoding
STMDB SP!, <registers>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
0
11101001001011010R000000
register_list
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-87
Thumb Instructions
A7.1.51 REV
15 12 11 8 7 6 5 3 2 0
1
0
1
1
1
0
1
0
0
0
Rn
Rd
REV (Byte-Reverse Word) reverses the byte order in a 32-bit register. It does not affect the flags.
Syntax
REV Rd, Rn
where:
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the operand.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
Rd[31:24] Rd[23:16] Rd[15: 8] Rd[ 7: 0] = = = = Rn[ 7: 0] Rn[15: 8] Rn[23:16] Rn[31:24]
Usage
Use REV to convert 32-bit big-endian data into little-endian data, or 32-bit little-endian data into big-endian data.
Equivalent ARM syntax and encoding
REV Rd, Rm
31
28 27
23 22 21 20 19
16 15
12 11
8
76
43
0
111001101011
SBO
Rd
SBO
0011
Rm
A7-88
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.52 REV16
15 12 11 8 7 6 5 3 2 0
1
0
1
1
1
0
1
0
0
1
Rn
Rd
REV16 (Byte-Reverse Packed Halfword) reverses the byte order in each 16-bit halfword of a 32-bit register.
It does not affect the flags
Syntax
REV16 Rd, Rn
where:
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the operand.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
Rd[15: 8] Rd[ 7: 0] Rd[31:24] Rd[23:16] = = = = Rn[ 7: 0] Rn[15: 8] Rn[23:16] Rn[31:24]
Usage
Use REV16 to convert 16-bit big-endian data into little-endian data, or 16-bit little-endian data into big-endian data.
Equivalent ARM syntax and encoding
REV16 Rd, Rm
31
28 27
23 22 21 20 19
16 15
12 11
876
4
3
0
111001101011
SBO
Rd
SBO
1011
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-89
Thumb Instructions
A7.1.53 REVSH
15 12 11 8 7 6 5 3 2 0
1
0
1
1
1
0
1
0
1
1
Rn
Rd
REVSH (Byte-Reverse Signed Halfword) reverses the byte order in the lower 16-bit halfword of a 32-bit
register, and sign extends the result to 32-bits. It does not affect the flags.
Syntax
REVSH Rd, Rn
where:
<Rd> <Rn>
Specifies the destination register. Specifies the register that contains the operand.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
Rd[15: 8] = Rn[ 7: 0] Rd[ 7: 0] = Rn[15: 8] if Rn[7] == 1 then Rd[31:16] = 0xFFFF else Rd[31:16] = 0x0000
Usage
Use REVSH to convert either: 16-bit signed big-endian data into 32-bit signed little-endian data 16-bit signed little-endian data into 32-bit signed big-endian data.
A7-90
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
REVSH Rd, Rm
31
28 27
23 22 21 20 19
16 15
12 11
876
4
3
0
111001101111
SBO
Rd
SBO
1011
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-91
Thumb Instructions
A7.1.54 ROR
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
0
1
1
1
Rs
Rd
ROR (Rotate Right Register) provides the value of the contents of a register rotated by a variable value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. ROR updates the condition code flags, based on the result.
Syntax
ROR <Rd>, <Rs>
where:
<Rd> <Rs>
Contains the value to be rotated, and is also the destination register for the operation. Is the register containing the rotation applied to the value of <Rd>. The value of the rotation is stored in the least significant byte.
Architecture version
All T variants.
Exceptions
None.
Operation
if Rs[7:0] == 0 then C Flag = unaffected Rd = unaffected else if Rs[4:0] == 0 then C Flag = Rd[31] Rd = unaffected else /* Rs[4:0] > 0 */ C Flag = Rd[Rs[4:0] - 1] Rd = Rd Rotate_Right Rs[4:0] N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 V Flag = unaffected
A7-92
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
MOVS <Rd>, <Rd>, ROR <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
87654
3
0
111000011011
SBZ
Rd
Rs
0111
Rd
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-93
Thumb Instructions
A7.1.55 SBC
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
0
1
1
0
Rm
Rd
SBC (Subtract with Carry) subtracts the value of its second operand and the value of NOT(Carry flag) from
the value of its first operand.
SBC updates the condition code flags, based on the result.
Use SBC to synthesize multi-word subtraction.
Syntax
SBC <Rd>, <Rm>
where:
<Rd>
Contains the first operand for the subtraction, and is also the destination register for the operation. Contains the value to be subtracted from <Rd>.
<Rm>
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rd - Rm - NOT(C Flag) N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rd - Rm - NOT(C Flag)) V Flag = OverflowFrom(Rd - Rm - NOT(C Flag))
Equivalent ARM syntax and encoding
SBCS <Rd>, <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111000001101
Rd
Rd
00000000
Rm
A7-94
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.56 SETEND
15 14 13 12 11 10 9 8 7 6 5 3 2 0
1
0
1
1
0
1
1
0
0
1
0
1
E
SBZ
SETEND modifies the CPSR E bit, without changing any other bits in the CPSR.
Syntax
SETEND <endian_specifier>
where:
<endian_specifier>
Is one of:
BE LE
Sets the E bit in the instruction. This sets the CPSR E bit. Clears the E bit in the instruction. This clears the CPSR E bit.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
CPSR = CPSR with specified E bit modification
Usage
Use SETEND to change the byte order for data accesses. You can use SETEND to increase the efficiency of access to a series of big-endian data fields in an otherwise little-endian application, or to a series of little-endian data fields in an otherwise big-endian application. See Endian support on page A2-30 for more information.
Equivalent ARM syntax and encoding
SETEND <endian_specifier>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
10 9
8
7
43
0
1111000100000001
SBZ
E SBZ 0 0 0 0
SBZ
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-95
Thumb Instructions
A7.1.57 STMIA
15 14 13 12 11 10 8 7 0
1
1
0
0
0
Rn
register_list
STMIA (Store Multiple Increment After) stores a non-empty subset, or possibly all, of the general-purpose registers to sequential memory locations.
Syntax
STMIA <Rn>!, <registers>
where:
<Rn> ! <registers>
Is the register containing the start address for the instruction. Causes base register write-back, and is not optional. Is a list of registers to be stored, separated by commas and surrounded by { and }. The list is encoded in the register_list field of the instruction, by setting bit[i] to 1 if register Ri is included in the list and to 0 otherwise, for each of i=0 to 7. At least one register must be stored. If bits[7:0] are all zero, the result is
UNPREDICTABLE.
The registers are stored in sequence, the lowest-numbered register to the lowest memory address (start_address), through to the highest-numbered register to the highest memory address (end_address). The start_address is the value of the base register <Rn>. Subsequent addresses are formed by incrementing the previous address by four. One address is produced for each register that is specified in <registers>. The end_address value is four less than the sum of the value of the base register and four times the number of registers specified in <registers>. Finally, the base register <Rn> is incremented by 4 times the numbers of registers in
<registers>.
Architecture version
All T variants.
Exceptions
Data Abort.
A7-96
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() start_address = Rn end_address = Rn + (Number_Of_Set_Bits_In(register_list) * 4) - 4 address = start_address for i = 0 to 7 if register_list[i] == 1 Memory[address,4] = Ri if Shared(address then /* from ARMv6 */ physical_address = TLB(address ClearExclusiveByAddress(physical_address,4) address = address + 4 assert end_address == address - 4 Rn = Rn + (Number_Of_Set_Bits_In(register_list) * 4)
For details on shared memory and synchronization primitives, see Synchronization primitives on page A2-44.
Usage
STMIA is useful as a block store instruction. Combined with LDMIA (Load Multiple), it allows efficient block
copy.
Notes
Operand restrictions If <Rn> is specified in <registers>: Data Abort Alignment If <Rn> is the lowest-numbered register specified in <registers>, the original value of <Rn> is stored. Otherwise, the stored value of <Rn> is UNPREDICTABLE.
For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Store Multiple instructions ignore the least significant two bits of address. If an implementation includes a System Control coprocessor (see Chapter B3 The System Control Coprocessor) and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception. From ARMv6, an alignment checking option is supported: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, the instruction ignores the least significant two bits of the address.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-97
Thumb Instructions
and CP15_reg1_Ubit == 1, unaligned accesses cause a Data Abort (Alignment fault).
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38. Time order The time order of the accesses to individual words of memory generated by this instruction is only defined in some circumstances. See Memory access restrictions on page B2-13 for details.
Equivalent ARM syntax and encoding
STMIA <Rn>!, <registers>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15 14 13 12 11 10 9 8
7
0
111010001010
Rn
00000000
register_list
A7-98
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.58 STR (1)
15 14 13 12 11 10 6 5 3 2 0
0
1
1
0
0
immed_5
Rn
Rd
STR (1) (Store Register) stores 32-bit data from a general-purpose register to memory. The addressing mode
is useful for accessing structure (record) fields. With an offset of zero, the address produced is the unaltered value of the base register <Rn>.
Syntax
STR <Rd>, [<Rn>, #<immed_5> * 4]
where:
<Rd> <Rn> <immed_5>
Is the register that contains the word to be stored to memory. Is the register containing the base address for the instruction. Is a 5-bit value that is multiplied by 4 and added to the value of <Rn> to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-99
Thumb Instructions
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() address = Rn + (immed_5 * 4) if (CP15_reg1_Ubit == 0) if address[1:0] == 0b00 then Memory[address,4] = Rd else Memory[address,4] = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ Memory[address,4] = Rd if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address, 4)
For details on shared memory and synchronization primitives, see Synchronization primitives on page A2-44.
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not word-aligned, the instruction is UNPREDICTABLE. Alignment checking (taking a data abort when address[1:0] != 0b00), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
STR <Rd>, [<Rn>, #<immed_5> * 4]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76
2
10
111001011000
Rn
Rd
00000
immed_5
00
A7-100
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.59 STR (2)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
1
0
1
0
0
0
Rm
Rn
Rd
STR (2) stores 32-bit data from a general-purpose register to memory. The addressing mode is useful for
pointer + large offset arithmetic, and for accessing a single element of an array.
Syntax
STR <Rd>, [<Rn>, <Rm>]
where:
<Rd> <Rn> <Rm>
Is the register that contains the word to be stored to memory. Is the register containing the first value used in forming the memory address. Is the register containing the second value used in forming the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() address = Rn + Rm if (CP15_reg1_Ubit == 0) if address[1:0] == 0b00 then Memory[address,4] = Rd else Memory[address,4] = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ Memory[address,4] = Rd if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address, 4)
For details on shared memory and synchronization primitives, see Synchronization primitives on page A2-44.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-101
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not word-aligned, the instruction is UNPREDICTABLE. Alignment checking (taking a data abort when address[1:0] != 0b00), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
STR <Rd>, [<Rn>, <Rm>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111001111000
Rn
Rd
00000000
Rm
A7-102
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.60 STR (3)
15 14 13 12 11 10 8 7 0
1
0
0
1
0
Rd
immed_8
STR (3) stores 32-bit data from a general-purpose register to memory. The addressing mode is useful for accessing stack data. In this case, STR stores a word from register <Rd> to memory.
Syntax
STR <Rd>, [SP, #<immed_8> * 4]
where:
<Rd> SP <immed_8>
Is the register that contains the word to be stored to memory. Is the stack pointer. Its value is used to calculate the memory address. Is an 8-bit value that is multiplied by 4 and added to the value of the SP to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() address = SP + (immed_8 * 4) if (CP15_reg1_Ubit == 0) if address[1:0] == 0b00 then Memory[address,4] = Rd else Memory[address,4] = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ Memory[address,4] = Rd if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address, 4)
For details on shared memory and synchronization primitives, see Synchronization primitives on page A2-44.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-103
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not word-aligned, the instruction is UNPREDICTABLE. Alignment checking (taking a data abort when address[1:0] != 0b00), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
STR <Rd>, [SP, #<immed_8> * 4]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
12 11 10 9
2
10
1110010110001101
Rd
00
immed_8
00
A7-104
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.61 STRB (1)
15 14 13 12 11 10 6 5 3 2 0
0
1
1
1
0
immed_5
Rn
Rd
STRB (1) (Store Register Byte) stores 8-bit data from a general-purpose register to memory. The addressing
mode is useful for accessing structure (record) fields. With an offset of zero, the address produced is the unaltered value of the base register <Rn>.
Syntax
STRB <Rd>, [<Rn>, #<immed_5>]
where:
<Rd> <Rn> <immed_5>
Is the register whose least significant byte is stored to memory. Is the register containing the base address for the instruction. Is a 5-bit immediate value that is added to the value of <Rn> to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() address = Rn + immed_5 Memory[address,1] = Rd[7:0] if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address, 1)
For details on shared memory and synchronization primitives, see Synchronization primitives on page A2-44.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-105
Thumb Instructions
Notes
Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Equivalent ARM syntax and encoding
STRB <Rd>, [<Rn>, #<immed_5>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
7654
0
111001011100
Rn
Rd
0000000
immed_5
A7-106
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.62 STRB (2)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
1
0
1
0
1
0
Rm
Rn
Rd
STRB (2) stores 8-bit data from a general-purpose register to memory. The addressing mode is useful for pointer + large offset arithmetic, and for accessing a single element of an array.
Syntax
STRB <Rd>, [<Rn>, <Rm>]
where:
<Rd> <Rn> <Rm>
Is the register whose least significant byte is stored to memory. Is the register containing the first value used in forming the memory address. Is the register whose value is added to <Rn> to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() address = Rn + Rm Memory[address,1] = Rd[7:0] if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address, 1)
For details on shared memory and synchronization primitives, see Synchronization primitives on page A2-44.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-107
Thumb Instructions
Notes
Data Abort For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21.
Equivalent ARM syntax and encoding
STRB <Rd>, [<Rn>, <Rm>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111001111100
Rn
Rd
00000000
Rm
A7-108
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.63 STRH (1)
15 14 13 12 11 10 6 5 3 2 0
1
0
0
0
0
immed_5
Rn
Rd
STRH (1) (Store Register Halfword) stores 16-bit data from a general-purpose register to memory. The addressing mode is useful for accessing structure (record) fields. With an offset of zero, the address produced is the unaltered value of the base register <Rn>.
Syntax
STRH <Rd>, [<Rn>, #<immed_5> * 2]
where:
<Rd> <Rn> <immed_5>
Is the register whose least significant halfword is stored to memory. Is the register containing the base address for the instruction. Is a 5-bit immediate value that is multiplied by two and added to the value of <Rn> to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() address = Rn + (immed_5 * 2) if (CP15_reg1_Ubit == 0) if address[0] == 0b0 then Memory[address,2] = Rd[15:0] else Memory[address,2] = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ Memory[address,2] = Rd[15:0] if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address, 2)
For details on shared memory and synchronization primitives, see Synchronization primitives on page A2-44.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-109
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not halfword-aligned, the instruction is UNPREDICTABLE. Alignment checking (taking a data abort when address[0] != 0), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
STRH <Rd>, [<Rn>, #<immed_5> * 2]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9
8
7
6543
10
111000011100
Rn
Rd
00
immed immed 1011 0 [4:3] [2:0]
A7-110
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.64 STRH (2)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
1
0
1
0
0
1
Rm
Rn
Rd
STRH (2) stores 16-bit data from a general-purpose register to memory. The addressing mode is useful for
pointer + large offset arithmetic and for accessing a single element of an array.
Syntax
STRH <Rd>, [<Rn>, <Rm>]
where:
<Rd> <Rn> <Rm>
Is the register whose least significant halfword is stored to memory. Is the register containing the first value used in forming the memory address. Is the register whose value is added to <Rn> to form the memory address.
Architecture version
All T variants.
Exceptions
Data Abort.
Operation
MemoryAccess(B-bit, E-bit) processor_id = ExecutingProcessor() address = Rn + Rm if (CP15_reg1_Ubit == 0) if address[0] == 0b0 then Memory[address,2] = Rd[15:0] else Memory[address,2] = UNPREDICTABLE else /* CP15_reg1_Ubit == 1 */ Memory[address,2] = Rd[15:0] if Shared(address) then /* from ARMv6 */ physical_address = TLB(address) ClearExclusiveByAddress(physical_address, 2)
For details on shared memory and synchronization primitives, see Synchronization primitives on page A2-44.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-111
Thumb Instructions
Notes
Data Abort Alignment For details of the effects of the instruction if a Data Abort occurs, see Effects of data-aborted instructions on page A2-21. Prior to ARMv6, if the memory address is not halfword-aligned, the instruction is UNPREDICTABLE. Alignment checking (taking a data abort when address[0] != 0), and support for a big endian (BE-32) data format are implementation options. From ARMv6, a byte-invariant mixed endian format is supported, along with an alignment checking option: If CP15_reg1_Abit == 1, unaligned accesses cause a Data Abort (Alignment fault). If CP15_reg1_Abit == 0: and CP15_reg1_Ubit == 0, unaligned accesses are UNPREDICTABLE. and CP15_reg1_Ubit == 1, unaligned accesses are supported.
For more details on endianness and alignment, see Endian support on page A2-30 and Unaligned access support on page A2-38.
Equivalent ARM syntax and encoding
STRH <Rd>, [<Rn>, <Rm>]
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11
8
765432
10
111000011000
Rn
Rd
SBZ
1011
Rm
A7-112
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.65 SUB (1)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
0
0
1
1
1
1
immed_3
Rn
Rd
SUB (1) (Subtract) subtracts a small constant value from the value of a register and stores the result in a
second register. It updates the condition code flags, based on the result.
Syntax
SUB <Rd>, <Rn>, #<immed_3>
where:
<Rd> <Rn> <immed_3>
Is the destination register for the operation. Is the register containing the first operand for the subtraction. Is a 3-bit immediate value (values 0 to 7) that is subtracted from <Rn>.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rn - immed_3 N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rn - immed_3) V Flag = OverflowFrom(Rn - immed_3)
Equivalent ARM syntax and encoding
SUBS <Rd>, <Rn>, #<immed_3>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7 6 5 4
32
0
111000100101
Rn
Rd
0 0 0 0 0 0 0 0 0 immed_3
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-113
Thumb Instructions
A7.1.66 SUB (2)
15 14 13 12 11 10 8 7 0
0
0
1
1
1
Rd
immed_8
SUB (2) subtracts a large immediate value from the value of a register and stores the result back in the same
register. It updates the condition code flags, based on the result.
Syntax
SUB <Rd>, #<immed_8>
where:
<Rd>
Is the register containing the first operand for the subtraction, and is also the destination register for the operation. Is an 8-bit immediate value (values 0 to 255) that is subtracted from <Rd>.
<immed_8>
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rd - immed_8 N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rd - immed_8) V Flag = OverflowFrom(Rd - immed_8)
Equivalent ARM syntax and encoding
SUBS <Rd, <Rd>, #<immed_8>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
7
0
111000100101
Rd
Rd
0000
immed_8
A7-114
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.67 SUB (3)
15 14 13 12 11 10 9 8 6 5 3 2 0
0
0
0
1
1
0
1
Rm
Rn
Rd
SUB (3) subtracts the value of one register from the value of a second register and stores the result in a third
register. It updates the condition code flags, based on the result.
Syntax
SUB <Rd>, <Rn>, <Rm>
where:
<Rd> <Rn> <Rm>
Is the destination register for the operation. Is the register containing the first operand for the subtraction. Is the register whose value is subtracted from <Rn>.
Architecture version
All T variants.
Exceptions
None.
Operation
Rd = Rn - Rm N Flag = Rd[31] Z Flag = if Rd == 0 then 1 else 0 C Flag = NOT BorrowFrom(Rn - Rm) V Flag = OverflowFrom(Rn - Rm)
Equivalent ARM syntax and encoding
SUBS <Rd>, <Rn>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8 7 6 5 4
3
0
111000000101
Rn
Rd
00000000
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-115
Thumb Instructions
A7.1.68 SUB (4)
15 14 13 12 11 10 9 8 7 6 0
1
0
1
1
0
0
0
0
1
immed_7
SUB (4) decrements the SP by four times a 7-bit immediate (that is, by a multiple of 4 in the range 0 to 508).
The condition codes are not affected.
Syntax
SUB SP, #<immed_7> * 4
where:
SP <immed_7>
Indicates the stack pointer. The result of the operation is also stored in the SP. Is a 7-bit immediate value that is multiplied by 4 and then subtracted from the value of the stack pointer.
Architecture version
All T variants.
Exceptions
None.
Operation
SP = SP - (immed_7 << 2)
Usage
For the Full Descending stack which the Thumb instruction set is designed to use, decrementing the SP is used to allocate extra memory variables on the top of the stack.
Notes
Alternative syntax This instruction can also be written as SUB SP, SP, #<immed_7> * 4.
A7-116
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
SUB SP, SP, #<immed_7> * 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
0
1110001001001101110111110
immed_7
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-117
Thumb Instructions
A7.1.69 SWI
15 14 13 12 11 10 9 8 7 0
1
1
0
1
1
1
1
1
immed_8
SWI (Software Interrupt) generates a software interrupt or SWI, which is handled by an operating system.
See Exceptions on page A2-16. Use it as a call to an operating system service to provide a service.
Syntax
SWI <immed_8>
where:
<immed_8>
Is an 8-bit immediate value that is put into bits[7:0] of the instruction. This value is ignored by the processor, but can be used by an operating system's SWI exception handler to determine which operating system service is being requested.
Architecture version
All T variants.
Exceptions
Software Interrupt.
Operation
R14_svc = address of next instruction after the SWI instruction SPSR_svc = CPSR CPSR[4:0] = 0b10011 /* Enter Supervisor mode */ CPSR[5] =0 /* Execute in ARM state */ /* CPSR[6] is unchanged */ CPSR[7] =1 /* Disable normal interrupts */ /* CPSR[8] is unchanged */ CPSR[9] = CP15_reg1_EEbit if high vectors configured then PC = 0xFFFF0008 else PC = 0x00000008
A7-118
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
Equivalent ARM syntax and encoding
SWI <immed_8>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
0
111011110000000000000000
immed_8
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-119
Thumb Instructions
A7.1.70 SXTB
15 14 13 12 11 10 9 8 7 6 5 3 2 0
1
0
1
1
0
0
1
0
0
1
Rm
Rd
SXTB (Signed Extend Byte) extracts the least significant 8 bits of the operand, and sign extends the value to
32 bits. It does not affect the flags.
Syntax
SXTB <Rd>, <Rm>
where:
<Rd> <Rm>
Specifies the destination register. Specifies the operand register.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
Rd = SignExtend(Rm[7:0])
Usage
Use SXTB to sign extend a byte to a word, for example in instruction sequences acting on signed char values in C/C++.
Equivalent ARM syntax and encoding
SXTB <Rd>, <Rm>
31
28 27 26 25 24 23 22 21 20 19 18 17 16 15
12 11 10 9 8
76543
0
1110011010101111
Rd
00000111
Rm
A7-120
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.71 SXTH
15 14 13 12 11 10 9 8 7 6 5 3 2 0
1
0
1
1
0
0
1
0
0
0
Rm
Rd
SXTH16 (Signed Extend Halfword) extracts the least significant 16 bits of the operand, and sign extends the
value to 32 bits.
SXTH does not affect the flags.
Syntax
SXTH <Rd>, <Rm>
where:
<Rd> <Rm>
Specifies the destination register. Specifies the operand register.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
Rd = SignExtend(Rm[15:0])
Usage
Use SXTH to sign extend a halfword to a word, for example in instruction sequences acting on signed short values in C/C++.
Equivalent ARM syntax and encoding
SXTH <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
12 11 10 9 8 7 6 5 4
3
0
1110011010111111
Rd
00000111
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-121
Thumb Instructions
A7.1.72 TST
15 14 13 12 11 10 9 8 7 6 5 3 2 0
0
1
0
0
0
0
1
0
0
0
Rm
Rn
TST (Test) determines whether a particular subset of bits in a register includes at least one set bit. A very common use for TST is to test whether a single bit is set or clear.
It updates the condition code flags, based on the result.
Syntax
TST <Rn>, <Rm>
where:
<Rn> <Rm>
Is the register containing the first operand for the instruction. Is the register whose value is logically ANDed with the value of <Rn>.
Architecture version
All T variants.
Exceptions
None.
Operation
alu_out = Rn AND Rm N Flag = alu_out[31] Z Flag = if alu_out == 0 then 1 else 0 C Flag = unaffected V Flag = unaffected
Equivalent ARM syntax and encoding
TST <Rn>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19
16 15
12 11 10 9 8
76543
0
111000010001
Rn
SBZ
00000000
Rm
A7-122
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.1.73 UXTB
15 14 13 12 11 10 9 8 7 6 5 3 2 0
1
0
1
1
0
0
1
0
1
1
Rm
Rd
UXTB (Unsigned Extend Byte) extracts the least significant 8 bits of the operand, and zero extends the value to 32 bits.
Syntax
UXTB <Rd>, <Rm>
where:
<Rd> <Rm>
Specifies the destination register. Specifies the operand register.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
Rd = Rm AND 0x000000ff
Usage
Use UXTB to zero extend a halfword to a word, for example in instruction sequences acting on unsigned short values in C/C++.
Equivalent ARM syntax and encoding
UXTB <Rd>, <Rm>
31
28 27 26 25 24 23 22 21 20 19 18 17 16 15
12 11 10 9 8 7 6 5 4
3
0
1110011011101111
Rd
00000111
Rm
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-123
Thumb Instructions
A7.1.74 UXTH
15 14 13 12 11 10 9 8 7 6 5 3 2 0
1
0
1
1
0
0
1
0
1
0
Rm
Rd
UXTH (Unsigned Extend Halfword) extracts the least significant 16 bits of the operand, and zero extends the value to 32 bits.
Syntax
UXTH <Rd>, <Rm>
where:
<Rd> <Rm>
Specifies the destination register. Specifies the operand register.
Architecture version
ARMv6 and above.
Exceptions
None.
Operation
Rd = Rm AND 0x0000ffff
Usage
Use UXTH to zero extend a halfword to a word, for example in instruction sequences acting on unsigned short values in C/C++.
Equivalent ARM syntax and encoding
UXTH <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
12 11 10 9 8
76543
0
1110011011111111
Rd
00000111
Rm
A7-124
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Thumb Instructions
A7.2
Thumb instructions and architecture versions
Table A7-1 shows which Thumb instructions are present in each current ARM architecture version that supports Thumb. Table A7-1 Thumb instructions by architecture Instruction
ADC ADD (all forms) AND ASR (both forms) B (both forms) BIC BKPT BL BLX (both forms) BX CMN CMP (all forms) CPS CPY EOR LDMIA LDR (all forms) LDRB (both forms) LDRH (both forms) LDRSB LDRSH LSL (both forms)
v4T Yes Yes Yes Yes Yes Yes No Yes No Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes
v5T Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes
v6 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
A7-125
Thumb Instructions
Table A7-1 Thumb instructions by architecture (continued) Instruction
LSR (both forms) MOV (all forms) MUL MVN NEG ORR POP PUSH REV (all forms) ROR SBC SETEND STMIA STR (all forms) STRB (both forms) STRH (both forms) SUB (all forms) SWI SXTB/H TST UXTB/H
v4T Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes Yes Yes No Yes No
v5T Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes Yes Yes No Yes No
v6 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
A7-126
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Part B
Memory and System Architectures
Chapter B1 Introduction to Memory and System Architectures
This chapter provides a high-level overview of memory and system architectures. It contains the following sections: About the memory system on page B1-2 Memory hierarchy on page B1-4 L1 cache on page B1-6 L2 cache on page B1-7 Write buffers on page B1-8 Tightly Coupled Memory on page B1-9 Asynchronous exceptions on page B1-10 Semaphores on page B1-12.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B1-1
Introduction to Memory and System Architectures
B1.1
About the memory system
The ARM architecture has evolved over many years. Over a billion ARM processors have shipped in this period, the vast majority of these were ARMv4 or ARMv5 compliant. The memory system requirements of these applications vary considerably, from simple memory blocks with a flat address map, to systems using any or all of the following to optimize their use of memory resources: multiple types of memory caches write buffers virtual memory and other memory remapping techniques. Memory system control has primarily been described through the cacheable and bufferable attributes. These attributes derived their names from the underlying hardware mechanisms, without any formal description of the properties associated with the mechanisms on which the programmer could rely. In addition, the order model of the memory accesses made was not defined. An implicit model evolved from early implementations, which were much simpler systems than those being developed today. To meet the demands of higher performance systems and their associated implementations, ARMv6 introduces new disciplines for virtual memory systems and a weakly-ordered memory model including an additional memory barrier command. Memory behavior is now classified by type: strongly ordered device normal. These basic types can be further qualified by cacheable and shared attributes as well as access mechanisms. As in the second edition of the ARM Architecture Reference Manual, general requirements are described in keeping with the diversity of needs, however, emphasis is given to the ARMv6 virtual memory model and its absolute requirements. The virtual memory support mechanisms associated with earlier variants are described in the backwards compatibility model. Some earlier features are deprecated, and therefore not recommended for use in new designs. Coprocessor 15 (CP15) remains the primary control mechanism for virtual memory systems, as well as identification, configuration and control of other memory configurations and system features. CP15 provision is a requirement of ARMv6. The Memory System and Memory Order Model is described in Part B as a series of chapters as follows: Introduction This chapter. Memory hierarchy An overview including basic cache theory and the concept of tightly coupled memory. Memory Order Model Memory attributes and order rules introduced with ARMv6.
B1-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to Memory and System Architectures
The System Control coprocessor An overview of the features and support provided. Virtual Memory System Architecture (VMSA) A sophisticated system to control virtual-to-physical address mapping, access permissions to memory, and other memory attributes, based on the use of a Memory Management Unit (MMU). The revised ARMv6 model, and the model used by earlier architecture variants, are described. Protected Memory System Architecture (PMSA) An alternative, simpler protection mechanism suitable for many applications that do not require the full facilities provided by the MMU memory system. The revised ARMv6 and earlier architecture variant models are described. Caches and Write buffers Mechanisms provided to control cache and write buffer functionality in a memory hierarchy. L1 Tightly Coupled Memory Support ARMv6 provision including the associated DMA and Smartcache models. Fast Context Switch Extension Describes the Fast Context Switch Extension. This facilitated fast switching between up to 128 processes executing in separate process blocks, each of size up to 32 MB. This is supported in ARMv6 only for backwards compatibility, and its use is deprecated.
Note
Part B describes a wide variety of functionality. ARMv6 is the first architecture variant to standardize the memory model and many system level features. It is the first architecture variant to mandate provision of the System Control coprocessor, and a level of consistency at the system level for hardware and software design. Because of this, ARMv6 is considered a watershed in terms of how material is presented in Part B. Absolute requirements are provided for ARMv6 compliant implementations, whereas information can only be considered as system guidelines for earlier architecture variants. It is assumed that all versions of the architecture prior to version 4 are now OBSOLETE. For example, all references to 26-bit mode have been removed. Some ARM processors prior to ARMv6 have implemented functions in a different manner from those described here. Because of this, the datasheet or Technical Reference Manual for a particular ARM processor is the definitive source of information for memory and system control facilities. Processors which have followed the guidelines are more likely to be compatible with existing and future ARM software. ARMv6 establishes a baseline for system design, but there will always be additional functionality and areas of implementation dependent options. The system designer is strongly encouraged to read the architecture in conjunction with vendor datasheets for optimal system design and performance.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B1-3
Introduction to Memory and System Architectures
B1.2
Memory hierarchy
Good system design is a balance of many trade-offs to achieve the overall system performance and cost goals. An important part of this decision process is the memory provision: types of memory, for example ROM, Flash, DRAM, SRAM, disk based storage size - capacity and silicon area access speed - core clock cycles required to read or write a location architecture - Harvard (separate instruction and data memories) or Von Neumann (unified memory). As a general rule, the faster the memory access time, the more constrained the amount of resource available, because it needs to be closely coupled to the processor core, that is, on the same die. Even on-chip memory may have different timing requirements because of its type or size, power constraints, and the associated critical path lengths to access it in the physical layout. Caches provide a means to share the fastest, most expensive system memory resources between the currently active process threads in an application. Where a system is designed with different types of memory in a layered model, this is referred to as a memory hierarchy. Systems can employ caches at multiple levels. The outer layers trade increased latency for increasing size. All the caches in the system must adhere to a memory coherency policy, which is part of the system architecture. Such layered systems usually number the layers - level 1, level 2 ... level n- with the increasing numbers representing increased access times for layers further from the core. IO can also be provided at the different layers, that is, some no-wait-state register-based peripherals at level 1, out to memory mapped peripherals on remote system buses. Figure B1-1 shows an example memory hierarchy.
Virtual address
Address Translation
Physical address
CP15 configuration/ control ARM Core R15 . . . R0 Instruction Prefetch Load Store
Level 1 Cache(s)
Level 2 Caches
Level 3 DRAM SRAM Flash ROM
Tightly Coupled Memory TCM(s)
Level 4 (for example, CF card, disk)
Figure B1-1 Memory hierarchy example
B1-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to Memory and System Architectures
The ARMv6 specifies the Level 1 (L1) subsystem, providing cache, Tightly-Coupled Memory (TCM), and an associated TCM-L1 DMA system. The architecture permits a range of implementations, with software visible configuration registers to allow identification of the resources that exist. Options are provided to support the L1 subsystem with a Memory Management Unit (VMSAv6) or a simpler Memory Protection Unit (PMSAv6). Some provision is also made for multiprocessor implementations and Level 2 (L2) caches. However, these are not fully specified in this document. To ensure future compatibility, it is recommended that Implementors of L2 caches and closely-coupled multiprocessing systems work closely with ARM. VMSAv6 describes Inner and Outer attributes which are defined for each page-by-page. These attributes are used to control the caching policy at different cache levels for different regions of memory. Implementations can use the Inner and Outer attributes to describe caching policy at other levels in an IMPLEMENTATION DEFINED manner. See sections Memory region attributes on page B4-11 for the architecture details. All levels of cache need appropriate cache management and must support: cache cleaning (write-back caches only) cache invalidation (all caches). ARM processors and software are designed to be connected to a byte-addressed memory. Prior to ARMv6, addressing was defined as word invariant. Word and halfword accesses to the memory ignored the byte alignment of the address, and accessed the naturally-aligned value that was addressed, that is, a memory access ignored address bits 0 and 1 for word access, and ignored bit 0 for halfword accesses. The endianness of the ARM processor normally matched that of the memory system, or was configured to match it before any non-word accesses occurred. ARMv6 introduces: a byte-invariant address model support of unaligned word and halfword accesses additional control features for loading and storing data in a little or big endian manner. See Endian support on page A2-30 for details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B1-5
Introduction to Memory and System Architectures
B1.3
L1 cache
Before ARMv6, ARM caches were normally implemented as virtually addressed caches, with virtual indexing and virtual address tags. With this model, physical pages were only mapped into a single virtual page, otherwise the result was UNPREDICTABLE. These implementations did not provide coherence between multiple virtual copies of a single physical page. ARMv6 specifies a cache architecture where the expected behavior is that normally associated with physically tagged caches. The ARMv6 L1 cache architecture is designed to reduce the requirement for cache clean and/or invalidation on a context switch, and to support multiple virtual address aliases to a particular memory location. Flexibility on the size, associativity or organization of the caches within this subsystem is provided in the Coprocessor System Control Register (CP15). The cache organization may be a Harvard architecture with separate instruction and data caches, or a von Neumann architecture with a single, unified cache. In a Harvard architecture, an implementation does not need to include hardware support for coherency between the Instruction and Data caches. Where such support would be required, for example, in the case of self-modifying code, the software must make use of the cache cleaning instructions to avoid such problems. An ARMv6 L1 cache must appear to software to behave as follows: the entries in the cache do not need to be cleaned and/or invalidated by software for different virtual to physical mappings aliases to the same physical address may exist in memory regions that are described in the page tables as being cacheable, subject to the restrictions for 4KB small pages outlined in Restrictions on Page Table Mappings on page B6-11.
Caches can be implemented with virtual or physical addressing (including indexing) provided these behavior requirements are met. ARMv6 L1 cache management uses virtual addresses, which is consistent with earlier architecture guidelines and implementations. For architecture details on the L1 cache see Chapter B6 Caches and Write Buffers.
B1-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to Memory and System Architectures
B1.4
L2 cache
L1 caches are always tightly coupled to the core, but L2 caches can be either: tightly coupled to the core implemented as memory mapped peripherals on the system bus. A recommended minimum set of L2 cache commands is defined for configuration and control. Closely-coupled L2 caches must be managed through the System Control Coprocessor. It is IMPLEMENTATION DEFINED whether they use virtual or physical addresses for control functions. Memory mapped L2 caches must use physical address based control. Further levels of cache are possible, but their control is not mandated within ARMv6 except that they must comply with: the inner and outer attribute model described in Memory region attributes on page B4-11. coherency needs associated with managing multi-level caches through the System Control Coprocessor interface, see Considerations for additional levels of cache on page B6-12.
For architecture details on the L2 cache see section L2 cache.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B1-7
Introduction to Memory and System Architectures
B1.5
Write buffers
The term write buffer can cover a number of different behaviors. The effects of these behaviors on different uses of memory mapped space needs to be understood by the programmer to avoid unexpected results. For this reason, the term bufferable is no longer used as an attribute to describe the required behavior of a memory system. A write buffer exists to decouple a write transaction from the execution of subsequent memory transactions. In addition, particular buffer implementations may perform additional tasks such as the re-ordering of memory transfers, the merging of multiple writes into proximate locations, or the forwarding of write data to subsequent reads. These buffering behaviors are becoming more cache-like in nature. The memory attributes Strongly Ordered, Device, and Normal described in Strongly Ordered memory attribute on page B2-12 are designed to allow the programmer to describe the required behavior, leaving the Implementor free to choose whatever structures are optimal for a given system, provided that the behavior for each memory attribute is correctly fulfilled. For writes to buffered areas of memory, precise aborts can only be signaled to the processor as a result of conditions that are detectable at the time the data is placed in the write buffer. Conditions that can only be detected when the data is later written to main memory, such as an ECC error from main memory, must be handled by other methods, by raising an interrupt or an imprecise abort.
B1-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to Memory and System Architectures
B1.6
Tightly Coupled Memory
The Tightly Coupled Memory (TCM) is an area of memory that can be implemented alongside the L1 cache, as part of the level 1 memory subsystem. The TCM is physically addressed, with each bank occupying a unique part of the physical memory map. See SmartCache Behavior on page B7-6 for an optional, smartcache, ARMv6 usage model. In keeping with the L1 cache, the TCM may be structured as a Harvard architecture with separate instruction and data TCM, or as a Von Neumann architecture with a unified TCM. The TCM is designed to provide low latency memory that can be used by the processor without the unpredictability that is a feature of caches. Such memory can be used to hold critical routines, such as interrupt handling routines or real-time tasks, where the indeterminacy of a cache would be highly undesirable. Other example uses are: scratchpad data data types whose locality properties are not well suited to caching critical data structures such as Interrupt stacks. For architectural details on TCM, see Chapter B7 Tightly Coupled Memory.
B1.6.1
Tightly Coupled Memory versus cache memory
The TCM is designed to be used as part of the physical memory map of the system, and is not expected to be backed by a level of external memory with the same physical addresses. For this reason, the TCM behaves differently from the caches for regions of memory which are marked as being Write-Through cacheable. In such regions, no external writes occur in the event of a write to memory locations contained in the TCM. It is an architectural requirement that memory locations are contained either in the TCM or the cache, not in both. In particular, no coherency mechanisms are supported between the TCM and the cache. This means that it is important when allocating the base address of the TCM to ensure that the TCM address range does not overlap with any valid cache entries.
B1.6.2
DMA support for Tightly Coupled Memory
ARMv6 includes a DMA model with register support for its configuration. This is the only mechanism other than the associated processor core that can read and write the TCM. Up to two DMA channels are provided for. This allows chained operations, see Level 1 (L1) DMA model on page B7-8 for architectural details.
Note
The TCM DMA mechanism and smartcache functionality described in SmartCache Behavior on page B7-6 are mutually exclusive.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B1-9
Introduction to Memory and System Architectures
B1.7
Asynchronous exceptions
Many exceptions are synchronous events related to instruction execution in the core. However, the following exceptions cause asynchronous events to occur: Reset on page A2-18 Interrupts Imprecise aborts on page B1-11.
B1.7.1
Reset
This is the only non-maskable event in the ARM architecture. See Reset on page A2-18 for more information.
B1.7.2
Interrupts
ARM processors implement fast and normal levels of interrupt. Both interrupts are signaled externally, and many implementations synchronize interrupts before an exception is raised. Fast interrupt request (FIQ) Disables subsequent normal and fast interrupts by setting the I and F bits in the CPSR. Non-maskable (by software) fast interrupt request Same as FIQ, except the F bit in the CPSR can only be set by hardware on exception entry. Software can only (re)enable the interrupt mechanism. Normal interrupt request (IRQ) Disables subsequent normal interrupts by setting the I bit in the CPSR. Some implementations incorporate a mechanism controlled by the System Control Coprocessor to return interrupt vectors directly to the core. The mechanism typically applies to the IRQ mode, but can also apply to FIQ mode. The exact behavior is IMPLEMENTATION DEFINED. For more information on interrupts, see Interrupt request (IRQ) exception on page A2-24, Fast interrupt request (FIQ) exception on page A2-24, and Vectored interrupt support on page A2-26.
Cancelling interrupts
It is the responsibility of software (the interrupt handler) to ensure that the cause of an interrupt is cancelled (no longer signaled to the processor) before interrupts are re-enabled (by clearing the I or F bit, or both, in the CPSR). Interrupts can be cancelled with any instruction that might make an explicit data access, that is: any load any store a swap any coprocessor instruction.
B1-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Introduction to Memory and System Architectures
The latency between the memory or coprocessor operation to cancel an interrupt and the point at which the interrupt masks (I and F) in the CPSR can be cleared is IMPLEMENTATION DEFINED. In particular, the ARMv6 memory types do not include a type whose accesses are architecturally guaranteed to complete before the execution of a following instruction. As a result, the architected mechanism to ensure the cancelling of an interrupt is to poll an IMPLEMENTATION DEFINED location dedicated to each interrupt cancelling mechanism, in order to ensure that the interrupt has been cancelled before the interrupt mask is cleared.
B1.7.3
Imprecise aborts
ARMv6 has introduced the concept of imprecise aborts. These aborts can occur after the instruction that caused the abort has been retired. Therefore an imprecise abort is fatal, at least to the process that caused it, or requires external resources to record address, data and control information for a software recovery. These aborts are masked on entry to most exception vectors, and can be masked by privileged software using the CPSR_A bit. See Exceptions on page A2-16 for more information.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B1-11
Introduction to Memory and System Architectures
B1.8
Semaphores
The Swap (SWP) and Swap Byte (SWPB) instructions need to be used with care to ensure that expected behavior is observed. Two examples are as follows: Systems with multiple bus masters that use the Swap instructions to implement semaphores to control interaction between different bus masters. In this case, the semaphores must be placed in an uncached region of memory, where any buffering of writes occurs at a point common to all bus masters using the mechanism. The Swap instruction then causes a locked read-write bus transaction. This type of semaphore can be externally aborted. Systems with multiple threads running on a uniprocessor that use the Swap instructions to implement semaphores to control interaction of the threads. In this case, the semaphores can be placed in a cached region of memory, and a locked read-write bus transaction might or might not occur. The Swap and Swap Byte instructions are likely to have better performance on such a system than they do on a system with multiple bus masters (as described above). This type of semaphore has UNPREDICTABLE behavior if it is externally aborted. From ARMv6, load and store exclusive instructions (LDREX and STREX) are the preferred method of implementing semaphores for system performance reasons. The new mechanism is referred to as synchronization primitives, and requires data monitor logic within the memory system that monitors access to the requested location from all sources in the shared memory model case. The instructions provide a degree of decoupling between the load and store elements, with the store only being successful if no other resource has written to the location since its associated load. See Synchronization primitives on page A2-44 for more details.
Note
The Swap and Swap Byte instructions are deprecated in ARMv6.
B1-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Chapter B2 Memory Order Model
This chapter provides a high-level overview of the memory order model. It contains the following sections: About the memory order model on page B2-2 Read and write definitions on page B2-4 Memory attributes prior to ARMv6 on page B2-7 ARMv6 memory attributes - introduction on page B2-8 Ordering requirements for memory accesses on page B2-16 Memory barriers on page B2-18 Memory coherency and access issues on page B2-20.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-1
Memory Order Model
B2.1
About the memory order model
The architecture prior to ARMv6 did not attempt to define the acceptable memory ordering of explicit memory transactions, describing the regions of memory according to the hardware approaches that had previously been used to implement such memory systems. Thus regions of memory had been termed as being one of Write-Through Cacheable, Write-Back Cacheable, Non-Cacheable Bufferable or Non-Cacheable, Non-Bufferable. These terms are based on the previous hardware implementations of cores and the exact properties of the memory transactions could not be rigorously inferred from the memory names. Implementations have chosen to interpret these names in different ways, leading to potentially incompatible uses. In a similar manner, the order in which memory accesses could be presented to memory was not defined, and in particular there was no definition of what order could be relied upon by an observer of the memory transactions generated by a processor. As implementations and systems become more complicated, these undefined areas of the architecture move from being simply based on a standard default to having the potential of presenting significant incompatibilities between different implementations; at processor core and system level. ARMv6 introduces a set of memory types - Normal, Device, and Strongly Ordered - with memory access properties defined to fit in a largely backwards compatible manner to the defacto meanings of the original memory regions. A potential incompatibility has been introduced with the need for a software polling policy when it is necessary for the program to be aware that memory accesses to I/O space have completed, and all side effects are visible across the whole system. This reflects the increasing difficulty of ensuring linkage between the completion of memory accesses and the execution of instructions within a complex high-performance system. A shared memory attribute to indicate whether a region of memory is shared between multiple processors (and therefore requires an appearance of cache transparency in an ordering model) is also introduced. Implementations remain free to choose the mechanisms to implement this functionality. The key issues with the memory order model are slightly different depending on the target audience: for software programmers, the key factor is that side effects are only architecturally visible after software polling of a location that indicates that it is safe to proceed for silicon Implementors, the Strongly Ordered and Device memory attributes defined in this chapter place certain restrictions on the system designer in terms of what they are allowed to build, and when to indicate completion of a transaction.
Additional attributes and behaviors relate to the memory system architecture. These features are defined in other areas of this manual: Virtual memory systems based on an MMU described in Chapter B4 Virtual Memory System Architecture. Protected memory systems based on an MPU described in Chapter B5 Protected Memory System Architecture. Caches and write buffers described in Chapter B6 Caches and Write Buffers. Tightly Coupled Memory (TCM) described in Chapter B7 Tightly Coupled Memory
B2-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
Some attributes are described in relation to an MMU for ARMv6. In general, these can also be applied to an MPU based system.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-3
Memory Order Model
B2.2
Read and write definitions
Memory accesses can be either reads or writes.
B2.2.1
Reads
Reads are defined as memory operations that have the semantics of a load. In the ARM instruction set, these are: LDM, LDRH, LDRSH, LDRB, LDRSB LDM, LDRD, LDRT, LDRBT, LDC, RFE, SWP, SWPB, LDREX, STREX. In the Thumb instruction set, they are: LDR, LDRH, LDRSH, LDRB, LDRSB LDM, POP. Jazelle opcodes that are accelerated by hardware can cause a number of reads to occur, according to the state of the operand stack and the implementation of the Jazelle hardware acceleration.
B2.2.2
Writes
Writes are defined as operations that have the semantics of a store. In the ARM instruction set, these are: STR, STRH, STRB STM, STRD, STRT, STRBT STC, SRS, SWP, SWPB, STREX In the Thumb instruction set, they are: STR, STRH, STRB STM, PUSH Jazelle opcodes that are accelerated by hardware can cause a number of writes to occur, according to the state of the operand stack and the implementation of the Jazelle hardware acceleration.
B2.2.3
Memory synchronization primitives
Synchronization primitives are required to ensure correct operation of system semaphores within the memory order model. The memory synchronization primitive instructions are defined as those instructions that are used to ensure memory synchronization: LDREX, STREX SWP, SWPB (deprecated in ARMv6). Prior to ARMv6, support consisted of the SWP and SWPB instructions. ARMv6 has introduced new LDREX and STREX (Load and Store Exclusive) instructions. See Memory barriers on page B2-18 for the architecture details.
B2-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
LDREX and STREX are supported to shared and non-shared memory. Non-shared memory can be used when the processes to be synchronized are running on the same processor. When the processes to be synchronized are running on different processors, shared memory must be used.
B2.2.4
Observability and completion
The concept of observability applies to all memory, however, the concept of global observability only applies to shared memory. Normal, Device and Strongly Ordered memory are defined in ARMv6 memory attributes - introduction on page B2-8. For all memory: A write to a location in memory is said to be observed by a memory system agent when a subsequent read of the location by the same memory system agent returns the value written by the write. A write to a location in memory is said to be globally observed when a subsequent read of the location by any memory system agent returns the value written by the write. A read to a location in memory is said to be observed by a memory system agent when a subsequent write of the location by the same memory system agent has no effect on the value returned by the read. A read to a location in memory is said to be globally observed when a subsequent write of the location by any memory system agent has no effect on the value returned by the read.
Additionally, for Strongly Ordered memory: A read or write to a memory mapped location in a peripheral which exhibits side-effects is said to be observed, and globally observed, only when the read or write meets the general conditions listed, can begin to affect the state of the memory-mapped peripheral, and can trigger any side effects that affect other peripheral devices, cores and/or memory.
For all memory, the completion rules are: A read or write is defined to be complete when it is globally observed and any page table walks associated with the read or write are complete. A page table walk is defined to be complete when the memory transactions associated with the page table walk are globally observed, and the TLB is updated. A cache, branch predictor or TLB maintenance operation is defined to be complete when the effects of operation are globally observed and any page table walks which arise are complete.
Note
For all memory-mapped peripherals, where the side-effects of a peripheral are required to be visible to the entire system, the peripheral must provide an IMPLEMENTATION DEFINED location which can be read to determine when all side effects are complete.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-5
Memory Order Model
Side effect completion in Strongly Ordered and Device memory
To determine when any side effects have completed, it is necessary to poll a location associated with the device, for example, a status register. This is a key element of the architected memory order model.
B2-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
B2.3
Memory attributes prior to ARMv6
Prior to ARMv6, all memory has been tagged with a combination of two control bits in the ARM virtual and protected memory management models, VMSA and PMSA respectively. The bits are: a bufferable (B) bit (allow write buffering between the core and memory) a cacheable (C) bit. These are traditionally interpreted to define the memory behavior of a given location as shown in Table B2-1. Table B2-1 Interpretation of cacheable and bufferable bits C 0 0 1 1 B 0 1 0 1 Write-through cache Uncached/unbuffered Uncached/buffered
IMPLEMENTATION DEFINED
Write-back only cache Uncached/unbuffered Uncached/buffered
UNPREDICTABLE
Write-back/write-through cache Uncached/unbuffered Uncached/buffered Write-through cached/buffered Write-back cached/buffered
Cached/buffered
Cached/buffered
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-7
Memory Order Model
B2.4
ARMv6 memory attributes - introduction
ARMv6 defines a set of memory attributes with the characteristics required to support all memory and devices in the system memory map. The ordering of accesses for regions of memory is also defined by the memory attributes. There are three mutually exclusive main memory type attributes to describe the memory regions: Normal Device Strongly Ordered. Normal memory is idempotent, exhibiting the following properties: write transactions can be repeated with no side effects repeated read transactions return the last value written to the resource being read transactions can be restarted if interrupted multibyte accesses need not be atomic, and can be restarted or replayed unaligned accesses can be supported transactions can be merged prior to accessing the target memory system read transactions can prefetch additional memory locations with no side effects. System peripherals (I/O) generally conform to different access rules; defined in ARMv6 as Strongly Ordered or Device memory. Examples of I/O accesses are: FIFOs where consecutive accesses add (write) or remove (read) queued values interrupt controller registers where an access can be used as an interrupt acknowledge changing the state of the controller itself memory controller configuration registers that are used to set up the timing (and correctness) of areas of normal memory memory-mapped peripherals where the accessing of memory locations causes side effects within the system.
To ensure system correctness, access rules are more restrictive than those to normal memory: accesses (reads and writes) can have side effects transactions must not be repeated, for example, on return from an exception transaction number, size and order must be maintained. In addition, the Shared attribute indicates whether the memory is private to a single processor, or accessible from multiple processors or other bus master resources, for example, an intelligent peripheral with DMA capability. Table B2-2 on page B2-9 shows a summary of the memory attributes.
B2-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
Table B2-2 Memory attribute summary Memory type attribute Strongly Ordered Shared attribute Other attributes Description All memory accesses to Strongly Ordered memory occur in program order. All Strongly Ordered accesses are assumed to be Shared. Designed to handle memory mapped peripherals that are shared by several processors. Designed to handle memory mapped peripherals that are used only by a single processor. Non-cacheable/ Write-Through cacheable/ Write-Back cacheable Non-cacheable/ Write-Through cacheable/ Write-Back cacheable Designed to handle normal memory which is shared between several processors.
Device
Shared Non-Shared
Normal
Shared
Non-Shared
Designed to handle normal memory which is used only by a single processor.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-9
Memory Order Model
B2.4.1
Normal memory attribute
This attribute is defined for each page in an MMU, can be further defined as being Shared or Non-Shared, and describes most memory used in a system. It is designed to provide memory access orderings that are suitable for Normal memory. Such memory stores information without side effects. Normal memory may be read/write or read-only. For writable Normal memory unless there is a change to the physical address mapping: A load from a specific location will return the most recently stored data at that location for the same processor. Two loads from a specific location, without a store in between, will return the same data for each load.
For read-only Normal memory: Two loads from a specific location will return the same data for each load.
Accesses to Normal Memory conform to the weakly-ordered model of memory ordering. A description of the weakly-ordered model can be found in standard texts describing memory ordering issues. A recommended text is chapter 2 of Memory Consistency Models for Shared Memory-Multiprocessors, Kourosh Gharachorloo, Stanford University Technical Report CSL-TR-95-685. All explicit accesses must correspond to the ordering requirements of accesses described in Ordering requirements for memory accesses on page B2-16.
Non-shared Normal memory
The Non-Shared Normal memory attribute is designed to describe normal memory that can be accessed only by a single processor. A region of memory marked as Non-Shared Normal does not have any requirement to make the effect of a cache transparent. For regions of memory marked as Non-shared Non-cacheable, a DMB memory barrier must be used in situations where the forwarding of data from the internal buffering of previous accesses within the single processor is required.
Shared Normal memory
The Shared Normal memory attribute is designed to describe normal memory that can be accessed by multiple processors or other system masters. A region of memory marked as Shared Normal is one in which the effect of interposing a cache (or caches) on the memory system is entirely transparent to data accesses. Explicit software management is still required to ensure coherency of instruction caches. Implementations can use a variety of mechanisms to support this, from very simply not caching accesses in shared regions to more complex hardware schemes for cache coherency for those regions. Writes to Shared Normal Memory may not be atomic, that is, all observers might not see the writes occurring at the same time. To preserve coherence where two writes are made to the same location, it is required that the order of those writes is seen to be the same by all observers. Reads to Shared Normal Memory that are aligned in memory to the size of the access must be atomic.
B2-10 Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved. ARM DDI 0100I
Memory Order Model
Cacheable write-through, cacheable write-back and non-cacheable memory
In addition to marking a region of normal memory as being Shared or Non-Shared, each page of memory marked in an MMU as Normal can also be marked as being one of: cacheable write-through cacheable write-back non-cacheable. This marking is independent of the marking of a region of memory as being Shared or Non-Shared. It indicates the required handling of the data region for reasons other than those to handle the requirements of shared data. As a result, it is acceptable for a region of memory that is marked as being cacheable and shared not to be held in the cache in an implementation which handles shared regions as not caching the data. If the same memory locations are marked as having different cacheable attributes, for example by the use of synonyms in a virtual to physical address mapping, UNPREDICTABLE behavior results.
B2.4.2
Device memory attribute
The Device memory attribute is defined for memory locations where an access to the location can cause side effects, or where the value returned for a load can vary depending on the number of loads performed. Memory mapped peripherals and I/O locations are typical examples of areas of memory that should be marked as being Device. The Device attribute is defined for each page in an MMU. Explicit accesses from the processor to regions of memory marked as Device occur at the size and order defined by the instruction. The number of accesses that occur to such locations is the number that is specified by the program. Implementations must not repeat accesses to such locations when there is only one access in the program, that is, the accesses are not restartable. An example where an implementation might want to repeat an access is before and after an interrupt, in order to allow the interrupt to cause a slow access to be abandoned. Such implementation optimizations must not be performed for regions of memory marked as Device. In addition, address locations marked as Device are non-cacheable. While writes to device memory may be buffered, writes shall only be merged where the correct number of accesses, order, and their size is maintained. Multiple accesses to the same address cannot change the number of accesses to that address. Coalescing of accesses is not permitted in this case. Accesses to memory mapped locations that have side effects that apply to Normal memory locations require Memory Barriers to ensure correct execution. An example is the programming of the configuration registers of a memory controller with respect to the memory accesses it controls. All explicit accesses to memory marked as Device must correspond to the ordering requirements of accesses described in Ordering requirements for memory accesses on page B2-16.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-11
Memory Order Model
Shared attribute
The Shared attribute is defined for each page in an MMU. These regions can be referred to as: memory marked as Shared Device memory marked as Non-Shared Device. Memory marked as Non-Shared Device is defined as only accessible by a single processor. An example of a system supporting Shared and Non-shared Device memory is an implementation that supports a local bus for its private peripherals, whereas system peripherals are situated on the main (Shared) system bus. Such a system might have more predictable access times for local peripherals such as watchdog timers or interrupt controllers.
B2.4.3
Strongly Ordered memory attribute
The Strongly Ordered memory attribute is defined for each page in the MMU. Accesses to memory marked as Strongly Ordered have a strong memory-ordering model for all explicit memory accesses from that processor. An access to memory marked as Strongly Ordered is required to act as if a DMB memory barrier were inserted before and after the access from that processor. See DataMemoryBarrier (DMB) CP15 register 7 on page B2-18. To maintain backwards compatibility with ARMv5, any ARMv5 instructions that implicitly or explicitly change the interrupt masks in the CSPR and appear in program order after a Strongly Ordered access must wait for the Strongly Ordered memory access to complete. These instructions are MSR, with the control field mask bit set, and the flag-setting variants of arithmetic and logical instructions with R15 as the destination register (these copy the SPSR to CSPR). This requirement exists only for backwards compatibility with previous versions of the ARM architecture; the behavior is deprecated in ARMv6. ARMv6 compliant programs must not rely on this behavior, but instead include an explicit Memory Barrier between the memory access and the following instruction, see DataSynchronizationBarrier (DSB) CP15 register 7 on page B2-18 when synchronization is required. Explicit accesses from the processor to memory marked as Strongly Ordered occur at their program size, and the number of accesses that occur to such locations is the number that are specified by the program. Implementations must not repeat accesses to such locations when there is only one access in the program, that is, the accesses are not restartable. Address locations marked as Strongly Ordered are not held in a cache, and are always treated as Shared memory locations. All explicit accesses to memory marked as Strongly Ordered must correspond to the ordering requirements of accesses described in Ordering requirements for memory accesses on page B2-16.
B2-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
B2.4.4
Memory access restrictions
The following restrictions apply to memory accesses: For any access X, the bytes accessed by X must all have the same memory type attribute, otherwise, the behavior of the access is UNPREDICTABLE. That is, unaligned accesses that span a boundary between different memory types are UNPREDICTABLE. For any two memory accesses X and Y, such that X and Y are generated by the same instruction, X and Y must all have the same memory type attribute, otherwise, the results are UNPREDICTABLE. For example, an LDC, LDM, LDRD, STC, STM, or STRD that spans a boundary between Normal and Device memory is UNPREDICTABLE. Instructions that generate unaligned memory accesses to Device or Strongly Ordered memory are
UNPREDICTABLE.
Memory operations which cause multiple transactions to Device or Strongly Ordered memory should not crosses a 4KB address boundary to ensure access rules are maintained. For this reason, it is important that accesses to volatile memory devices are not made using single instructions that cross a 4KB address boundary. This restriction is expected to cause restrictions to the placing of such devices in the memory map of a system, rather than to cause a compiler to be aware of the alignment of memory accesses. For instructions that generate accesses to Device or Strongly Ordered memory, implementations do not change the sequence of accesses specified by the pseudo-code of the instruction. This includes not changing how many accesses there are, nor their time order, nor the data sizes and other properties of each individual access. Furthermore, processor core implementations expect any attached memory system to be able to identify accesses by memory type, and to obey similar restrictions with regard to the number, time order, data sizes and other properties of the accesses. Exceptions to this rule are: An implementation of a processor core can break this rule, provided that the information it does supply to the memory system enables the original number, time order, and other details of the accesses to be reconstructed. In addition, the implementation must place a requirement on attached memory systems to do this reconstruction when the accesses are to Device or Strongly Ordered memory. For example, the word loads generated by an LDM might be paired into 64-bit accesses by an implementation with a 64-bit bus. This is because the instruction semantics ensure that the 64-bit access is always a word load from the lower address followed by a word load from the higher address, provided a requirement is placed on memory systems to unpack the two word loads where the access is to Device or Strongly Ordered memory. Any implementation technique that produces results that cannot be observed to be different from those described above is legitimate.
Multi-access instructions that load or store R15 must only access normal memory. If they access Device or Strongly Ordered memory the results are UNPREDICTABLE.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-13
Memory Order Model
Instruction fetches must only access normal memory. If they access Device or Strongly Ordered memory, the results are UNPREDICTABLE. By example, instruction fetches must not be performed to areas of memory containing read-sensitive devices, because there is no ordering requirement between instruction fetches and explicit accesses. If the same memory location is marked as Shared Normal and Non-Shared Normal in a MMU, for example by the use of synonyms in a virtual to physical address mapping, UNPREDICTABLE behavior results. If the same memory locations are marked as having different memory types (Normal, Device, or Strongly Ordered), for example by the use of synonyms in a virtual to physical address mapping, UNPREDICTABLE behavior results. If the same memory locations are marked as having different cacheable attributes, for example by the use of synonyms in a virtual to physical address mapping, UNPREDICTABLE behavior results. If the same memory location is marked as being Shared Device and Non-Shared Device in an MMU, for example by the use of synonyms in a virtual to physical address mapping, UNPREDICTABLE behavior results.
Note
Implementations must also ensure that prefetching down non-sequential paths, for example, as a result of a branch predictor, cannot cause unwanted accesses to read-sensitive devices. Implementations may prefetch by an IMPLEMENTATION DEFINED amount down a sequential path from the instruction currently being executed. Prior to ARMv6, it is IMPLEMENTATION DEFINED whether a low interrupt latency mode is supported. From ARMv6, low interrupt latency support is controlled from the System Control coprocessor (FI-bit). It is IMPLEMENTATION DEFINED whether multi-access instructions behave correctly in low interrupt latency configurations.
B2-14
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
B2.4.5
Backwards compatibility
ARMv6 memory attributes are significantly different from those in previous versions of the architecture. Table B2-3 shows the interpretation of the earlier memory types in the light of this definition. Table B2-3 Backwards compatibility Previous architectures NCNB (Non-cacheable, Non-Bufferable) NCB (Non-cacheable, Bufferable) Write-Through cacheable, Bufferable Write-Back cacheable, Bufferable ARMv6 attribute Strongly Ordered a Shared Device a Non-Shared Normal (Write-Through cacheable) Non-Shared Normal (Write-Back cacheable)
a. Memory locations contained within the TCMs are treated as being Non-Cacheable, not Strongly Ordered or Shared Device
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-15
Memory Order Model
B2.5
Ordering requirements for memory accesses
ARMv6 defines access restrictions in the memory ordering allowed, depending on the memory attributes of the accesses involved. Figure B2-1 shows the memory ordering between two explicit accesses A1 and A2, where A1 occurs before A2 in program order. The symbols used in Figure B2-1 are as follows: < (blank) Accesses must be globally observed in program order, that is, A1 must be globally observed strictly before A2. Accesses can be globally observed in any order, provided that the requirements of uniprocessor semantics, for example respecting dependencies between instructions within a single processor, are maintained.
A2 A1 Normal Read Device Read (Non-Shared) Device Read (Shared) Strongly Ordered Read Normal Write Device Write (Non-Shared) Device Write (Shared) Strongly Ordered Write < < < < < < < < < < Normal Read Device Read NonShared Shared Strongly Ordered Read < < < < < < < < < < < < < < < < < < Normal Write Device Write NonShared Shared Strongly Ordered Write < < < < < < < <
Figure B2-1 Memory ordering restrictions There are no ordering requirements for implicit accesses to any type of memory.
B2-16
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
B2.5.1
Program order for instruction execution
Program order of instruction execution is the order of the instructions in the control flow trace. Explicit memory accesses in an execution can be either: Strictly Ordered Ordered Denoted by <. Must occur strictly in order. Denoted by <=. Must occur either in order, or simultaneously.
Multiple load and store instructions, such as LDM, LDRD, STM, and STRD, generate multiple word accesses, each of which is a separate access for the purpose of determining ordering. The rules for determining program order for two accesses A1 and A2 are: If A1 and A2 are generated by two different instructions: A1 < A2 if the instruction that generates A1 occurs before the instruction that generates A2 in program order A2 < A1 if the instruction that generates A2 occurs before the instruction that generates A1 in program order.
If A1 and A2 are generated by the same instruction: If A1 and A2 are the load and store generated by a SWP or SWPB instruction: A1 < A2 if A1 is the load and A2 is the store A2 < A1 if A2 is the load and A1 is the store.
If A1 and A2 are two word loads generated by an LDC, LDRD, or LDM instruction, or two word stores generated by an STC, STRD, or STM instruction, excluding LDM or STM instructions whose register list includes the PC: A1 <= A2 if the address of A1 is less than the address of A2 A2 <= A1 if the address of A2 is less than the address of A1.
If A1 and A2 are two word loads generated by an LDM instruction whose register list includes the PC or two word stores generated by an STM instruction whose register list includes the PC, the program order of the memory operations is not defined. If A1 and A2 are two word loads generated by an LDRD instruction or two word stores generated by an STRD instruction whose register list includes the PC, Rd equals R14 and the instruction is
UNPREDICTABLE.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-17
Memory Order Model
B2.6
Memory barriers
Memory barrier is the general term applied to an instruction, or sequence of instructions, used to force synchronization events by a processor with respect to retiring load/store instructions in a processor core. A memory barrier is used to guarantee completion of preceding load/store instructions to the programmers model, flushing of any prefetched instructions prior to the event, or both. ARMv6 mandates three explicit barrier instructions in the System Control Coprocessor to support the memory order model described in this chapter, and requires these instructions to be available in both privileged and user modes: DataMemoryBarrier as described in DataMemoryBarrier (DMB) CP15 register 7 DataSynchronizationBarrier (DataWriteBarrier) as described in DataSynchronizationBarrier (DSB) CP15 register 7 PrefetchFlush as described in PrefetchFlush CP15 register 7 on page B2-19.
These instructions may be sufficient on their own, or may need to be used in conjunction with cache and memory management maintenance operations; operations which are only available in privileged modes. Support of memory barriers in earlier versions of the architecture is IMPLEMENTATION DEFINED. Explicit memory barriers affect reads and writes to the memory system generated by load and store instructions being executed in the CPU. Reads and writes generated by L1 DMA transactions, and instruction fetches or accesses caused by a hardware page table access, are not explicit accesses.
B2.6.1
DataMemoryBarrier (DMB) CP15 register 7
DMB acts as a data memory barrier, exhibiting the following behavior: All explicit memory accesses by instructions occurring in program order before this instruction are globally observed before any explicit memory accesses due to instructions occurring in program order after this instruction are observed. DataMemoryBarrier has no effect on the ordering of other instructions executing on the processor.
As such, DMB ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. The encoding for DataMemoryBarrier is described in Register 7: cache management functions on page B6-19.
B2.6.2
DataSynchronizationBarrier (DSB) CP15 register 7 Note
This operation has historically been referred to as DrainWriteBuffer or DataWriteBarrier (DWB). From ARMv6, these names (and the use of DWB) are deprecated in favor of the new DataSynchronizationBarrier name and DSB. DSB better reflects the functionality provided in ARMv6; it is architecturally defined to include all cache, TLB and branch prediction maintenance operations as well as explicit memory operations.
B2-18
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
The DataSynchronizationBarrier operation acts as a special kind of memory barrier. The DSB operation completes when: All explicit memory accesses before this instruction complete. All Cache, Branch predictor and TLB maintenance operations preceding this instruction complete.
In addition, no instruction subsequent to the DSB may execute until the DSB completes. The encoding for DataSynchronizationBarrier is described in Register 7: cache management functions on page B6-19.
B2.6.3
PrefetchFlush CP15 register 7
The PrefetchFlush instruction flushes the pipeline in the processor, so that all instructions following the pipeline flush are fetched from cache or memory after the instruction has been completed. It ensures that the effects of context altering operations, such as changing the Application Space IDentifier (ASID), or completed TLB maintenance operations or branch predictor maintenance operations, as well as all changes to the CP15 registers, executed before the PrefetchFlush are visible to the instructions fetched after the PrefetchFlush. In addition, the PrefetchFlush operation ensures that any branches which appear in program order after the PrefetchFlush are always written into the branch prediction logic with the context that is visible after the PrefetchFlush. This is required to ensure correct execution of the instruction stream.
Note
Any context altering operations appearing in program order after the PrefetchFlush only take effect after the PrefetchFlush has been executed. This is due to the behavior of the context altering instructions.
Note
ARM implementations are free to choose how far ahead of the current point of execution they prefetch instructions; either a fixed or a dynamically varying number of instructions. As well as being free to choose how many instructions to prefetch, an ARM implementation can choose which possible future execution path to prefetch along. For example, after a branch instruction, it can choose to prefetch either the instruction following the branch or the instruction at the branch target. This is known as branch prediction. A potential problem with all forms of instruction prefetching is that the instruction in memory might be changed after it was prefetched but before it is executed. If this happens, the modification to the instruction in memory does not normally prevent the already prefetched copy of the instruction from executing to completion. The PrefetchFlush and memory barrier instructions (DMB or DSB as appropriate) are used to force execution ordering where necessary. See Ordering of cache maintenance operations in the memory order model on page B2-21. The encoding for the PrefetchFlush is described in Register 7: cache management functions on page B6-19.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-19
Memory Order Model
B2.7
Memory coherency and access issues
System designers and programmers need to consider all aspects of a design for overall system correctness. This section outlines some of the problems and pitfalls faced, along with the necessary steps which should be taken to ensure predictable system behavior.
Note
For the definitions in this section, a return from an exception is defined to mean one of: Using a data-processing instruction with the S bit set, and the PC as the destination. Using the Load Multiple with Restore CPSR instruction. See LDM (3) on page A4-40 for details. Using an RFE instruction.
B2.7.1
Introduction to cache coherency
When a cache and/or a write buffer is used, the system can hold multiple versions of the value of a memory location. Possible physical locations for these values are main memory, write buffers and caches. If Harvard caches are used, either or both of the instruction cache and the data cache can contain a value for the memory location. In a multi-level cache, a cache line may only be present in some levels, having been overwritten or evicted elsewhere. Not all of these physical locations necessarily contain the value written to the memory location most recently. The memory coherency problem is to ensure that when a memory location is read (either by a data read or an instruction fetch), the value actually obtained is always the value that was written to the location most recently. In the ARM memory system architectures, some aspects of memory system coherency are required to be provided automatically by the system. Other aspects are dealt with by memory coherency rules, which are limitations on how programs must behave if memory coherency is to be maintained. The memory attribute distinguishing shared and non-shared memory, as defined in ARMv6 memory attributes - introduction on page B2-8 for ARMv6 is designed to provide information on coherency needs, allowing implementations to maintain overall correctness, for example, allowing an implementation to enforce a non-cacheable policy on a region of memory marked as shared cacheable where snooping is not provided. The behavior of a program that breaks a memory coherency rule is UNPREDICTABLE. Address mapping and caches require careful management to ensure memory coherency at all times. Cache and write buffer management typically requires a sequence containing one or more of the following: cleaning the data cache if it is a write-back cache invalidating the data cache invalidating the instruction cache draining the write buffer performing a prefetch flush on the instruction pipeline. flushing branch prediction logic (branch target buffers).
B2-20
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
Prior to ARMv6, the operations and sequences are IMPLEMENTATION DEFINED. In ARMv6, the memory order model, cache, TLB and memory barrier operations supported in the System Control Coprocessor (CP15) allow the operating system support to be standardized for level 1 memory.
Note
Implementors are strongly advised to work with ARM where control of additional cache levels is required, to minimize potential impacts of future compatibility.
B2.7.2
Ordering of cache maintenance operations in the memory order model
The following rules apply to cache maintenance operations with respect to the memory order model: All Cache and Branch Predictor Maintenance operations are executed in program order relative to each other. Where a cache or branch predictor maintenance operation appears in program order before a change to the page tables, the cache or branch predictor maintenance operation is guaranteed to take place before change to the page tables is visible. Where a change of the page tables appears in program order before a cache or branch predictor maintenance operation, the sequence outlined in TLB maintenance operations and the memory order model on page B2-22 must be executed before that change can be guaranteed to visible. DMB causes the effect of all cache maintenance operations appearing in program order prior to the DMB operation to be visible to all explicit load and store operations appearing in program order after the DMB. It also ensures that the effects of any cache maintenance operations appearing in program order before the DMB are globally observable before any cache maintenance or explicit memory operations appearing in program order after the DMB are observed. Completion of the DMB does not ensure the visibility of all data to other (relevant) observers. (e.g. page table walks). DSB causes the completion of all cache maintenance operations appearing in program order prior to the DSB operation, and ensures that all data written back is visible to all (relevant) observers. PrefetchFlush or a return from exception causes the effect of all Branch Predictor maintenance operations appearing in program order prior to the PrefetchFlush operation to be visible to all instructions after the PrefetchFlush operation or exception return. An exception causes the effect of all Branch Predictor maintenance operations appearing in program order prior to the point in the instruction stream where the exception is taken to be visible to all instructions executed after the exception entry (including the instruction fetch of those instructions). A Data (or unified) cache maintenance operation by MVA must be executed in program order relative to any explicit load or store on the same processor to an address covered by the MVA of the cache operation. The ordering of a Data (or unified) cache maintenance operation by MVA relative to any explicit load or store on the same processor where the address of the explicit load or store is not covered by the MVA of the cache operation is not restricted. Where the ordering is to be restricted, a DMB operation must be inserted to enforce ordering.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-21
Memory Order Model
The ordering of a Data (or unified) cache maintenance operation by Set/Way relative to any explicit load or store on the same processor is not restricted. Where the ordering is to be restricted, a DMB operation must be inserted to enforce ordering. The execution of a Data (or unified) cache maintenance operation by Set/Way is not necessarily visible to other observers within the system until a DSB operation has been executed. The execution of an Instruction cache maintenance operation is only guaranteed to be complete after the execution of a DSB barrier. The completion of an Instruction cache maintenance operation is only guaranteed to be visible to the instruction fetch after the execution of a PrefetchFlush operation or an exception or return from exception.
As a result of the last two points, the sequence of cache cleaning operations for a line of self-modifying code on a uniprocessor system is:
STR rx, [Instruction location] Clean Data cache by MVA to point of unification [instruction location] DSB ; ensures visibility of the data cleaned from the D Cache Invalidate Instruction cache by MVA [instruction location] Invalidate BTB entry by MVA [instruction location] DSB ; ensures completion of the ICache invalidation PrefetchFlush
B2.7.3
TLB maintenance operations and the memory order model
The following rules apply to the TLB maintenance operations with respect to the memory order model: The completion of a TLB maintenance operation is only guaranteed to be completed by the execution of a DSB instruction. PrefetchFlush, or a return from an exception, causes the effect of all completed TLB maintenance operations appearing in program order prior to the PrefetchFlush or return from exception to be visible to all subsequent instructions (including the instruction fetch for those instructions). An exception causes all completed TLB maintenance operations which appear in the instruction stream prior to the point that the exception was taken to be visible to all subsequent instructions (including the instruction fetch for those instructions). All TLB Maintenance operations are executed in program order relative to each other. The execution of a data (or unified) TLB maintenance operation is guaranteed by hardware not to affect any explicit memory transaction of any instructions which appear in program order prior to the TLB maintenance operation. As a result, no memory barrier is required. The execution of a data (or unified) TLB maintenance operation is only guaranteed to be visible to a subsequent explicit load or store after the execution of a DSB operation to ensure the completion of the TLB operation and a subsequent PrefetchFlush operation, the taking of an exception, or the return from an exception.
B2-22
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
The execution of an instruction (or unified) TLB maintenance operation is only guaranteed to be visible to the instruction fetch after the execution of a DSB operation to ensure the completion of the TLB operation and a subsequent PrefetchFlush operation, the taking of an exception, or the return from an exception.
The following rules apply when writing page table entries to ensure their visibility to subsequent transactions (including cache maintenance operations): The TLB page table walk is treated as a separate observer for the purposes of TLB maintenance: A write to the page tables (once cleaned from the cache if appropriate) is only guaranteed to be seen by a page table walk caused by an explicit load or store after the execution of a DSB operation. However, it is guaranteed that any writes to the page tables will not be seen by an explicit memory transaction occurring in program order before the write to the page tables. A clean of the page table must be performed between writing to the page tables and their visibility by a hardware page table walk if the page tables are held in WB cacheable memory. A write to the page tables (once cleaned from the cache if appropriate) is only guaranteed to be seen by a page table walk caused by an instruction fetch of an instruction following the write to the page tables after the execution of a DSB operation and a PrefetchFlush operation.
The typical code for writing a page table entry (covering changes to the instruction or data mappings) in a uniprocessor system is therefore:
STR rx, [Page table entry] ; Clean line [Page table entry] DSB ; ensures visibility of the data cleaned from the D Cache Invalidate TLB entry by MVA [page address] Invalidate BTB DSB ; ensure completion of the Invalidate TLB PrefetchFlush
B2.7.4
Synchronization primitives and the memory order model
The synchronization primitives, SWP/SWPB and LDREX/STREX, follow the memory ordering model of the memory types accessed by those instructions. For this reason: Portable code for claiming a spinlock is expected to include a DMB instruction between claiming the spinlock and making accesses that make use of the spinlock. Portable code for releasing a spinlock is expected to include a DMB instruction before writing to clear the spinlock.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-23
Memory Order Model
B2.7.5
Branch predictor maintenance operations and the memory order model
The following rule applies to the Branch Predictor maintenance operations with respect to the memory order model: Any invalidation of the branch predictor is only guaranteed to take effect after the execution of a PrefetchFlush operation, the taking of an exception, or a return from an exception.
The branch predictor maintenance operations must be used to invalidate entries in the branch predictor after one of the following events: enabling or disabling the MMU writing new data to instruction locations writing new mappings to the page tables changes to the TTBR0, TTBR1, or TTBCR changes to the FCSE ProcessID or ContextID. Failure to invalidate entries might give UNPREDICTABLE results caused by the execution of old branches.
B2.7.6
Changes to CP15 registers and the memory order model
All changes to CP14 and CP15 registers which appear in program order after any explicit memory operations are guaranteed not to affect those preceding memory operations. All changes to CP14 and CP15 registers are only guaranteed to be visible to subsequent instructions after the execution of a PrefetchFlush operation, or the taking of an exception, or the return from an exception. However, the following applies to coprocessor register accesses: When an MRC operation directly reads a register using the same register number which was used by an MCR operation to write it, it is guaranteed to observe the value written, without requiring a context-synchronization between the MCR and the MRC. When an MCR operation directly writes a register using the same register number which was used by a previous MCR operation to write it, the final result will be the value of the second MCR, without requiring a context-synchronization between the two MCR instructions.
Some CP15 registers might, on a case by case basis, require additional operations prior to the PrefetchFlush, exception or return from exception to guarantee their visibility. These cases are specifically identified with the definition of those registers. Where a change to the CP15 registers which is not yet guaranteed to be visible has an effect on exception processing, the following rule applies: Any change of state held in CP15 registers involved in the triggering of an exception is not yet guaranteed to be visible while any change involved with the processing of the exception itself (once it is determined that the exception is being taken) is guaranteed to take effect.
Therefore, in the following example (where A=1, V=0 initially), the LDR may or may not take a data abort due to the unaligned transaction, but if an exception occurs, the vector used will be affected by the V bit:
B2-24
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Memory Order Model
MCR p15, r0, c1, c0, 0 LDR r2, [R3]
; clears the A bit and sets the V bit ; unaligned load.
Synchronization of changes of ASID and TTBR
A common usage model of TLB management requires that the ContextID and Translation Table Base Registers are changed together to allow the ContextID to be associated with different page tables. However, the IMPLEMENTATION DEFINED depth of prefetch and the use of branch prediction create problems in ensuring the synchronization of changes of the ContextID and Translation Table Register (for example, TLBs, branch target caches and/or other caching of ASID and translation information might become corrupt with invalid translations). This synchronization is necessary to avoid either: the old ASID from being associated with page table walks from the new page tables the new ASID from being associated with page table walks from the old page tables. There are a number of possible solutions to this problem, as illustrated by the following example. Example solution In this approach, the ASID value of 0 is reserved by the operating system, and is not used except for the synchronization of the ASID and Translation Table Base Register. The following sequence is then followed (executed from memory marked as being Global):
Change ASID to 0 PrefetchFlush Change Translation Table Base Register PrefetchFlush Change ASID to new value
This approach ensures that any non-global pages accessed (by prefetch) at a time when it is uncertain whether the old or new page tables are being accessed will be associated with the unused ASID value of 0, and so cannot result in corruption of execution. Another manifestation of this same problem is that if a branch is encountered between the changing of an ASID and its synchronization, then the value in the branch predictor might be associated with the incorrect ASID. This manifestation is addressed by the ASID 0 approach, but might also be addressed by avoiding such branches.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B2-25
Memory Order Model
B2.7.7
Changes to CPSR and the memory order model
All changes to the CPSR via CPS, SETEND, and MSR instructions (that operate on the CPSR without causing or returning from exceptions), that appear in program order after any instruction operations, are guaranteed not to affect those instructions. All changes to the CPSR via CPS, SETEND, and MSR instructions (that operate on the CPSR without causing or returning from exceptions), are guaranteed to be visible to all instructions that appear in program order after those changes, in all aspects except the effect on instruction permission checking. If the effect on the CPSR is to change the privilege (or security) status of the execution, then this change is only visible for the purposes of instruction permission checking after the execution of a PrefetchFlush operation, or the taking of an exception, or the return from an exception.
B2-26
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Chapter B3 The System Control Coprocessor
This chapter describes coprocessor 15, the System Control coprocessor. It contains the following sections: About the System Control coprocessor on page B3-2 Registers on page B3-3 Register 0: ID codes on page B3-7 Register 1: Control registers on page B3-12 Registers 2 to 15 on page B3-18.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B3-1
The System Control Coprocessor
B3.1
About the System Control coprocessor
All of the standard memory and system facilities are controlled by coprocessor 15 (CP15), which is known as the System Control coprocessor. Some facilities also use other methods of control, and these are described in the chapters relating to those facilities. For example, the Memory Management Unit described in Chapter B4 Virtual Memory System Architecture is also controlled by page tables in memory. ARMv6 systems shall include a System Control Coprocessor, with support for automatic interrogation of cache, tightly coupled memory, and coprocessor provision. It also provides the control mechanism for memory management (MMU and MPU support as applicable). Prior to ARMv6, CP15 instructions are UNDEFINED when CP15 is not implemented. However, CP15 has become a de facto standard for processor ID, cache control, and memory management (MMU and MPU support) in implementations since ARMv4. This manual should be read in conjunction with the relevant implementation reference manual to determine the exact details of CP15 support in a particular part. This chapter describes the overall design of the System Control coprocessor and how its registers are accessed. Detailed information is given about some of its registers. Other registers are allocated to facilities described in detail in other chapters and are only summarized in this chapter.
B3-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The System Control Coprocessor
B3.2
Registers
The System Control coprocessor can contain up to 16 primary registers, each of which is 32 bits long. Additional fields in the register access instructions are used to further refine the access, increasing the number of physical 32-bit registers in CP15. The 4-bit primary register number is used to identify registers in descriptions of the System Control coprocessor, because it is the primary factor determining the function of the register. CP15 registers can be read-only, write-only or read/write. The detailed descriptions of the registers specify: the types of access that are allowed the functionality invoked by each type of access whether a primary register identifies more than one physical register, and if so, how they are distinguished any other details that are relevant to the use of the register.
B3.2.1
Register access instructions
The only defined System Control coprocessor instructions are: MCR instructions to write an ARM register to a CP15 register MRC instructions to read the value of a CP15 register into an ARM register MCRR instructions for range operations introduced in ARMv6, and optional in earlier versions of the architecture. MRRC optional for IMPLEMENTATION DEFINED features. All CP15 CDP, CDP2, LDC, LDC2, MCR2, MCRR2, MRC2, MRRC2 , STC, and STC2 instructions are UNDEFINED. The format of the MCR/MRC instructions is illustrated below, with bits[11:8](cp_num) indicating CP15, and the CRn field indicating the primary register number, with CRm and opcode2 providing additional register decode.
31 28 27 26 25 24 23 21 20 19 16 15 12 11 87 54 3 0
cond
1 1 1 0 opcode1 L
CRn
Rd
1 1 1 1 opcode2 1
CRm
The MCR and MRC instructions to access the CP15 registers use the generic syntax for those instructions:
MCR{<cond>} MRC{<cond>} p15, 0, <Rd>, <CRn>, <CRm>{, <opcode2>} p15, 0, <Rd>, <CRn>, <CRm>{, <opcode2>} (L = 0) (L = 1)
where:
<cond>
This is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3. If <cond> is omitted, the AL (always) condition is used.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B3-3
The System Control Coprocessor
Bits[23:21]
These bits of the instruction, which are the <opcode1> field in generic MRC and MCR instructions, are generally 0b000 in valid CP15 instructions. However, <opcode1> == 1 is being used for level 2 cache support and considered for some other specialist tasks. Unassigned values are UNPREDICTABLE. This is the ARM register involved in the transfer (the source register for MCR and the destination register for MRC). This register must not be R15, even though MRC instructions normally allow it to be R15. If R15 is specified for <Rd> in a CP15 MRC or MCR instruction, the instruction is UNPREDICTABLE. This is the primary CP15 register involved in the transfer (the destination register for MCR and the source register for MRC). The standard generic coprocessor register names are c0, c1, ..., c15. This is an additional coprocessor register name which is used for accesses to some primary registers to specify additional information about the version of the register and/or the type of access. When the description of a primary register does not specify <CRm>, c0 must be specified. If another register is specified, the instruction is UNPREDICTABLE.
<Rd>
<CRn>
<CRm>
<opcode2>
This is an optional 3-bit number which is used for accesses to some primary registers to specify additional information about the version of the register and/or the type of access. If it is omitted, 0 is used. When the description of a primary register does not specify <opcode2>, it must be omitted or 0 must be specified. If another value is specified, the instruction is
UNPREDICTABLE.
The MCRR format (see MCRR on page A4-64) has less scope for decode. The primary register is implied (no CRn field), and the CRm and opcode fields are used to decode the correct function. Prior to ARMv6, MCR and MRC instructions can only be used when the processor is in a privileged mode. If they are executed when the processor is in User mode, an Undefined Instruction exception occurs. ARMv6 introduced user access of the following commands: Prefetch flush Data synchronization barrier Data memory barrier Clean and prefetch range operations.
Note
If access to privileged System Control coprocessor functionality by User mode programs is required, the usual solution is that the operating system defines one or more SWIs to supply it. As the precise set of memory and system facilities available on different processors can vary considerably, it is recommended that all such SWIs are implemented in an easily replaceable module and that the SWI interface of this module is defined to be as independent of processor details as possible.
B3-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The System Control Coprocessor
B3.2.2
Primary register allocation
Table B3-1 shows the allocation of the primary registers of the System Control coprocessor. Table B3-1 Primary register allocation
Reg 0
Generic use ID codes (read-only)
Specific uses Processor ID, Cache, Tightly-coupled Memory and TLB type System Configuration Bits
Details in Register 0: ID codes on page B3-7
1
Control bits (read/write)
Control register on page B3-12, and Register 1: Control register on page B4-40 Register 2: Translation table base on page B4-41 Register 3: Domain access control on page B4-42 None. This is a reserved register. Fault Address and Fault Status registers on page B4-19, and Register 5: Fault status on page B4-43 Fault Address and Fault Status registers on page B4-19, and Register 6: Fault Address register on page B4-44 Register 7: cache management functions on page B6-19 Register 8: TLB functions on page B4-45 Register 9: cache lockdown functions on page B6-31 Register 10: TLB lockdown on page B4-47 L1 DMA control using CP15 Register 11 on page B7-9 None. This is a reserved register.
2 3 4 5
Memory protection and control Memory protection and control Memory protection and control Memory protection and control
Page Table Control Domain Access Control Reserved Fault status
6
Memory protection and control
Fault address
7 8 9 10 11 12
Cache and write buffer Memory protection and control Cache and write buffer Memory protection and control Tightly-coupled Memory Control Reserved
Cache/write buffer control TLB control Cache lockdown TLB lockdown DMA Control Reserved
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B3-5
The System Control Coprocessor
Table B3-1 Primary register allocation Reg 13 Generic use Process ID Specific uses Process ID Details in Register 13: Process ID on page B4-52, and Register 13: FCSE PID on page B8-7 Implementation documents
14 15
Reserved
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
B3-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The System Control Coprocessor
B3.3
Register 0: ID codes
CP15 register 0 contains one or more identification codes for the ARM and system implementation. When this register is read, the opcode2 field of the MRC instruction selects which identification code is wanted, as shown in Table B3-2, and the CRm field must be specified as c0 (if it is not, the instruction is UNPREDICTABLE). Writing to CP15 register 0 is UNPREDICTABLE. Table B3-2 System Control coprocessor ID registers opcode2 0b000 0b001 0b010 0b011 0b100 other Register Main ID register Cache type register Tightly Coupled Memory (TCM) type register TLB type register MPU type register (PMSAv6) Reserved (see main text) Details in Main ID register Cache type register on page B3-10 TCM type register on page B3-10
If an <opcode2> value corresponding to an unimplemented or reserved ID register is encountered, the System Control coprocessor returns the value of the main ID register. ID registers other than the main ID register are defined so that when implemented, their value cannot be equal to that of the main ID register. Software can therefore determine whether they exist by reading both the main ID register and the desired register and comparing their values. If the two values are not equal, the desired register exists.
B3.3.1
Main ID register
When CP15 register 0 is read with <opcode2> == 0, an identification code is returned from which, among other things, the ARM architecture version number can be determined, as well as whether or not the Thumb instruction set has been implemented.
Note
Only some of the fields in CP15 register 0 are architecturally defined. The rest are IMPLEMENTATION DEFINED and provide more detailed information about the exact processor variant. Consult individual datasheets for the precise identification codes used for each processor.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B3-7
The System Control Coprocessor
Implementor code
Bits[31:24] of the main ID register contain an implementor code. The following codes are defined (all other values of the architecture code are reserved by ARM Limited.): 0x41 A (ARM Limited) 0x44 D (Digital Equipment Corporation) 0x4D M (Motorola - Freescale Semiconductor Inc.) 0x56 V (Marvell Semiconductor Inc.) 0x69 i (Intel Corporation)
ARM processor implementation IDs
For historical reasons, there are a variety of ways in which the CP15 register 0 ID code might need to be interpreted. If bit[19] is zero, bits[15:12] should be interpreted as follows: if they are 0x0, this indicates an OBSOLETE part (pre-ARMv4 architecture) if they are 0x7, this indicates that the processor is in the ARM7 family if > 0x7, a more recent processor family than ARM7 is involved. ARM7 processor IDs are interpreted as follows:
31 24 23 22 16 15 43 0
Implementor
A
Variant
Primary part number
Revision
Bits[3:0] Bits[15:4] Bits[22:16] Bit[23]
Contain the IMPLEMENTATION DEFINED revision number for the processor. Contain the IMPLEMENTATION DEFINED representation of the primary part number for the processor. The top four bits of this number are 0x7. Contain an IMPLEMENTATION DEFINED variant number. Indicates which of the two possible architectures for an ARM7-based process is involved:
0 1
Architecture 3 (OBSOLETE part) Architecture 4T.
Bits[31:24]
0x41 = A (ARM Limited) implementation code.
Processor implementations since ARM7 have a general format of bits[23:0] which are common across implementations from ARM and architecture licensees. Two general formats are defined, dependent on the value of bit[19]. They are described in the following sections.
B3-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The System Control Coprocessor
Post-ARM7 processors
If bits[15:12] of the ID code are neither 0x0 nor 0x7, the ID code is interpreted as follows:
31 24 23 20 19 16 15 4 3 0
Implementor
Variant
Architecture
Primary part number
Revision
Bits[3:0] Bits[15:4] Bits[19:16]
Contain the IMPLEMENTATION DEFINED revision number for the processor. Contain an IMPLEMENTATION DEFINED representation of the primary part number for the processor. The top four bits of this number are not allowed to be 0x0 or 0x7. Contain an architecture code. The following architecture codes are defined: 0x1 ARM architecture v4 0x2 ARM architecture v4T 0x3 ARM architecture v5 0x4 ARM architecture v5T 0x5 ARM architecture v5TE 0x6 ARM architecture v5TEJ 0x7 ARM architecture v6 0xF Revised CPUID format. Details available from ARM. All other values of the architecture code are reserved by ARM Limited
Bits[23:20] Bits[31:24]
Contain an IMPLEMENTATION DEFINED variant number. This is typically used to distinguish two variants of the same primary part, for example, two different cache size variants. Contain an implementor code. See Implementor code on page B3-8.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B3-9
The System Control Coprocessor
B3.3.2
Cache type register
The Cache type register supplies the following details about the cache: whether it is a unified cache or separate instruction and data caches its size, line length and associativity whether it is a write-through cache or a write-back cache cache cleaning and lockdown capabilities. The format of the Cache type register is:
31 29 28 25 24 23 12 11 0
000
ctype
S
Dsize
Isize
ctype S bit
Specifies details of the cache not specified by the S bit and the Dsize and Isize fields. All values not specified in the table are reserved for future expansion. Specifies whether the cache is a unified cache (S == 0), or separate instruction and data caches (S == 1). If S == 0, the Isize and Dsize fields both describe the unified cache, and must be identical. Specifies the size, line length and associativity of the data cache, or of the unified cache if S == 0. Specifies the size, line length and associativity of the instruction cache, or of the unified cache if S == 0.
Dsize Isize
A detailed discussion on caches is provided in Chapter B6 Caches and Write Buffers. See Cache Type register on page B6-14 for the encoding of the cache type register fields.
B3.3.3
TCM type register
The format of the Tightly-Coupled Memory (TCM) type register is:
31 29 28 19 18 16 15 32 0
000
SBZ/UNP
DTCM
SBZ/UNP
ITCM
ITCM (Bits[2:0]) Indicate the number of Instruction (or Unified) Tightly-Coupled Memories implemented. This value lies in the range 0-4, all other values are reserved. All Instruction TCMs must be accessible to both instruction and data sides. DTCM (Bits[18:16]) Indicate the number of Data Tightly-Coupled Memories implemented. This value lies in the range 0-4, all other values are reserved. A detailed discussion of tightly coupled memory is provided in chapter Chapter B7 Tightly Coupled Memory.
B3-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The System Control Coprocessor
B3.3.4
TLB type register
The format of the TLB type register is:
31 24 23 16 15 87 10
SBZ/UNP
ILsize
DLsize
SBZ/UNP
S
S-bit DLsize ILsize
Specifies whether the TLB is a unified TLB (S == 0), or separate instruction and data TLBs (S == 1). Specifies the number of lockable entries in the data TLB if S ==1, or the unified TLB if S == 0. Specifies the number of lockable entries in the instruction TLB, if S == 1, otherwise SBZ.
A detailed description of the virtual memory system architecture is provided in Chapter B4 Virtual Memory System Architecture.
B3.3.5
MPU type register
The format of the Memory Protection Unit (MPU) type register is:
31 24 23 16 15 87 10
SBZ/UNP
IRegion
DRegion
SBZ/UNP
S
S-bit DRegion IRegion
Specifies whether the MPU is a unified MPU (S == 0), or separate instruction and data MPUs (S == 1). Specifies the number of protected regions in the data MPU if S ==1, or the unified MPU if S == 0. Specifies the number of protected regions in the instruction MPU, if S == 1, otherwise SBZ.
A detailed description of the protected memory system architecture is provided in Chapter B5 Protected Memory System Architecture.
Note
The MPU type register is introduced with PMSAv6.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B3-11
The System Control Coprocessor
B3.4
Register 1: Control registers
CP15 register 1 contains configuration control bits for the ARM processor. It contains 3 registers selected by the opcode_2 field. When opcode_2 is 0 the architecturally specified control register is selected. When opcode_2 is 1 an IMPLEMENTATION DEFINED control register is selected. Table B3-3 System Control coprocessor Control registers opcode2 0b000 0b001 0b010 other Register Control register Auxiliary control register (format IMPLEMENTATION DEFINED) Coprocessor access control register RESERVED
B3.4.1
Control register
This register contains: Enable/disable bits for the caches, MMUs, and other memory system blocks that are primarily controlled by other CP15 registers. This allows these memory system blocks to be programmed correctly before they are enabled. Various configuration bits for memory system blocks and for the ARM processor itself.
Note
Extra bits of both varieties might be added in the future. Because of this, this register should normally be updated using read/modify/write techniques, to ensure that currently unallocated bits are not needlessly modified. Failure to observe this rule might result in code which has unexpected side effects on future processors.
31
UNP/SBZP
27 26 25 24 23 22 21 20
L2 EE VE XP U FI
16 15 14 13 12 11 10 9 8
L4 RR V I Z F R S
765432
B L D PWC
10
AM
When a control bit in CP15 register 1 is not applicable to a particular implementation, it reads as the value that most closely reflects that implementation, and ignores writes. (Specific examples of this general rule are documented in the individual bit descriptions below.) Apart from bits that read as 1 according to this rule, all bits in CP15 register 1 are set to 0 on reset. M (bit[0]) This is the enable/disable bit for the MMU or Protection Unit: 0 = MMU or Protection Unit disabled
B3-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The System Control Coprocessor
1 = MMU or Protection Unit enabled. On systems without an MMU, this bit reads as 0 and ignores writes. A (bit[1]) In ARM architecture v6, this controls strict alignment: 0 = Alignment not strict 1 = Strict alignment. If a data access is not aligned to the width of the accessed data item, a Data Abort exception is generated. In architectures before v6, for memory systems which optionally allow the alignment of data memory accesses to be checked, this bit enables and disables alignment fault checking: 0 = Alignment fault checking disabled 1 = Alignment fault checking enabled. For other memory systems, this bit ignores writes, and reads as 1 or 0 according to whether the memory system does or does not check the alignment of data memory accesses. C (bit[2]) If a L1 unified cache is used, this is the enable/disable bit for the unified cache. If separate L1 caches are used, this is the enable/disable bit for the data cache. In either case: 0 = L1 unified/data cache disabled 1 = L1 unified/data cache enabled. If the L1 cache is not implemented, this bit reads as 0 and ignores writes. If the L1 cache cannot be disabled, this bit reads as 1 and ignores writes. The state of this bit does not affect other levels of cache in the system. W (bit[3]) This is the enable/disable bit for the write buffer: 0 = Write buffer disabled 1 = Write buffer enabled. If the write buffer is not implemented, this bit reads as zero (RAZ) and ignores writes. If the write buffer cannot be disabled, this bit reads as one and ignores writes. SBO (bits[4:6]) These bits read as 1 and ignore writes. B (bit[7]) This bit is used to configure the ARM processor to the endianness of the memory system. ARM processors which support both little-endian and big-endian word-invariant memory systems use this bit to configure the ARM processor to rename the four byte addresses within a 32-bit word. In V6 this becomes the mechanism by which legacy big-endian operating systems and applications can be supported. 0 = configured little-endian memory system (LE) 1 = configured big-endian word-invariant memory system (BE-32)
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B3-13
The System Control Coprocessor
Two configuration bits CFGEND[1:0] define the endian model at reset as described in Table A2-7 on page A2-35. (Previous architectures allowed an IMPLEMENTATION DEFINED configuration option to pre-set or reset this bit externally, depending on the external memory subsystem). S (bit[8]) R (bit[9]) F (bit[10]) Z (bit[11]) System protection bit, supported for backwards compatibility. The effect of this bit is described in Access permissions on page B4-8. The functionality is deprecated in ARMv6. ROM protection bit, supported for backwards compatibility. The effect of this bit is described in Access permissions on page B4-8. The functionality is deprecated in ARMv6. The meaning of this bit is IMPLEMENTATION DEFINED. On ARM processors which support branch prediction, this is the enable/disable bit for branch prediction: 0 = Program flow prediction disabled 1 = Program flow prediction enabled. If program flow prediction cannot be disabled, this bit reads as 1 and ignores writes. Program flow prediction includes all possible forms of speculative change of instruction stream prediction. Examples include static prediction, dynamic prediction, and return stacks. On ARM processors that do not support branch prediction, this bit reads as 0 and ignores writes. I (bit[12]) If separate L1 caches are used, this is the enable/disable bit for the L1 instruction cache: 0 = L1 instruction cache disabled 1 = L1 instruction cache enabled. If an L1 unified cache is used or the L1 instruction cache is not implemented, this bit reads as 0 and ignores writes. If the L1 instruction cache cannot be disabled, this bit reads as 1 and ignores writes. The state of this bit does not affect further levels of cache in the system. V (bit[13]) This bit is used to select the location of the exception vectors: 0 = Normal exception vectors selected (address range 0x00000000-0x0000001C) 1 = High exception vectors selected (address range 0xFFFF0000-0xFFFF001C). An implementation can provide an input signal that determines the state of this bit after reset. RR (bit[14]) If the cache allows an alternative replacement strategy to be used that has a more predictable performance, this bit selects it: 0 = Normal replacement strategy (for example, random replacement) 1 = Predictable strategy (for example, round-robin replacement). L4 (bit[15]) This bit inhibits ARMv5T Thumb interworking behavior when set. It stops bit[0] updating the CPSR T-bit. The disable feature is deprecated in ARMv6
B3-14
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The System Control Coprocessor
The instructions affected by this are: LDM (1) on page A4-36 LDR on page A4-43 POP on page A7-82. DT (bit[16]) SBO.
SBZ (bit[17]) This bit reads as 0 and ignores writes. IT (bit[18]) SBO.
SBZ (bit[19]) This bit reads as 0 and ignores writes. ST (bit[20]) FI (bit[21]) SBZ/UNP. Configure Fast Interrupt configuration. This bit may be used to reduce interrupt latency in an implementation by disabling IMPLEMENTATION DEFINED performance features: 0 = All performance features enabled 1 = Low interrupt latency configuration enabled. U(bit[22])) This bit enables unaligned data access operation, including support for mixed little-endian and big-endian data. 0 = unaligned loads are treated as rotated aligned data accesses (legacy code behavior). 1 = unaligned loads and stores are permitted and mixed-endian data support enabled. XP(bit[23]) Extended page table configure. This bit configures the hardware page table translation mechanism: 0 = Subpage AP bits enabled. 1 = Subpage AP bits disabled. In this case, hardware translation tables support additional features. VE(bit[24]) Configure vectored interrupts. Enables use of an IMPLEMENTATION DEFINED hardware mechanism to determine the interrupt vectors: 0 = Interrupt vectors are fixed: IRQ at 0x00000018 if V bit == 0, IRQ at 0xFFFF0018 if V bit == 1 FIQ at 0x0000001C if V bit == 0, FIQ at 0xFFFF001C if V bit == 1 1 = Interrupt vectors are defined by an IMPLEMENTATION DEFINED hardware mechanism. EE Bit[25] Mixed Endian exception entry. The EE bit is used to define the value of the CPSR E-bit on entry to an exception vector, including reset. The value is also used to indicate the endianness of page table data for page table lookups. This bit may be preset by CFGEND[1:0] pins on system reset. See Endian configuration and control on page A2-34 for more details. L2 unified cache enable.
L2 Bit[26]
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B3-15
The System Control Coprocessor
Bits[31:26]
RESERVED.
These bits are normally updated using read/modify/write techniques, to ensure that currently unallocated bits are not needlessly modified. Failure to observe this rule might result in code which has unexpected side effects on future processors. One exception that might be useful in some circumstances is that 0 can be written to these bits to restore them to their reset state.
B3.4.2
Auxiliary control register
The contents of this register are IMPLEMENTATION DEFINED. The register is guaranteed to be privileged read/write accessible, even if an implementation has not created any control bits within this register.
B3.4.3
Coprocessor access register
This register controls accesses to all coprocessors other than CP15 and CP14. A typical use for this register is to enable an operating system to control coprocessor resource sharing among applications. Initially all applications are denied access to the shared resources. When an application attempts to use that resource it results in an Undefined Instruction exception. The Undefined Instruction handler can then grant access to that resource by setting the appropriate bits in the coprocessor access register. Sharing resources among applications requires a state saving mechanism. Two possibilities are:
31
the operating system, during a context switch, saves the state of the coprocessor if the last executing process had access rights to a coprocessor the operating system, after a request for access to a coprocessor, saves off the old coprocessor state with the last process to have access to it.
29 27 25 23 21 19 17 15 13 11 9 7 5 3 0
UNP/SBZP cp13 cp12 cp11 cp10 cp9
cp8
cp7
cp6
cp5
cp4
cp3
cp2
cp1
cp0
Coprocessor access rights
Each pair of bits corresponds to the access rights for each coprocessor: 00 01 10 11 Access denied. Attempts to access corresponding coprocessor generates an undefined exception. Privileged access only. Attempts to access corresponding coprocessor in user mode generates an undefined exception.
RESERVED
(UNPREDICTABLE)
Full access (as defined by the relevant coprocessor).
B3-16
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
The System Control Coprocessor
After updating this register a PrefetchFlush instruction should be executed before the effect of the change to the coprocessor access register can be guaranteed to be visible. None of the instructions executed after changing this register and before the PrefetchFlush should be coprocessor instructions affected by the change in coprocessor access privileges. After a system reset all coprocessor access rights are set to Access denied. Any unimplemented coprocessors shall result in the associated bit field read-as-zero (RAZ). This allows system software to write all-1's to the coprocessor access register, then read back the result to determine which coprocessors are present, as part of an auto-configuration sequence. If more than one coprocessor is used for a set of functionality (for example in the case with VFP, where CP10 and CP11 are used) then having different values in the fields of the coprocessor access register for those coprocessors can lead to UNPREDICTABLE behavior.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B3-17
The System Control Coprocessor
B3.5
Registers 2 to 15
System Control coprocessor registers other than registers 0 and 1 are allocated to specific areas as follows: CP15 registers 2 to 6, 8, 10, and 13 are allocated to the memory protection system. See Chapter B4 Virtual Memory System Architecture, Chapter B5 Protected Memory System Architecture, and Chapter B8 Fast Context Switch Extension for details of these registers. CP15 registers 7 and 9 are allocated to the control of caches, and write buffers. See Chapter B6 Caches and Write Buffers for details of these registers. CP15 register 11 is allocated to the level 1 memory DMA support. See Chapter B7 Tightly Coupled Memory for details. CP15 register 15 is reserved for IMPLEMENTATION DEFINED purposes. See the technical reference manual for the implementation or other implementation-specific documentation for details of the facilities available through this register. CP15 registers 12 and 14 are reserved for future expansion. Accessing (reading or writing) any of these registers is UNPREDICTABLE, and UNDEFINED from ARMv6.
B3-18
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Chapter B4 Virtual Memory System Architecture
This chapter describes the Virtual Memory System Architecture (VMSA) based on a Memory Management Unit (MMU). It contains the following sections: About the VMSA on page B4-2 Memory access sequence on page B4-4 Memory access control on page B4-8 Memory region attributes on page B4-11 Aborts on page B4-14 Fault Address and Fault Status registers on page B4-19 Hardware page table translation on page B4-23 Fine page tables and support of tiny pages on page B4-35 CP15 registers on page B4-39.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-1
Virtual Memory System Architecture
B4.1
About the VMSA
Complex operating systems typically use a virtual memory system to provide separate, protected address spaces for different processes. Processes are dynamically allocated memory and other memory mapped system resources under the control of a Memory Management Unit (MMU). The MMU allows fine-grained control of a memory system through a set of virtual to physical address mappings and associated memory properties held within one or more structures known as Translation Lookaside Buffers (TLBs) within the MMU. The contents of the TLBs are managed through hardware translation lookups from a set of translation tables maintained in memory. The process of doing a full translation table lookup is called a translation table walk. It is performed automatically by hardware, and has a significant cost in execution time, at least one main memory access, and often two. TLBs reduce the average cost of a memory access by caching the results of translation table walks. Implementations can have a unified TLB (von Neumann architecture) or separate Instruction and Data TLBs (Harvard architecture). The VMSA has been significantly enhanced in ARMv6. This is referred to as VMSAv6. To prevent the need for a TLB invalidation on a context switch, each virtual to physical address mapping can be marked as being associated with a particular application space, or as global for all application spaces. Only global mappings and those for the current application space are enabled at any time. By changing the Application Space IDentifier (ASID), the enabled set of virtual to physical address mappings can be altered. VMSAv6 has added definitions for different memory types (see ARMv6 memory attributes - introduction on page B2-8), and other attributes (see Memory access control on page B4-8). For backwards compatibility there is an XP control bit in the System Control Coprocessor, CP15 register 1, as defined in Register 1: Control register on page B4-40. The set of memory properties associated with each TLB entry includes: Memory access permission control This controls whether a program has no-access, read-only access, or read/write access to the memory area. When an access is not permitted, a memory abort is signaled to the processor. The level of access allowed can be affected by whether the program is running in User mode, or a privileged mode, and by the use of domains. Memory region attributes These describe properties of a memory region. Examples include device (VMSAv6), non-cacheable, write-through, and write-back. Virtual-to-physical address mapping An address generated by the ARM processor is called a virtual address. The MMU allows this address to be mapped to a different physical address. This physical address identifies which main memory location is being accessed. This can be used to manage the allocation of physical memory in many ways. For example, it can be used to allocate memory to different processes with potentially conflicting address maps, or to allow an application with a sparse address map to use a contiguous region of physical memory.
B4-2
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
Note
Because of the Fast Context Switch Extension (FCSE, see Chapter B8), all references to virtual address in this chapter are made to the modified virtual address that it generates, except where explicitly stated otherwise. The virtual address and modified virtual address are equal when the FCSE mechanism is disabled (PID == zero). The FCSE is only present in ARMv6 for backwards compatibility. Its use in new systems is deprecated. System Control coprocessor registers allow high-level control of this system, such as the location of the translation tables. They are also used to provide status information about memory aborts to the ARM. The VMSA allows for specific TLB entries to be locked down in a TLB. This ensures that accesses to the associated memory areas never require looking up by a translation table walk. This enables the worst case access time to code and data for real-time routines to be minimized and deterministic. When translation tables in memory are changed or a different translation table is selected (by writing to CP15 register 2), previously cached translation table walk results in the TLBs can cease to be valid. The VMSA therefore supplies operations to flush TLBs.
B4.1.1
Key changes introduced in VMSAv6
The following list summarizes the changes introduced in VMSAv6: Entries can be associated with an application space identifier, or marked as a global mapping. This eliminates the requirement for TLB flushes on most context switches. Access permissions extended to allow both privileged read only, and privileged/user read-only modes to be simultaneously supported. The use of the System (S) and ROM (R) bits to control access permission determination are only supported for backwards compatibility. Memory region attributes to mark pages shared by multiple processors. The use of Tiny pages, and the fine page table second level format is now obsolete.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-3
Virtual Memory System Architecture
B4.2
Memory access sequence
When the ARM CPU generates a memory access, the MMU performs a lookup for a mapping for the requested modified virtual address in a TLB. From VMSAv6 this also includes the current ASID. Implementations can use either Harvard or unified TLBs. If the implementation has separate instruction and data TLBs, it uses: the instruction TLB for an instruction fetch the data TLB for all other accesses. If no global mapping, or mapping for the currently selected ASID (VMSAv6), for the modified virtual address can be found in the appropriate TLB then a translation table walk is automatically performed by hardware.
Note
Prior to VMSAv6, all modified virtual address translations can be considered as globally mapped. From ARMv6, the modified virtual address should be considered as the 32-bit modified virtual address, plus the ASID value when a non-global address is accessed. The FCSE mechanism described in Chapter B8 Fast Context Switch Extension is deprecated in ARMv6. Furthermore, concurrent use of both the FCSE and ASID results in UNPREDICTABLE behavior. Either the FCSE register must be cleared, or all memory declared as global. If a matching TLB entry is found then the information it contains is used as follows: 1. 2. The access permission bits and the domain are used to determine whether access is permitted. If the access is not permitted the MMU signals a memory abort. Otherwise the access is allowed to proceed. The memory region attributes are used to control: the cache and write buffer whether the access is cached or uncached the target memory type whether the target memory is shared or unshared. The physical address is used for any access to external or tightly coupled memory, and can be used to perform TAG matching for cache entries in physically tagged cache implementations.
3.
Figure B4-1 on page B4-5 shows this for a cached system.
B4-4
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
Access control hardware
Access bits, domain TLB
Translation table walk hardware
Abort Physical address (PA)
Physical address (PA) Control bits
Main memory
ARM
Modified virtual address (MVA)
Cache and write buffer
Cache line fetch hardware
Figure B4-1 Cached MMU memory system overview
B4.2.1
TLB match process
Each TLB entry contains a modified virtual address, a page size, a physical address, and a set of memory properties. It is marked as being associated with a particular application space, or as global for all application spaces. Where an ASID is used, register 13 in CP15 determines the currently selected application space. A TLB entry matches if bits 31-N of the modified virtual address match, and it is either marked as global, or the ASID matches the current ASID, where N is log2 of the page size for the TLB entry. If two or more entries match at any time (including global and ASID specific entries), the behavior of a TLB is UNPREDICTABLE. The operating system must ensure that no more than one TLB entry can match at any time, typically by flushing its TLBs when global page mappings are changed. A TLB can store entries based on the following block sizes: Supersections consist of 16MB blocks of memory Sections consist of 1MB blocks of memory Large pages consist of 64KB blocks of memory Small pages consist of 4KB blocks of memory.
Note
The use of Tiny (1KB) pages is not supported in VMSAv6. Supersections, sections and large pages are supported to allow mapping of a large region of memory while using only a single entry in a TLB. If no mapping for an address can be found within the TLB then the translation table is automatically read by hardware, and a mapping is placed in the TLB. See Hardware page table translation on page B4-23 for more details.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-5
Virtual Memory System Architecture
B4.2.2
Virtual to physical translation mapping restrictions
The VMSA can be used in conjunction with virtually-indexed, physically-tagged caches. For details of any mapping page table restrictions for virtual to physical addresses see Restrictions on Page Table Mappings on page B6-11.
B4.2.3
Enabling and disabling the MMU
The MMU can be enabled and disabled by writing the M bit (bit[0]) of register 1 of the System Control coprocessor. On reset, this bit is cleared to 0, disabling the MMU. When the MMU is disabled, memory accesses are treated as follows: All data accesses are treated as uncacheable and strongly ordered. Unexpected data cache hit behavior is IMPLEMENTATION DEFINED. If a Harvard cache arrangement is used then all instruction accesses are cacheable, non-sharable, normal memory if the I bit (bit[12]) of CP15 register 1 is set (1), and non-cacheable, non-sharable normal memory if the I bit is clear (0). The other cache related memory attributes (for example, Write-Through cacheable, Write-Back cacheable) are IMPLEMENTATION DEFINED. If a unified cache is used, all instruction accesses are treated as non-shared, normal, non-cacheable. All explicit accesses are strongly ordered. The value of the W bit (bit[3], write buffer enable) of CP15 register 1 is ignored. No memory access permission checks are performed, and no aborts are generated by the MMU. The physical address for every access is equal to its modified virtual address (this is known as a flat address mapping). The FCSE PID (see Register 13: Process ID on page B4-52) Should Be Zero (SBZ) when the MMU is disabled. This is the reset value for the FCSE PID. If the MMU is to be disabled, the FCSE PID should be cleared. The behavior is UNPREDICTABLE if the FCSE is not cleared when the MMU is disabled. Cache CP15 operations act on the target cache whether the MMU is enabled or not, and regardless of the values of the memory attributes. However, if the MMU is disabled, they use the architected flat mapping. CP15 TLB invalidate operations act on the target TLB whether the MMU is enabled or not. Instruction and data prefetch operations work as normal. Accesses to the TCMs work as normal if the TCM is enabled.
Before the MMU is enabled all relevant CP15 registers must be programmed. This includes setting up suitable translation tables in memory. Prior to enabling the MMU, the instruction cache should be disabled and invalidated. The instruction cache can then be re-enabled at the same time as the MMU is enabled.
B4-6
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
Note
Enabling or disabling the MMU effectively changes the virtual-to-physical address mapping (unless the translation tables are set up to implement a flat address mapping). Any virtually tagged caches, for example, that are enabled at the time need to be flushed (see Memory coherency and access issues on page B2-20). In addition, if the physical address of the code that enables or disables the MMU differs from its modified virtual address, instruction prefetching can cause complications (see PrefetchFlush CP15 register 7 on page B2-19). It is therefore strongly recommended that code which enables or disables the MMU has identical virtual and physical addresses.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-7
Virtual Memory System Architecture
B4.3
Memory access control
Access to a memory region is controlled by the access permission and domain bits in the TLB entry. APX and XN (execute never) bits have been added in VMSAv6. These form part of the page table entry formats described in Hardware page table translation on page B4-23.
B4.3.1
Access permissions
The access permission bits control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised. The access permissions are determined by a combination of the AP and APX bits in the page table, and the S and R bits in CP15 register 1. For page table formats not supporting the APX bit, the value 0 is used.
Note
The use of the S and R bits is deprecated in VMSAv6. Changes to the S and R bits do not affect the access permissions of entries already in the TLB. The TLB must be flushed for the updated S and R bit values to take effect. If an access is made to an area of memory without the required permission, a Permission Fault is raised (see Aborts on page B4-14).
B4-8
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
Table Table B4-1 shows the encoding of the access permissions. Table B4-1 MMU access permissions SR 0 x x x 0 0 0 0 0 x x x 0 0 0 0 APXa 0 0 0 0 1 1 1 1 AP[1:0] 0b00 0b01 0b10 0b11 0b00 0b01 0b10 0b11 Privileged permissions No access Read/write Read/write Read/write Read only Read only User permissions No access No access Read only Read/write No access Read only Description All accesses generate permission faults Privileged access only Writes in User mode generate permission faults Full access
RESERVED
Privileged read only Privileged/User read only
RESERVED
The S and R bits are deprecated in VMSAv6. The following entries apply to legacy systems only. 0 1 1 0 1 1 1 0 1 1 0 1 0 0 0 1 1 1 0b00 0b00 0b00 0bxx 0bxx 0bxx Read only Read only Read only No access Privileged/User read only Privileged read only
RESERVED RESERVED RESERVED RESERVED
a. VMSAv6 and above only.
Each memory region can be tagged as not containing executable code. If the Execute-Never (XN) bit is set to 1, any attempt to execute an instruction in that region results in a permission fault. If the XN bit is cleared to 0, code can execute from that memory region.
Note
The XN bit acts as an additional permission check. The address must also have a valid read access.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-9
Virtual Memory System Architecture
B4.3.2
Domains
A domain is a collection of memory regions. The ARM architecture supports 16 domains. Each page table entry and TLB entry contains a field that specifies which domain the entry is in. Access to each domain is controlled by a two-bit field in the Domain Access Control Register. Each field allows the access to an entire domain to be enabled and disabled very quickly, so that whole memory areas can be swapped in and out of virtual memory very efficiently. Two kinds of domain access are supported: Clients Managers Users of domains (execute programs and access data), guarded by the access permissions of the TLB entries for that domain. Control the behavior of the domain (the current sections and pages in the domain, and the domain access), and are not guarded by the access permissions for TLB entries in that domain.
One program can be a client of some domains, and a manager of some other domains, and have no access to the remaining domains. This allows very flexible memory protection for programs that access different memory resources. Table B4-2 shows the encoding of the bits in the Domain Access Control Register. Table B4-2 Domain Access Values Value 0b00 0b01 0b10 0b11 Access types No access Client Reserved Manager Description Any access generates a domain fault Accesses are checked against the access permission bits in the TLB entry Using this value has UNPREDICTABLE results Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
B4-10
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
B4.4
Memory region attributes
Each TLB entry has an associated set of memory region attributes. These control accesses to the caches, how the write buffer is used, and if the memory region is shareable and therefore must be kept coherent. Prior to VMSAv6, only C (cacheable) and B (bufferable) bits were provided. Their exact usage model (for example, how the bit settings affected write through versus write back cache policies) and any additional controls were IMPLEMENTATION DEFINED. VMSAv6 has introduced a more formal memory model (see ARMv6 memory attributes - introduction on page B2-8), supported by the additional bit field (TEX) and definitions described in this section.
B4.4.1
C, B, and TEX Encodings
Page table formats use five bits to encode the memory region type. These are TEX[2:0] and the C and B bits. Table B4-3 on page B4-12 shows the mapping of the Type extension field (TEX) and the cacheable and bufferable bits (C and B) to memory region type. For page tables formats with no TEX field the value 0b000 is used. In addition, certain page tables contain the shared bit (S). This bit only applies to normal, not device or strongly ordered memory, and determines if the memory region is shared (1), or not-shared (0). If not present, the S bit is assumed to be 0 (not-shared).
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-11
Virtual Memory System Architecture
Table B4-3 shows the C, B, and TEX encodings. Table B4-3 CB + TEX Encodings TEX 0b000 0b000 0b000 0b000 0b001 0b001 0b001 0b001 0b010 0b010 0b010 0b011 0b1BB C 0 0 1 1 0 0 1 1 0 0 1 X A B 0 1 0 1 0 1 0 1 0 1 X X A Description Strongly ordered Shared Device Outer and inner write through, no write allocate Outer and inner write back, no write allocate Outer and inner non-cacheable
RESERVED IMPLEMENTATION DEFINED
Memory type Strongly ordered Device Normal Normal Normal IMPLEMENTATION DEFINED
Page shareable Shareable Shareable S S S IMPLEMENTATION DEFINED
Outer and inner write back, write allocate Non-shared device
RESERVED RESERVED RESERVED
Normal Device Normal
S Not shareable S
Cached memory BB = outer policy, AA = inner policy
S indicates shareable if page table present, and S-bit in page table set, otherwise not shareable. For an explanation of the Shareable attribute, and Normal, Strongly ordered and Device memory types see ARMv6 memory attributes - introduction on page B2-8. The terms Inner and Outer refer to levels of caches that might be built in a system. Inner refers to the innermost caches, including Level 1. Outer refers to the outermost caches. The boundary between Inner and Outer caches is defined in the implementation of a cached system. Inner always includes L1. For example, in a system with three levels of caches, the Inner attributes might apply to L1 and L2, whereas the Outer attributes apply to L3. In a two-level system, it is expected that Inner applies to L1 and Outer to L2.
B4-12
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
Table B4-4 shows the encoding of the inner and outer cache policies. Table B4-4 Inner and outer cache policy Encoding 0 0 1 1 0 1 0 1 Description Non-cacheable Write back, write allocate Write through, no write allocate Write back, no write allocate
It is optional which write allocation policies an implementation supports. The allocate on write and no allocate on write cache policies indicate which allocation policy is preferred for a memory region, but it should not be relied on that the memory system implements that policy. Not all inner and outer cache policies are mandatory. Table B4-5 describes the implementation options. Table B4-5 Cache policy implementation options Cache policy Inner non-cacheable Inner write through Inner write back Outer non-cacheable Outer write through Outer write back Implementation options Mandatory. Mandatory. Optional. If not supported, memory system should implement as inner write through. Mandatory. Optional. If not supported, memory system should implement as outer non-cacheable. Optional. If not supported, memory system should implement as outer write through.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-13
Virtual Memory System Architecture
B4.5
Aborts
Mechanisms that can cause the ARM processor to take an exception because of a memory access are: MMU fault Debug abort External abort The MMU detects the restriction and signals the processor. Monitor debug-mode is enabled and a breakpoint or a watchpoint has been detected. The external memory system signals an illegal or faulting memory access.
Collectively, these are called aborts. Accesses that cause aborts are said to be aborted, and use Fault Address and Fault Status registers to record associated context information. The FAR and FSR registers are described in Fault Address and Fault Status registers on page B4-19
B4.5.1
MMU faults
The MMU generates four types of fault: alignment fault translation fault domain fault permission fault. Aborts that are detected by the MMU do not make an external access to the address that the abort was detected on. If the memory request that aborts is an instruction fetch, then a Prefetch Abort exception is raised if and when the processor attempts to execute the instruction corresponding to the aborted access. If the aborted access is a data access or a cache maintenance operation, a Data Abort exception is raised. See Exceptions on page A2-16 for more information about Prefetch and Data Aborts.
Fault-checking sequence
The sequence used by the MMU to check for access faults is slightly different for Sections and Pages. Figure B4-2 on page B4-15 shows the sequence for both types of access.
B4-14
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
Modified virtual address
Checking alignment?
No
Yes
Check address alignment
No
Misaligned?
Get first-level descriptor Translation external abort Alignment fault
Yes
External abort
No
Section translation fault
Yes
Descriptor fault
Section
Section or page?
Page
Get second-level descriptor Translation external abort
External abort
No
Yes
Invalid descriptor?
No
Yes
Page translation fault
Check domain
No access Manager
Check domain
No access
Section domain fault
Access type
Client
Access type
Client
Page domain fault
Check access permissions
Check access permissions Sub-page permission fault
Section permission fault
Yes
Violation?
No
Violation?
No
Yes
Physical address
Figure B4-2 Sequence for checking faults
Alignment fault
For details of when alignment faults are generated, see Table A2-10 on page A2-40
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-15
Virtual Memory System Architecture
Translation fault
There are two types of translation fault: Section This is generated if the first-level descriptor is marked as invalid. It happens when bits[1:0] of the descriptor are both 0, and in VMSAv6 formats when the value is 0b11, a RESERVED value. This is generated if the second-level descriptor is marked as invalid. It happens if bits[1:0] of the descriptor are both 0.
Page
Page Table Entry (PTE) fetches which result in translation faults are guaranteed not to be cached (no TLB updates). TLB maintenance operations are not required to flush corrupted entries on a translation fault.
Domain fault
There are two types of domain fault: Section domain faults the domain is checked when the first-level descriptor is returned. Page domain faults the domain is checked (based on the domain field of the first level descriptor) if a valid second-level descriptor is returned. Where a Domain fault results in an update to the associated page tables, it is necessary to flush the appropriate TLB entry to ensure correctness. See the page table entry update example in TLB maintenance operations and the memory order model on page B2-22 for more details. Changes to the Domain Access Control register are synchronized by performing a PrefetchFlush operation (or as result of an exception or exception return). See Changes to CP15 registers and the memory order model on page B2-24 for details.
Permission fault
If the two-bit domain field returns client (01), the permission access check is performed on the access permission field in the TLB entry. Where a permission fault results in an update to the associated page tables, it is necessary to flush the appropriate TLB entry to ensure correctness. See the page table entry update example in TLB maintenance operations and the memory order model on page B2-22 for more details.
B4-16
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
B4.5.2
Debug events
When Monitor debug-mode is enabled, an abort can be taken because of a breakpoint on an instruction access or a watchpoint on a data access. If an abort is taken because of Monitor debug-mode then the appropriate FSR (instruction or data) is updated to indicate a Debug abort. This is the only information saved on a Prefetch Abort (a breakpoint) debug event. This is a precise abort. R14_abt is used to determine the address of the failing instruction. Watchpoints are not taken precisely, because following instructions can run underneath load and store multiples. The debugger must read the Watchpoint Fault Address Register (WFAR) to determine which instruction caused the debug event.
B4.5.3
External aborts
External memory errors are defined as those that occur in the memory system other than those that are detected by an MMU. External memory errors are expected to be rare and are likely to be fatal to the running process. An example of an event that could cause an external memory error is an uncorrectable parity or ECC failure on a Level 2 Memory structure. It is IMPLEMENTATION DEFINED which, if any, external aborts are supported. The presence of a precise external abort is signaled in the DFSR or IFSR. For further details of the imprecise external abort model see Imprecise data aborts on page A2-23.
External abort on instruction fetch
Externally generated errors during an instruction prefetch are precise in nature, and are only recognized by the CPU if it attempts to execute the instruction fetched from the location that caused the error. The Fault Address register is not updated on an external abort on instruction fetch.
External abort on data read/write
Externally generated errors during a data read or write can be imprecise. This means that R14_abt on entry into the Abort handler on such an abort is not guaranteed to hold an address that is related to the instruction that caused the exception. Correspondingly, external aborts can be unrecoverable. If an imprecise external abort causes entry into the abort state while the abort state is not re-entrant, the processor is in an unrecoverable state, as the R14 and SPSR values have been corrupted. For this reason, the existence of an imprecise external abort must only be recognized by the processor at a point when the abort state is re-entrant. This is managed by the provision of a mask for imprecise external aborts in the CSPR, which is referred to as the A bit. Entry into the abort state caused by an imprecise external abort causes the DFSR to indicate the presence of an imprecise external abort. The FAR is not updated on an imprecise external abort on a data access.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-17
Virtual Memory System Architecture
External abort on a hardware page table walk
An external abort occurring on a hardware page table access must be returned with the page table data. Such aborts are precise. The FAR is updated on an external abort on a hardware page table walk on a data access, but not on an instruction access. The appropriate FSR (instruction or data) indicates that this has occurred.
Parity error reporting
Parity errors can occur as a precise (for example, from an L1 cache hit read) or an imprecise (for example, a cache linefill) abort. A fault status code is defined for reporting parity errors. It is IMPLEMENTATION DEFINED what parity error support is provided and whether the assigned fault status code or another appropriate encoding is used to report them.
B4-18
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
B4.6
Fault Address and Fault Status registers
Prior to VMSAv6, the architecture supported a single Fault Address Register (FAR) and Fault Status Register (FSR). VMSAv6 requires four registers: Instruction Fault Status Register (IFSR) updated on Prefetch Aborts Data Fault Status Register (DFSR) updated on Data Aborts Fault Address Register (FAR) updated with the faulting address for precise exceptions Watchpoint Fault Address Register (WFAR) updated on a watchpoint access with the address of the instruction that caused the Data Abort.
Note
The IFSR and DFSR are updated on Data Aborts because of instruction cache maintenance operations. For a description of precise and imprecise exceptions see Exceptions on page A2-16. VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR. It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of the architecture. A write flag (bit[11] of the DFSR) has also been introduced. Precise aborts resulting from data accesses (Precise Data Aborts) are immediately acted upon by the CPU. The DFSR is updated with a five-bit Fault Status (FS[10,3:0]) and the domain number of the access. In addition, the modified virtual address which caused the Data Abort is written into the FAR. If a data access simultaneously generates more than one type of Data Abort, they are prioritized in the order given in Table B4-1 on page B4-20. The highest priority abort is reported. Aborts arising from instruction fetches are flagged as the instruction enters the instruction pipeline. Only when, and if, the instruction is executed does it cause a Prefetch Abort exception. An abort resulting from an instruction fetch is not acted upon if the instruction is not used (for example, if it is branched around). The fault address associated with a Prefetch Abort exception is determined from the value saved in R14_abt when the Prefetch Abort exception vector is entered. If the Instruction Fault Address Register (IFAR) is implemented, then the modified virtual address which caused the abort will also be in that register. It is IMPLEMENTATION DEFINED whether the DFSR and FAR are updated for an abort arising from an instruction fetch, and if so, what useful information they contain about the fault. However, an abort arising from an instruction fetch never updates the DFSR and the FAR between the time that an abort arising from a data access updates them and the time of the corresponding entry into the Data Abort exception vector. In other words, a Data Abort handler can rely upon its FAR and DFSR values not being corrupted by an abort arising from an instruction fetch that was not acted upon. From VMSAv6, only the IFSR is updated by a Prefetch Abort.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-19
Virtual Memory System Architecture
Table B4-1 Fault status register encodings Architecture All VMSAv6 Priority Highest Sources Alignment PMSA - TLB miss (MPU) Alignment (deprecated) VMSAv6 Instruction Cache Maintenance Operation Fault External Abort on Translation Translation 1st level 2nd level Section Page Section Page Section Page FS [10,3:0] 0b00001 0b00000 0b00011 0b00100 Invalid Valid Domain a Invalid Invalid FAR Valid Valid
All
0b01100 0b01110 0b00101 0b00111 0b01001 0b01011 0b01101 0b01111 0b01000 0b01010 0b10100 0b11010
Invalid Valid Invalid Valid Valid Valid Valid Valid Invalid
Valid Valid Valid Valid Valid Valid Valid Valid Valid
All
All
Domain
All
Permission
VMSAv6
Precise External Abort External Abort, Precise (deprecated)
VMSAv6 VMSAv6
TLB Lock b Coprocessor Data Abort (IMPLEMENTATION
DEFINED)
Invalid Invalid
Invalid Invalid
VMSAv6 VMSAv6 VMSAv6 Lowest
Imprecise External Abort Parity Error Exception Debug event
0b10110 0b11000 0b00010
Invalid Invalid Valid
Invalid
IMPLEMENTATION DEFINED UNPREDICTABLE
a. domains only valid for the DFSR. b. see TLB lockdown procedure - translate and lock model on page B4-51.
B4-20
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
B4.6.1
Notes for fault status register encodings table
Prior to VMSAv6, the usage of FS[3:0] values associated with items marked as ARMv6 is IMPLEMENTATION DEFINED. This is true for either value of FS[10]. All other FS encodings are RESERVED. Before VMSAv6, and for VMSAv6 if the IFAR is not implemented, R14 must be used to determine the faulting address for Prefetch Aborts. Domain information is only available for data accesses. For Prefetch Aborts, the domain information can be determined by performing a TLB lookup for the faulting address and extracting the domain field. From VMSAv6: All Data Aborts cause the Data Fault Status Register (DFSR) to be updated so that the cause of the abort can be determined. All Instruction Aborts cause the Instruction Fault Status Register (IFSR) to be updated so that the cause of the abort can be determined. For all Data Aborts, excluding external aborts (other than on translation), the Fault Address register (FAR) will be updated with the address that caused the abort. External data aborts, other than on translation, can all be imprecise and hence the FAR does not contain the address of the abort. See section Imprecise data aborts on page A2-23 for more details on imprecise aborts. If a translation abort occurs during a data cache maintenance operation by modified virtual address, a Data Abort is taken and the DFSR indicates the reason. The FAR provides the faulting address. If a precise abort occurs during an instruction cache maintenance operation, then a Data Abort is taken, and an Instruction Cache Maintenance Operation Fault indicated in the DFSR. The IFSR indicates the reason. The FAR provides the faulting modified virtual address. The WFAR contains a copy of the PC: the address + 8 when executing in ARM state, and the address +4 when executing in Thumb state. The value is relative to the virtual address of the instruction causing the abort, not the modified virtual address. The WFAR is used to store the address of the instruction that caused the watchpoint access. If the IFAR is implemented, it holds the faulting address for a Prefetch Abort (other than Debug aborts).
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-21
Virtual Memory System Architecture
B4.6.2
Abort FSR/FAR update summary
For VMSAv6, a summary of which abort vector is taken, and which of the fault status and Fault Address registers are updated on each abort type is given in Table B4-2. The IFAR is optional. Table B4-2 Abort FSR/FAR update summary
Abort Type Instruction MMU fault Instruction debug abort Instruction external abort on translation Instruction external abort Instruction cache Parity error Instruction cache maintenance operation Data MMU fault Data debug abort Data external abort on translation Data external abort Data cache Parity error Data cache maintenance operation Here: Y N UNP
Vector PABORT PABORT PABORT PABORT PABORT DABORT DABORT DABORT DABORT DABORT DABORT DABORT
Precise Yes Yes Yes Yes Yes Yes Yes No Yes No No Yes
IFSR Y Y Y Y Y Y N N N N N N
DFSR N N N N N Y Y Y Y Y Y Y
FAR N N N N N Y Y N Y N N Y
WFAR N N N N N N N Y N N N N
IFAR Y UNP Y Y Y N N N N N N N
Register is updated on this abort type Register is not updated on this abort type.
UNPREDICTABLE.
B4-22
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
B4.7
Hardware page table translation
The MMU supports memory accesses based on sections or pages: Supersections (optional) Consist of 16MB blocks of memory Sections Consist of 1MB blocks of memory.
The following page sizes are supported: Tiny pages (not in VMSAv6) Consist of 1KB blocks of memory. Small pages Large pages Consist of 4KB blocks of memory. Consist of 64KB blocks of memory.
Sections and large pages are supported to allow mapping of a large region of memory while using only a single entry in the TLB. Additional access control mechanisms are extended within small pages to 1KB subpages, and within large pages to 16KB subpages. The use of subpage AP bits is deprecated in VMSAv6. The translation table held in main memory has two levels: First-level table Second-level tables Holds section and supersection translations, and pointers to second-level tables. Hold both large and small page translations. A second form of page table, fine rather than coarse, supports tiny pages.
The MMU translates modified virtual addresses generated by the CPU into physical addresses to access external memory, and also derives and checks the access permission. Translations occur as the result of a TLB miss, and start with a first-level fetch. A section-mapped access only requires a first-level fetch, whereas a page-mapped access also requires a second-level fetch. The value of the EE-bit in the System Control coprocessor is used to determine the endianness of the page table look ups. See Endian configuration and control on page A2-34 for more details.
Note
As the fine page table format and support for tiny pages is now OBSOLETE, definition of these features has been moved into a separate section, Fine page tables and support of tiny pages on page B4-35.
B4.7.1
Translation table base
The translation process is initiated when the on-chip TLB does not contain an entry for the requested modified virtual address. The Translation Table Base Register (TTBR in CP15 register 2) holds the physical address of the base of the first-level table.
ARM DDI 0100I
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
B4-23
Virtual Memory System Architecture
Prior to VMSAv6, a single TTBR existed. Only bits[31:14] of the Translation Table Base Register are significant, and bits[13:0] should be zero. Therefore, the first-level page table must reside on a 16KB boundary. VMSAv6 introduced an additional translation table base register and a translation table base control register: TTBR0, TTBR1 and TTBCR. On a TLB miss, the top bits of the modified virtual address determine if the first or second translation table base is used, see Page table translation in VMSAv6 on page B4-25 for a detailed description of the usage model. TTBR1 is expected to be used for operating system and I/O addresses, which do not change on a context switch. TTBR0 is expected to be used for process specific addresses. When TTBCR is programmed to zero, all translations use TTBR0 in a manner compatible with earlier versions of the architecture. The size of the TTBR1 table is always 16KB, but the TTBR0 table ranges in size from 128 bytes to 16KB, depending on the value (N) in the TTBCR, where N = 0 to 7. All translation tables must be naturally aligned. VMSAv6 has also introduced a control bit field into the lowest bits of the TTBRs, see Page table translation in VMSAv6 on page B4-25 for details.
B4.7.2
First-level fetch
Bits[31:14] of the Translation Table Base register are concatenated with bits[31:20] of the modified virtual address and two zero bits to produce a 32-bit physical address as shown in Figure B4-3. This address selects a four-byte translation table entry which is a first-level descriptor for a section or a pointer to a second-level page table.
31 14-X 13-X 0
Translation base
SBZ
31-X
20 19
0
Table index
31
14-X 13-X
21
0
Translation base
Table index
00
Figure B4-3 Accessing the translation table first-level descriptors
Note
Under VMSAv6, the Translation Base is always address [31:14] when TTBR1 is selected. However, the value used with TTBR0 varies from address [31:14] to address [31:7] for TTBCR values of N=0 to N=7 respectively. The value of X shown in Figure B4-3 to Figure B4-7 on page B4-34 is 0 if TTBR1 is used, and is the TTBCR value N if TTBR0 is used. Before VMSAv6, only the TTBR0 existed, and the value of X in these diagrams is always 0.
B4-24
Copyright 1996-1998, 2000, 2004, 2005 ARM Limited. All rights reserved.
ARM DDI 0100I
Virtual Memory System Architecture
B4.7.3
Page table translation in VMSAv6
VMSAv6 supports two page table formats: A backwards-compatible format supporting sub-page access permissions. These have been extended so certain page table entries support extended region types. A new format, not supporting sub-page access permissions, but with support for the VMSAv6 features. These features are: extended region types global and process specific pages more access permissions marking of shared and nonshared regions marking of execute-never regions.
Subpages are described in Second-level descriptor - Coarse pa