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### ee261_lecture_34

Course: EE 261, Fall 2008
School: Montana
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261 EE Introduction to Logic Circuits Lecture #34 Agenda 1. Programmable Logic Announcements : 1. Read 6.4, 6.5 and 6.7 EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 1 Programmable Logic Programmable Logic Devices (PLD) - when combinational logic gets large, it becomes impractical to implement using discrete devices - an alternative to an Application Specific Integrated Circuit (ASIC)...

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261 EE Introduction to Logic Circuits Lecture #34 Agenda 1. Programmable Logic Announcements : 1. Read 6.4, 6.5 and 6.7 EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 1 Programmable Logic Programmable Logic Devices (PLD) - when combinational logic gets large, it becomes impractical to implement using discrete devices - an alternative to an Application Specific Integrated Circuit (ASIC) is a programmable logic device - there are many types of programmable logic to choose from, each with advantages/disadvantages - PLA - PAL - CPLD - FPGA - the type of programmable device we target can influences how we minimize/synthesize our logic EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 2 Programmable Logic Array (PLA) Programmable Logic Array (PLA) - a PLA is a 2-level AND-OR configuration that implements SOP expressions - a PLA has: - n inputs - m outputs - p product terms - inputs are initially buffered and inverted to always create X and X literals - fuses (or reconfigurable switches) are used to selectively connect the literals to the AND level - fuses are again used to decide which product terms are connected to the OR level - pull-ups on the lines can produce constant outputs - logic configurations can also produce constant outputs EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 3 Programmable Logic Array (PLA) Programmable Logic Array (PLA) ex) 2-input, 2-output, 2-product term PLA the Xs represent where the fuses can be left connected or blown EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 4 Programmable Array Logic (PAL) Programmable Array Logic (PAL) - a PAL is an extension of a PLA but uses a fixed OR stage instead of a programmable one - since 0s going into an OR have no effect, this is possible - a PAL also has some additional functionality - Output enables - Output feed back Complex Programmable Logic Devices (CPLD) - multiple PLAs/PALs/PLDs can be put on one chip with a matrix of programmable interconnect - this is called a CPLD and gives the ability to begin building a system on a chip EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 5 FPGA's What is an FPGA Field Programmable Gate Array An FPGA uses Re-configurable Logic Blocks - we set the config bits of this block to set its Boolean logic function - the configuration is a Truth Table (or Look Up Table) of functionality In1 In2 config Out config 000 001 010 011 100 101 110 111 Out NOT(In1) NOT(In2) OR NOR AND NAND XOR XNOR EE 261 Introduction to Logic Circuits Fall 2008 Lecture Page #34 6 FPGA's LUTs = Look Up Tables - we can program the LUTs to be whatever type of gate is needed by the design - there are a finite number of LUTs within a given FPGA (also called "resources") The LUTs are configured into an ARRAY on the silicon - Array of LUT's = Array of Gates = Gate Array In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out In1 In2 config Out EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 7 FPGA's Programmable Interconnect - there are programmable interconnect switches that connect the LUTs LUT X X X X X LUT X X X X X LUT X LUT X LUT X LUT X LUT X LUT X LUT EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 8 FPGA's Configuration - We start with a Gate Level Schematic of our design (from synthesis) - The FPGA LUTs are configured to implement Gates LUT X X X X X LUT X X X X X LUT X LUT X LUT X LUT X LUT X LUT X LUT EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 9 FPGA's Configuration - The interconnect switches are then programmed to implement the net connections A B C INV X X X X X AND X X X X X LUT X INV X OR X LUT Out X LUT X LUT X LUT EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 10 FPGA's Configuration - The LUT and Interconnect configuration is volative (i.e., it goes away when power is removed) - Since the programming is done by the user after fabrication, we call it "Field Programmable" A B C INV X X X X X AND X X X X X LUT X INV X OR X LUT Out X LUT X LUT X LUT - We now understand where Field Programmable Gate Array EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 11 FPGA's Adding More Functionality - FPGA manufacturer's quickly learned that Flip-Flops would be useful - They put a DFF next to a 4-Input LUT to form a "Configurable Logic Block" (CLB) CLB X X X CLB X CLB X CLB EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 12 FPGA's Adding Even More Functionality - To Improve performance, common logic functions were "hard coded" on the silicon - Block RAM - Adders / Multipliers - Global Clock Buffers - even Microprocessors! EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 13 FPGA's What else can we program? - Which Pins to use on the package - What logic levels - CMOS_33, CMOS25 - SSTL, SSTL2, etc EE 261 Introduction to Logic Circuits Fall 2008 Lecture #34 Page 14
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