3182 CSCI Class Test 2
6:00 pm to 7:20 pm Thursday October 26th, 2000 Name:................................................................... FIVE pages Attempt all questions in the spaces provided. Use extra paper if necessary. Mark/40 CLEARLY SHOW HOW YOU OBAINED YOUR ANSWERS. NO MARKS FOR SIMPLY WRITING A NUMERIC ANSWER WITHOUT SHOWING HOW YOU OBTAINED IT. Qu. 1 Answer each of the following briefly: (a) Draw the logic circuit to implement the operation MAR PC, assuming two signals have been produced, one to select PC and one to select MAR. 2
Select PC as the source PC Q Logic 1 Q Selec MAR as the destination Clock
MAR D
D
Logic 1
Internal bus
(b) A microinstruction implements the step Rdestination Rsource where there are 24 possible sources and 34 possible destinations. How many bits are needed in the microinstruction to implement this step using a horizontal format? 2 58 bits (c) In a microprogrammed control unit, how is next microinstruction selected after one microinstruction has been to executed? 2 For non-branch microinstructions, the microprogram counter provides the address of the next microinstruction. For branch microinstructions, the next address is in the microinstruction (if the branch is taken)
(d) In a pipelined processor, what information would be passed from the operand fetch unit and the execute unit during the execution of the instruction LD R1, 100[R2]? 2 Opcode LD R1 (identification number) Contents of R2 100 (constant)
1
(e) A 1024-byte semiconductor memory chip has a 1 organization and a square array of memory cells. How many rows and columns are there in the array of memory cells? 2
25 rows and 25 columns
(f)
How is binary information represented in a dynamic semiconductor memory device?
2
Charge on a capacitor (no charge = one binary value, charge = other binary value)
(g)
Define the Principle Locality of as it applies to computer programs.
2
Two aspects: 1.Temporal locality (locality in time) individual locations, once referenced, are likely to be referenced again in the near future. 2.Spatial locality (locality in space) references, including the next location, are likely to be near the last reference.
(h) If the cache hit ratio is 0.95, the main memory access time is 50 ns, and the cache access time is 5 ns, what is the average access time of the memory system? 2
ta = tc + (1 - h)tm = 5 + 0.05 50 = 7.5 ns
(i) Suggest one disadvantage of the set-associative cache organization when compared to the direct mapped organization. 2 Needs a replacement algorithm or Two comparators instead of one 2
Qu. 2 Draw a suitable pipeline that could implement the following (CISC) machine instruction: MOV [R1],[R2] ;contents of a memory location whose address is held in R2 is ;copied to a memory location whose address is held in R1 Determine the information that must pass from one stage to the next in executing the instruction. Annotate your figure.
12 Register file
Instruction memory Instruction A...