Shortest Intrinsic Path Length: A New, Accurate A Priori Wirelength Estimator
Andrew B. Kahng [e-mail] Sherief Reda [e-mail]
VLSI CAD Laboratory University of CA, San Diego http://vlsicad.ucsd.edu/~sreda
Outline
Previous work and motivation Intrinsic Shortest Path Length (ISPL) definition Validation of ISPL as wirelength estimator Practical Applications: A Priori Total wirelength estimation A Priori Global interconnect prediction Relationship to Rent parameter
Definition and Applications
A priori wirelength estimation is the process of estimating and predicting the wirelength characteristics of VLSI netlists without knowledge of the netlist placement or floorplanning. Applications that benefit from a priori wirelength estimation: Physical driven synthesis Faster timing convergence Early system planning Determining amount of necessary whitespace VLSI netlist characterization/reverse engineering/creation
Previous Work
Previous approaches: Correlators: If some measure e correlates with net length l then e can be used in relevant applications, e.g., clustering. Typically no analytical modeling between l and e. Examples: mutual contraction and edge separability. Average wirelength estimators: Rent parameter-based. Predict aggregate wirelength characteristics, e.g., wirelength di...
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