Organization
Sequential Computer Logic and Memory Elements
Sequential Logic
Individual logic functions are decisionmaking functions s Combining these functions let us do more complex tasks s Sequential logic has time as an important factor
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Not just in the sense of propagation delay
Sequential Logic
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Feedback: outputs are fed back into the inputs
Change in input causes a change in an output This change is fed back as an input This can cause another output change Etc.
Problematic keeping track of time sequences of all the changes s Clocked sequential systems
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RS Latch
To create a 1-bit memory, we need a circuit to remember previous input values s Let output at time t+1 = output at time t regardless of the input values s The Reset-Set latch
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bistable (2 valid states) 2 inputs (Reset and Set) 2 outputs (Q and Q)
RS Latch
S R s Q Q RS Latch Truth Table R S Q Q 0 0 no change 0 1 1 0 1 0 0 1 1 1 invalid
S=HI, R=LO sets Q to HI s S=LO, R=HI resets Q to LO s S=LO, R=LO: Q remembers what it was previously
RS Latch
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RS Latch can be constructed with NOR gates
RS Latch
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Logic Works Simulation
RS Latch with Enable
The Enable allows the latch to operate when it is HIGH but when it is LOW prevents the latch from operating.
RS Latch with Preset and Clear
Preset and Clear override other inputs (See simulation)
D Latch / D Flip Flop
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A Latch is a level-triggered device
the latch will respond when the correct level is attached to the ENABLE input. Output responds to the input only at the transition between levels of the enabling signal Leading edge (from LO to HI) Trailing edge (from HI to LO)
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A flip flop is an edge-triggered device
D Latch / D Flip Flop
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D latch and D flip flop have one only input (D) and an enabling device (usually a clock)
D Latch / Flip Flop Truth Table Enable 0 0 1 1 D 0 1 0 1 Q Q no change no change 0 1 1 0
D Latch
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RS Latch with a single input
RS Latch
D can be latched into Q then enable removed. Then D is free to assume a new value
JK Flip Flop
It is often necessary to sample data at a certain point in time or at a regular interval. s This can be accomplished through edge triggering. s The JK Flip-Flop uses edge triggering to determine when the input information should be passed to the output.
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JK Flip Flop
The RS Latch has the pesky situation where RS = 11 is not allowed s Consider the following:
s S = JQ R = KQ Q = QK + Q Q = JQ + Q
JK Flip Flop
J 0 0 1 1 K 0 1 0 1 Qn+1 Qn 0 1 Qn
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See simulation (JKFF.cct)
JK Flip Flop
A single change in an input could trigger a sequence of changes in flip-flop states s Analysis is very complex s It is difficult to keep track of what happens when
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Tolerances of timing in gates inconsistent timing
JK Flip Flop
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Add a clock i...