of University California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz
Midterm I SOLUTIONS
October 13, 1999 CS252 Graduate Computer Architecture
Your Name: SID Number: Discussion Section:
Problem 1 2 3 4 Total
Possible 20 20 35 25 100
Score 20 20 35 25 100
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Question #1: Short Answer
1a) Give a simple definition of precise interrupts/exceptions: An interrupt / exception is precise if the instruction that cause the exception (or during which an interrupt occurred) and all the younger instructions have left no architecturally visible effects (other than in exception registers) and all the older instructions have completed.
1b) Explain how the presence of delayed branches complicates the description of a precise exception point (think about information that the operating system needs to continue execution after an exception)? If an instruction in the shadow of a branch (in a branch delay slot) causes an exception, it is not sufficient to return execution after handling the exception to the pc of the offending instruction because the previous branch has altered the control flow after the instruction.
1c) The Alpha 21064 (first version of the Alpha processor) supported precise exceptions for virtual memory but not for floating point operations. What sort of argument might be used to justify this complicated combination of behaviors? In VM exceptions, recovery is absolutely necessary (without which VM would not work). However, typically threads that cause FP exceptions are terminated, and thus it is not necessary for FP exceptions to be handled in a precise manner. VM exceptions tend to occur more frequently than FP exceptions. FP exception handlers can afford to make the exception precise in software if necessary.
1d) Explain the relationship between support for precise exceptions and support for branch prediction. What hardware structure supports both of these mechanisms in a modern out-oforder pipeline? Handling branch mispredictions and exceptions in a precise manner require younger speculative instructions to be rolled back. The re-order buffer supports both mechanisms.
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1e) When is it better to handle events via interrupts rather than polling? How about the reverse? Be specific. In systems where the variance in time between asynchronous events is high, polling can hurt performance and so interrupts are a better choice. In systems where events occur at predictable times (such as communication in scientific hand tuned code), polling can be more effective.
1f) Name 3 different things that people try to predict in modern processors: Branch direction, branch presence, jump targets, load/store dependencies, load values 1g) Why is branch prediction desirable? Calculating branch conditions can take several cycles, due to pipeline designs and dependencies. Branch prediction (if >50% accurate) allows stalls in long pipelines behind branches to be filled and allows multiple issue (or high issue rate) processors to schedule instructions across basic blocks (a branch occurs roughly every 6 instructions).
1h) Draw a simple diagram for each of the following branch predictors: GAg, PAg, PAp
Global Pattern History Table Global Branch History 2 bit ctr Per Branch-PC Pattern History Tables Per Branch-PC History 2 bit ctr 2 bit ctr 2 bit ctr
GAg
PAp
Global Pattern History Table Per Branch-PC History 2 bit ctr
PAg
1i) Explain the difference between implicit and explicit register renaming as defined in class: In implicit register renaming, there is no register mapping between physical and logical registers extra registers are available in distributed locations (e.g. in reservation stations) that can be used in certain specific ways. In explicit register renaming, a mapping exists and instructions are renamed to use physical registers rather than the logical ones.
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Problem #2: Superpipelining
Suppose that we have single-issue, in-order pipeline with one fetch stage, one decode stage, multiple execution stages (which include memory access) and a singe write-back stage. Assume that it has the following execution latencies (i.e. the number of stages that it takes to compute a value): multf (5 cycles), addf (3 cycles), divf (2 cycles), integer ops (1 cycle). Assume full bypassing and two cycles to perform memory accesses, i.e. loads and stores take a total of 3 cycles to execute (with address computation). Finally, branch conditions are computed by the integer execution unit.. 2a) Assume that this pipeline consists of a single linear sequence of stages in which later stages serve as no-ops for shorter operations. Draw the pipeline by naming each of the stages. Describe what is computed in each stage and show all of the bypass paths (as arrows). Your goal is to design a pipeline which never stalls unless a value is not ready. Label each of these arrows with the types of instructions that will forward their results along these paths (i.e. use "M" for multf, "D" for divf, "A" for addf, "I" for integer operations). [Hint: be careful about store instructions!]
I,D,Ld,A,M I,D,Ld,A I,D,Ld,A I,D I
Stage: F Fetch next instruction D Decode stage EX1 Integer Ops Address compute (for Ld/St) First stage of: Addf,Multf,Divf EX2 First stage of: Ld/St. Last Stage of: Divf, Second stage of: Addf, Mulff EX3 Last stage of: Ld/St, Addf Third stage of: Multf EX4 Fourth stage of: Multf EX5 Last stage of: Multf W Writeback stage
F
D Ex1 Ex2 Ex3 Ex4 Ex5 W
D Ld,A M
2b) How many extra instructions are required between each of these instruction combinations to avoid stalls (i.e. assume that the second instruction uses a value from the first). Be careful! Between a divf and an store: 0 Between a load and a multf: 2 Between two integer instructions: 0 Between a multf and an addf: 4 Between an addf and a divf: 2 Between an integer op and a store: 0
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2c) How many branch delay slots does this machine have? Explain.
This machine has 2 branch delay slots. This can be seen simply by considering the fact that the result of a branch comparison must somehow effect (forward in time!) a fetch:
F D E1 E2 F D E1 F D F
E3 E2 E1 D
E4 E3 E2 E1
E5 E4 E3 E2
W E5 W E4 E5 E3 E4
W E5
W
As a result, there must be 2 intervening instructions between the branch and the first instruction that is an actual taken branch.
2d) Would it make sense to add register renaming hardware to this pipeline? Why or why not? NO: Since this pipeline has in-order commit (as well as a read-early/write late pipeline), there are no WAR or WAW hazards. Hence, register renaming will buy you nothing.
2e) Could branch prediction increase performance of this pipeline? Why or why not?
YES. Without some form of prediction, we must expose the 2 delay slots (part c) to the compiler. It is hard to do a good job of filling two delay slots with useful instructions. Thus, we could "remove" the delay slots from the ISA and use branch prediction to predict instructions immediately after a branch. It is possible that a good branch prediction scheme could do a better job of finding two good instructions for these delay slots then the static compiler. Note, however, that this is very application dependent.
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Problem #3: Fixing the loops
For this problem, assume that we have a superpipelined architecture like that in problem (2) with the following use latencies (these are not the right answers for problem #2b!): Between a multf and an addf: 3 insts Between a load and a multf: 2 insts Between an addf and a divf: 1 insts Between a divf and a store: 7 insts Between an int op and a store: 0 insts Number of branch delay slots: 1 insts Consider the following loop which performs a restricted rotation and projection operation. In this code, F0 and F1 contain sin() and cos() for rotation. The array based at register r1 contains pairs of single-precision (32-bit) values which represent x,y coordinates. The array based at register r2 receives a projected coordinate along the observer's horizontal direction:
project: ldf multf ldf multf addf divf stf addi addi subi bneq nop F3,0(r1) F10,F3,F0 F4,4(r1) F11,F4,F1 F12,F10,F11 F13,F12,F2 0(r2),F13 r1,r1,#8 r3,r3,#1 r2,r2,#4 project
Total: 15 stall cycles
3a) How many cycles does this loop take per iteration? Indicate stalls in the above code by labeling each of them with a number of cycles of stall: Total cycles: 12 + 15 = 27
3b) Reschedule this code to run with as few cycles per iteration as possible. Do not unroll it or software pipeline it. How many cycles do you get per iteration of the loop now?
project: ldf ldf addi multf multf addi subi addf divf bneq stf F3,0(r1) F4,4(r1) r1,r1,#8 F10,F3,F0 F11,F4,F1 r2,r2,#4 r3,r3,#1 F12,F10,F11 F13,F12,F2 project -4(r2),F13
8 Stall cycles, 11 instructions 19 cycles/iteration
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3c)
Unroll the loop once and schedule it to run with as few cycles as possible per iteration of the original loop. How many cycles do you get per iteration now?
project: ldf ldf ldf multf multf ldf multf multf addf divf addf divf addi addi subi stf bneq stf F3,0(r1) F4,4(r1) F5,0(r1) F10,F3,F0 F11,F4,F1 F6,4(r1) F12,F5,F0 F13,F6,F1 F14,F10,F11 F15,F14,F2 F16,F12,F13 F17,F16,F2 r1,r1,#16 r2,r2,#8 r3,r3,#2 -8(r2),F15 project -4(r2),F17
So, total number of stalls = 5. Number of instructions = (7 x 2+4). Thus, we have 23/2 = 11.5 cycles/original iteration. The elusive "better" solution was just that. Elusive. This is probably the best solution. Thus, think of this part as worth 9 points (everyone lost 1 point gratuitously). 3d) Your loop in (3c) will not run without stalls. Without going to the trouble to unroll further, what is the minimum number of times that you would have to unroll this loop to avoid stalls? How many cycles would you get per iteration then? Once we get past 3 iterations, we can put all the loads together, all the multiplies together, etc. without any stalls until the stores. Thus, at the end, we have: DN I3 SN 1 B S So, between the first D and first S, we have (N-1) D's, and 3 I's. So, (N+2) = 7 N=5 So, we want a total of 5 iterations. #cycles/iteration= [(7x 5)+4]/5 = 7.8 cycles/iteration 3e) Software pipeline this loop to avoid stalls. Overlap 5 different iterations. What is the average number of cycles per iteration? Your code should have no more than one copy of the original instructions. Ignore startup and exit code.
project: stf divf addf multf multf ldf ldf addi subi bneq addi -16(r2),F13 F13,F12,F2 F12,F10,F11 F10,F3,F0 F11,F4,F1 F3,0(r1) F4,4(r1) r1,r1,#8 r3,r3,#1 project r2,r2,#4z
Cycles/iteration=11
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3f) Assume that you have a Tomasulo architecture with functional units of the same execution latency (number of cycles) as our deeply pipelined processor (be careful to adjust use latencies to get number of execution cycles!). Assume that it issues one instruction per cycle and has an unpipelined divider with a small number of reservation stations. Suppose the other functional units are duplicated with many reservation stations and that there are many CDBs. . What is the minimum number of divide reservation stations to achieve one instruction per cycle with the optimized code of (3b)? Show your work. [hint: assume that the maximum issue rate is sustained and look at the scheduling of a single iteration] Answer: 2. The best way to understand this is to actually look at the timing of issue slots. First, we take the use latencies from the beginning of this problem to extract the execution latencies (number of execution stages) for the different operations: Load: 3 cycles, Add: 2 cycles, Multiply: 4 cycles, Divide: 9 cycles (careful here!) Next, we show the timing of two iterations. Note that we assume that the WB (broadcast) of one operation and the scheduling of the next can occur in the same cycle:
Name ldf ldf addi multf multf addi subi addf divf bne stf ldf ldf addi multf multf addi subi addf divf bne stf ldf ldf addi multf Issue 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Start Execution 2 3 4 6 7 7 8 12 15 11 25 13 14 15 17 18 18 19 23 26 22 36 24 25 26 19 End Execution 4 5 4 9 10 7 8 13 23 11 27 15 16 15 20 21 18 19 24 34 22 38 26 27 26 22 Write Back 5 6 5 10 11 8 9 14 24 12 28 16 17 16 21 22 19 20 25 35 23 39 27 28 27 23
Looking at this table, we see that we only need 2 reservation stations: one that is running, and one waiting.
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Question #4: Explicit Register Renaming and Precise Interrupts
This problem describes a machine that uses a scoreboard for scheduling in combination with a reorder buffer and explicit register renaming. The constraints of this machine are as follows: Only one instruction can issue per cycle The Reorder buffer eight slots There are 32 architectural registers and an explicit rename unit with 64 physical registers There are 2 floating-point multiplier units There is 1 floating-point divider There are 2 floating-point adder units There is 1 load/store unit Floating-point multiplies and divides take 6 cycles to execute Floating-point adds take 2 cycles of execution Loads and stores take 1 cycle of execution Consider the following instruction sequence:
Start: ld addd multd divd ld addd subd addd nop F0,0(R12) F0,F0,F4 F2,F4,F6 F6,F2,F8 F6,10(R1) F12,F6,F14 F2,F8,F20. F8,F10,F6
4a) Page 11 shows the state of the machine after cycle #2. Mark up page 11 to show the status of the machine after the DIVD instruction is finished execution (just entering the WR stage). Feel free to cross out elements (e.g. to change an "N" to a "Y" or vice versa). 4b) Assume that the divide instruction caused a floating-point exception. What is the state of the machine after rollback has occurred to make this exception precise? Show your work on Page 12 (which again starts you with the state of the machine after cycle #2). 4c) Give the exact sequence of steps that would have been carried out by the hardware to get from your table in (a) to your table in (b). Write pseudo-code for this. If instruction at head of R.O.B. caused exception, starting from tail of R.O.B. until & including offending instruction: a. Replace new physical register in rename table with old physical register b. Put new physical register back at the head of the free list c. Mark R.O.B. entry invalid d. If instruction was using a FU, clear the unit & mark it not busy in the scoreboard 4d) What does a machine like the R10000K do to make it quicker to rollback for branch mispredictions? Keep a copy of the register rename table and free list at every branch speculation point. On a mis-speculation, the mapping can be restored. On confirmation of speculation, the mapping can be thrown away.
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After Cycle #2: write on this for problem (5a)
ScoreBoard (Functional Unit Status) Dest S1 S2 FU Op Fi Fj Fk Qj FU Qk Fj? Rj Fk? Rk
Time
Name MultF1 MultF1 Divide AddF1 AddF2 LD/ST
Busy N N N N N N
add
P34
[P4]
LD/ST
YES
YES
load
P32
[R12]
YES
Reorder Buffer
Dest Reg Old Reg Status (Cycle #) IS RO EX WR Value Done?
Entry
Valid
Instruction
1 2 3 4 5 6 7 8 9
N N N Y Y Y Y Y N
ld F0,0(R12) addd F0,F0,F4 multd F2, F4, F6 divd F6, F2, F8 ld F6, 10(R1) addd F12, F6, F14 subd F2, F8, F20 addd F8, F10, F6
P32 P34 P36 P38 P40 P42 P44 P46
P0 P32 P2 P6 P38 P12 P36 P8
1 2 3 4 5 6 9 13
2 5 4 12 6 9 10 14
3 7 10 18 7 11 12 16
4 8 11 8 12 13 17
Y Y Y N Y Y Y Y
Register Rename Table name reg busy? F0 F2 F4 P4 N F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
P34 P44 N N
P40 P46 P10 P42 P14 P16 P18 P20 P22 P24 P26 P28 P30 N N N N N N N N N N N N N
Free List (FIFO Managed) P36 P38 P40 P42 P44 P46 P48 P50 P52 P54 P56 P58 P60 P62 P0 P32 P2
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After Cycle #2: write on this for problem (5b)
ScoreBoard (Functional Unit Status) Dest S1 S2 FU Op Fi Fj Fk Qj FU Qk Fj? Rj Fk? Rk
Time
Name MultF1 MultF1 Divide AddF1 AddF2 LD/ST
Busy N N N N N N
add
P34
[P4]
LD/ST
YES
YES
load
P32
[R12]
YES
Reorder Buffer
Dest Reg Old Reg Status (Cycle #) IS RO EX WR Value Done?
Entry
Valid
Instruction
1 2 3 4 5 6 7 8 9
N N N N N N N N N
ld F0,0(R12) addd F0,F0,F4 multd F2, F4, F6
P32 P34 P36
P0 P32 P2
1 2 3
2 5 4
3 7 10
4 8 11
Y Y Y
Register Rename Table name reg busy? P36 F0 F2 F4 P4 N F6 P6 N F8 P8 N F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 N N N N N N N N N P0 N P32 N P2
P34 P36 N N
Free List (FIFO Managed) P38 P40 P42 P44 P46 P48 P50 P52 P54 P56 P58 P60 P62
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