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05_491_F04

Course: ECE 491, Fall 2009
School: Lafayette
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491 ECE - Senior Design I Lecture 5 - Lab 2; The Xilinx Microblaze Fall 2004 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu Where we are Last Time: New Verilog Material Coding guidelines initial blocks functions Tasks Verification and Testbenches Today: Discuss Lab 2 The Microblaze Processor ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 2 Lab...

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491 ECE - Senior Design I Lecture 5 - Lab 2; The Xilinx Microblaze Fall 2004 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu Where we are Last Time: New Verilog Material Coding guidelines initial blocks functions Tasks Verification and Testbenches Today: Discuss Lab 2 The Microblaze Processor ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 2 Lab 2 Overview 1. Parameterized counter (base on BCD example) BW parameter: bitwidth M parameter: counter modulus (counts from 0..M-1) Inputs: clk, reset, enb Outputs: Q, carry BW rclk Q carry enb eset 2. Generic counter testbench ECE 491 Fall 2004 Test counters with varying BW, M Modify self-check features to test different values Lecture 5 - Xilinx Microblaze 3 Lab 2 Overview (cont'd) 3. Write code to instantiate 4 counters with carry outputs generating 1MHz mhz_en 1KHz khz_en 1Hz hz_en 1/60 Hz min_en Connect all counters to common 50MHz clock Test using LED output ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 4 Lab 2 Overview (cont'd) 4. Create a digital clock Buttons: reset - sets time to 12:00 hr_set - advances 1 hr/sec min_set - advances 1 min/sec reset min_set hr_set ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 5 Lab 2 Overview (cont'd) 4. Create a digital clock (cont'd) Design ideas Use counters for clock digits (add extra logic where needed) Build a state machine or counter that time-multiplexes digits reset min_set hr_set ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 6 Review: BCD Counter How can it be parameterized? module bcdcounter(clk, reset, enb, Q, carry); input clk, reset, enb; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 9) & enb; always @( posedge clk ) begin if (reset) Q <= 0; else if (enb) begin if (carry) Q <= 0; else Q <= Q + 1; end end endmodule ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 7 Overview - Xilinx Microblaze Microblaze - a "soft processor core" 32-bit RISC Architecture similar to MIPS Pipelined (3 stages) Implementation in 1,000 Logic Cells (4,320 Logic Cells in a Xilinx XC3S200) Gnu development tools (gcc etc.) support programming Created and licensed by Xilinx Alternative Approaches: Xilinx Picoblaze - 8 bit soft core PowerPC - 32-bit hard core on Xilinx Pro Virtex-2 FPGAs Altera NIOS - 32-bit RISC soft core on Altera FPGAs Public domain cores - see www.opencores.org Lecture 5 - Xilinx Microblaze 8 ECE 491 Fall 2004 Microblaze Block Diagram ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 9 More Microblaze Features Harvard-style architecture w/ optional caches Several peripherals available Three interface buses Local Memory Bus (LMB) - simple synchronous bus On-Chip Peripheral Bus (OPB) - peripheral bus from IBM Fast Simplex Link (FSL) - for fast streaming comm. ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 10 Microblaze Registers and Memory 0 32 bits R0 R1 R2 31 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C 0 0 1 2 3 31 R30 R31 32 General Purpose Registers 0 0 PC = 0x0000001C MSR (Machine Status Reg.) Registers 31 31 0xfffffff4 0xfffffffc 0xfffffffc Memory (Big-Endian) ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 11 Microblaze Instructions All instructions exactly 32 bits wide Different formats for different purposes 6 bits 5 bits 5 bits 5 bits 11 bits Opcode 6 bits Rd 5 bits Ra 5 bits Rb 00000000000 16 bits Type A Opcode Rd Ra Imm. Value Type B ECE 491 Fall 2004 Lecture 5 - Xilinx Microblaze 12 Microblaze MSR CC Arithmetic Carry Copy DCE Data Cache Enable DZ Division by Zero ICE Instruction Cache Enable FSL FSL interface error BIP Break in Progr...

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Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 5 - Verilog Simulation &amp; DelayFall 2006 Read Verilog Handout Section 7Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduToday's Outline Discuss Lab 2 Verilog Pa
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ECE 491 - Senior Design ILecture 5 - Coding Guidelines; Simulation &amp; DelayFall 2007 Read Verilog Handout Section 7Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduToday's Outline Verilog Coding
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ECE 491 - Senior Design ILecture 6 - Microblaze (cont'd); C ProgrammingFall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduSome graphics in this presentation are taken from the Xilinx Micr
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 6 - Verification &amp; TestbenchesFall 2006 Read Verilog Handout Sections 7-10Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: Coding g
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 6 - Verification &amp; TestbenchesFall 2007 Read Verilog Handout Sections 7-10Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: Coding g
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 7 - C Programming (continued)Fall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduSome examples in this presentation are taken from B. Kernighan and D. Ritc
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 7 - Verification Case StudyFall 2006Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time Verification Techniques Today Finish Brooks Lect
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ECE 491 - Senior Design ILecture 7 - Verification Case Study - Pentium 4Fall 2007 Read Salt &amp; Rothery Ch. 4 (System Design) Colwell Ch. 3 (The Refinement Phase)Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@
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ECE 491 - Senior Design ILecture 8 - Data CommunicationsFall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduSome examples in this presentation are taken from B. Kernighan and D. Ritchie, T
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ECE 491 - Senior Design ILecture 8 - Data CommunicationsFall 2006 Reading: S&amp;R Ch. 3 - Requirements Analysis Colwell Ch 2 - The Concept Phase Short Quiz on FridayProf. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestor
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 8 - Data CommunicationsFall 2007 Reading: S&amp;R Ch. 4 (System Design) Colwell Ch 3 (The Refinement Phase)Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduData Comm
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 9 - Data Communications 2, Discuss Lab 4Fall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: Feedback from Lab 2 Network Protocol
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 9 - Requirements AnalysisFall 2006Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time Data Communications (cont'd) RS-232 Receiver Design
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 9 - Data Communications 2, Discuss Lab 4Fall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduThe following references were used for this lecture: J. Wakerly,
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ECE 491 - Senior Design ILecture 10 - Control/Datapath ParadigmFall 2006Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: Serial Data Encoding Requirements Analysis T
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ECE 491 - Senior Design ILecture 10 - System Design &amp; Project Mgt.Fall 2007 Reading:S&amp;R Ch.4 - System Design, S&amp;R Ch. 5 - Project Management Colwell Ch. 2 - The Concept Phase, Colwell Ch. 3 - The Refinement PhaseQuiz Friday 10/5: Sequential Veri
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ECE 491 - Senior Design ILecture 11 - Verilog (again), Timing, SynchrnizationFall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: More about Serial Communication C
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ECE 491 - Senior Design ILecture 11 - Data Communications 2Fall 2007 Quiz FridayVerilog ASM Diagrams Design Readings (S&amp;R Ch. 1-5, Colwell Ch. 1-3)Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.ed
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 12 Manchester Transmitter, Drivers &amp; ReceiversFall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: More about Verilog Coding Cloc
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 12 - MetastabilityFall 2007 Homework due Friday 10/3: Metastability problem, p. 18Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: Data
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ECE 491 - Senior Design ILecture 13 - ASM DiagramsFall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduAnnouncements 2 tutors needed for Junior Electronics contact Prof. Wey if interested
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 13 - More Data CommunicationsFall 2006 Quiz FridayVerilog Sequential Circuits Design ReadingsReading:S&amp;R Ch. 4 - 5 Colwell Ch. 2 - 3 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 14 - Communicating State MachinesFall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: More about Lab 5 - Test Circuit ASM Diagram
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ECE 491 - Senior Design ILecture 15- Project Assignment Part 1Fall 2004Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: Discuss Lab 6 - Manchester Receiver Today: Us
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 16 - Manchester Transmitter &amp; ReceiverFall 2007 Quiz Friday: Ethernet PaperProf. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: Handshaking
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ECE 491 - Senior Design ILecture 13 - Detailed DesignFall 2007 Reading: Colwell, Ch. 3-4, Design Reviews Salt &amp; Rothery Chapter 5, 6Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are
Lafayette - ECE - 491
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Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 17 - Intellectual PropertyFall 2007Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduThe New Yorker, May 16, 1953Today's Outline Types of Intellectual Property
Lafayette - ECE - 491
&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt; &lt;Error&gt;&lt;Code&gt;NoSuchKey&lt;/Code&gt;&lt;Message&gt;The specified key does not exist.&lt;/Message&gt;&lt;Key&gt;f87875fda8dc693bbf38ae9b7fe62e7918bcb628.ppt&lt;/Key&gt;&lt;RequestId&gt;D 87435E3D7D11A55&lt;/RequestId&gt;&lt;HostId&gt;8NxLyUhpK68SqY5bvkZQYFoo8b9
Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 18 - EthernetFall 2007Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduSome slides in this presentation are derived from Prof. Nick McKeown's class notes for CS
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Lafayette - ECE - 491
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Lafayette - ECE - 491
ECE 491 - Senior Design ILecture 21 - Cyclic Redundancy Check (CRC), BRAMFall 2007Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.eduWhere we are Last Time: Project Assignment Today: Cyclic R
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