491 ECE - Senior Design I
Lecture 5 - Lab 2; The Xilinx Microblaze
Fall 2004
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 [e-mail]
Where we are
Last Time:
New Verilog Material
Coding guidelines initial blocks functions Tasks
Verification and Testbenches
Today:
Discuss Lab 2 The Microblaze Processor
ECE 491 Fall 2004
Lecture 5 - Xilinx Microblaze
2
Lab 2 Overview
1. Parameterized counter (base on BCD example)
BW parameter: bitwidth M parameter: counter modulus (counts from 0..M-1) Inputs: clk, reset, enb Outputs: Q, carry
BW rclk Q carry enb eset
2. Generic counter testbench
ECE 491 Fall 2004
Test counters with varying BW, M Modify self-check features to test different values
Lecture 5 - Xilinx Microblaze
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Lab 2 Overview (cont'd)
3. Write code to instantiate 4 counters with carry outputs generating
1MHz mhz_en 1KHz khz_en 1Hz hz_en 1/60 Hz min_en Connect all counters to common 50MHz clock Test using LED output
ECE 491 Fall 2004
Lecture 5 - Xilinx Microblaze
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Lab 2 Overview (cont'd)
4. Create a digital clock
Buttons:
reset - sets time to 12:00 hr_set - advances 1 hr/sec min_set - advances 1 min/sec
reset min_set hr_set
ECE 491 Fall 2004
Lecture 5 - Xilinx Microblaze
5
Lab 2 Overview (cont'd)
4. Create a digital clock (cont'd)
Design ideas
Use counters for clock digits (add extra logic where needed) Build a state machine or counter that time-multiplexes digits
reset min_set hr_set
ECE 491 Fall 2004
Lecture 5 - Xilinx Microblaze
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Review: BCD Counter
How can it be parameterized?
module bcdcounter(clk, reset, enb, Q, carry); input clk, reset, enb; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 9) & enb; always @( posedge clk ) begin if (reset) Q <= 0; else if (enb) begin if (carry) Q <= 0; else Q <= Q + 1; end end endmodule
ECE 491 Fall 2004
Lecture 5 - Xilinx Microblaze
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Overview - Xilinx Microblaze
Microblaze - a "soft processor core"
32-bit RISC Architecture similar to MIPS Pipelined (3 stages) Implementation in 1,000 Logic Cells (4,320 Logic Cells in a Xilinx XC3S200) Gnu development tools (gcc etc.) support programming Created and licensed by Xilinx
Alternative Approaches:
Xilinx Picoblaze - 8 bit soft core PowerPC - 32-bit hard core on Xilinx Pro Virtex-2 FPGAs Altera NIOS - 32-bit RISC soft core on Altera FPGAs Public domain cores - see www.opencores.org
Lecture 5 - Xilinx Microblaze 8
ECE 491 Fall 2004
Microblaze Block Diagram
ECE 491 Fall 2004
Lecture 5 - Xilinx Microblaze
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More Microblaze Features
Harvard-style architecture w/ optional caches Several peripherals available Three interface buses
Local Memory Bus (LMB) - simple synchronous bus On-Chip Peripheral Bus (OPB) - peripheral bus from IBM Fast Simplex Link (FSL) - for fast streaming comm.
ECE 491 Fall 2004
Lecture 5 - Xilinx Microblaze
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Microblaze Registers and Memory
0 32 bits
R0 R1 R2
31 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C
0 0 1 2 3
31
R30 R31 32 General Purpose Registers
0 0
PC = 0x0000001C MSR (Machine Status Reg.) Registers
31 31 0xfffffff4 0xfffffffc 0xfffffffc
Memory (Big-Endian)
ECE 491 Fall 2004
Lecture 5 - Xilinx Microblaze
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Microblaze Instructions
All instructions exactly 32 bits wide Different formats for different purposes
6 bits 5 bits 5 bits 5 bits 11 bits
Opcode
6 bits
Rd
5 bits
Ra
5 bits
Rb
00000000000
16 bits
Type A
Opcode
Rd
Ra
Imm. Value
Type B
ECE 491 Fall 2004
Lecture 5 - Xilinx Microblaze
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Microblaze MSR
CC Arithmetic Carry Copy DCE Data Cache Enable DZ Division by Zero ICE Instruction Cache Enable FSL FSL interface error BIP Break in Progr...