421 CPE/EE Microcomputers
Instructor: Dr Aleksandar Milenkovic Lecture Note S21
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Course Administration
Instructor: Aleksandar Milenkovic [e-mail] www.ece.uah.edu/~milenka EB 217-L Mon. 5:30 PM 6:30 PM, Wen. 12:30 13:30 PM http://www.ece.uah.edu/~milenka/cpe421-05F Joel Wilder Lab #5 is on. Hw2 due is 11/02/05. 11/09/05 (MSP430 & related). Microprocessor Systems Design: 68000 Hardware, Software, and Interfacing
URL: TA: Labs: Test II: Text: Review:
M68K (Chapter 1; Chapter 2; Chapter 3), MSP430 (Introduction, Arch., Basic Clock System, WDT, Low Power Modes, Digital I/O), Timers, MSP 430 UART;
CPE/EE 421/521 Microcomputers M68000 Hw (Chapter 4)
Today:
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THE 68000 CPU HARDWARE MODEL Chapter 4
68000 interface Timing diagram Minimal configuration using the 68000
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68000 Interface
M68000: 64 pins, arranged in 9 groups:
Address Bus: Data Bus: Asynchronous bus control: Synchronous bus control: Bus arbitration control: Function code: System control: Interrupt control: Miscellaneous: Legend:
XX XX XX
A01 A23 D00 D15 AS*, R/W*, UDS*, LDS*, DTACK*, BERR* E, VPA*, VMA* BR*, BG*, BGACK* FC0, FC1, FC2 CLK, RESET*, HALT* IPL0*, IPL1*, IPL2* Vcc(2), Gnd(2) Type
Input Output Input/Output
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68000 Interface, cont'd
Classification of pins based on function
SYSTEM SUPPORT PINS
Essential in every 68000 system (power supply, clock, ...)
MEMORY AND PERIPHERAL INTERFACE PINS
Connect the processor to an external memory subsystem
SPECIAL-PURPOSE PINS (not needed in a minimal application of the processor)
Provide functions beyond basic system functions
Terminology
Asterisk following a name: indicates the signal is active low "Signal is asserted" means signal is placed in its active state "Signal is negated" means signal is placed in its inactive state
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System Support Pins
Power Supply
Single +5V power supply: 2 Vcc pins and 2 ground pins
Clock
Single-phase, TTL-compatible signal Bus cycle: memory access, consists of a minimum 4 clock cycles Instruction: consists of one or more bus cycles
RESET*
Forces the 68000 into a known state on the initial application of power:
supervisor's A7 is loaded from memory location $00 0000 Program counter is loaded from address $00 0004
During power-up sequence must be asserted together with the HALT* input for at least 100 ms. Acts also as an output, when processor executes the instruction RESET (used to reset peripherals w/out resetting the 68000)
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System Support Pins, cont'd
HALT*
In simple 68000 systems can be connected together with RESET* Can be used:
by external devices to make the 68000 stop execution after current bus cycle (and to negate all control signals) to single-step (bus cycle by bus cycle) through program to rerun a failed bus cycle (if memory fails to respond correctly) in conjunction with the bus error pin, BERR*
It can be used as an output, to indicate that the 68000 found itself in situation from which it cannot recover (HALT* is asserted)
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Memory and Peripheral Interface Pins
Address Bus
23-bit address bus, permits 223 16-bit words to be addressed Tri-state output pins (to permit devices other then the CPU to take a control over it) Auxiliary function:
supports vectored interrupts Address lines A01, A02, A03 indicate the level of the interrupt being serviced All other address lines are set to a high level
Data Bus
Bi-directional 16-bit wide data bus
During a CPU read cycle acts as an input During a CPU write cycle acts as an output
Byte operations: only D00-D07 or D08-D15 are active Interrupting device identifies itself to the CPU by placing an interrupt vector number on D00-D07 during an interrupt acknowledge cycle
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Memory and Peripheral Interface Pins, cont'd
AS*
When asserted, indicates that the content of the address bus is valid.
R/W*
Determines the type of a memory access cycle
CPU is reading from memory: R/W* = 1 CPU is writing to memory: R/W* = 0 If CPU is performing internal operation, R/W* is always 1 When CPU relinquishes control of its busses, R/W* is undefined
UDS* and LDS*
Used to determine the size of the data being accessed If both UDS* and LDS* are asserted, word is accessed R/W* UDS* LDS*
010: write lower byte (D00 D07: data valid, replicated on D8-D15) 011: write word (D00 D15: data valid) 101: read upper byte (D00 D07: invalid, D8-D15 data valid)
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Memory and Peripheral Interface Pins, cont'd
DTACK* (Data Transfer Acknowledge)
Handshake signal generated by the device being accessed Indicates that the contents of the data bus is valid If DTACK* is not asserted, CPU generates wait-states until DTACK goes low or until an error state is declared. When DTACK* is asserted, CPU completes the current access and begins the next cycle DTACK* has to be generated a certain time after the beginning of a valid memory access (timer supplied by the system designer).
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Memory and Peripheral Interface Pins, cont'd
Figure 4.3
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Special-Function Pins of the 68000
BERR* (Bus Error Control)
Enables the 68000 to recover from errors within the memory system
BR*, BG*, BGACK* FC0-FC2
(Bus Arbitration Control)
Used to implement multiprocessor systems based on M68000
(Function Code Output)
Indicate the type of cycle currently being executed Becomes valid approximately half a clock cycle earlier than the contents of the address bus
IPL0*-IPL2*
(Interrupt Control Interface)
Used by an external device to indicate that it requires service 3-bit code specifies one of eight levels of interrupt request
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Special-Function Pins of the 68000, cont'd
Function Code Output FC2 FC1 FC0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Processor Cycle Type Undefined, reserved User data User program Undefined, reserved Undefined, reserved Supervisor data Supervisor program CPU space (interrupt acknowledge)
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Special-Function Pins of the 68000, cont'd
Using the 68000's function code outputs
User data memory
User program memory
Supervisor program and data memory
Figure 4.8
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Special-Function Pins of the 68000, cont'd
Asynchronous Bus Control
Figure 4.11
The 68000 is not fully asynchronous because its actions are synchronized with a clock input
It can prolong a memory access until an ACK is received, but it has to be in increments of one clock cycle
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Interpreting the Timing Diagram
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Timing Diagram of a Simple Flip-Flop
Idealized form of the timing diagram
Actual behavior of a D flip-flop
Data hold time Data setup time Max time for output to become valid after clock
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General form of the timing diagram
An alternative form of the timing diagram
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The Clock
A microprocessor requires a clock that provides a stream of timing pulses to control its internal operations A 68000 memory access takes a minimum of eight clock states numbered from clock state S0 to clock state S7
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A memory access begins in clock state S0 and ends in state S7
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The most important parameter of the clock is the duration of a cycle, tCYC.
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At the start of a memory access the CPU sends the address of the location it wishes to read to the memory
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Address Timing
We are interested in when the 68000 generates a new address for use in the current memory access The next slide shows the relationship between the new address and the state the of 68000's clock
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In state S1 a new Initially, in state address becomes S0 the address valid for the remainder bus contains the of the memory access old address
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The time at which the contents of the address bus change can be related to the edges of the clock.
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Address Timing
Let's look at the sequence of events that govern the timing of the address bus The "old" address is removed in state S0 The address bus is floated for a short time, and the CPU puts out a new address in state S1
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The old address is removed in clock state S0 and the address bus floated
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tCLAV The designer is interested in the point at which the address first becomes valid. This point is tCLAV seconds after the falling edge of S0.
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The memory needs to know when the address from the CPU is valid. An address strobe, AS*, is asserted to indicate that the address is valid.
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Address and Address Strobe
We are interested in the relationship between the time at which the address is valid and the time at which the address strobe, AS*, is asserted When AS* is active-low it indicates that the address is valid We now look at the timing of the clock, the address, and the address strobe
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AS* goes active low after AS* the address has become valid goes inactive high before the address changes
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AS* goes low in clock state S2
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The Data Strobes
The 68000 has two data strobes LDS* and UDS*. These select the lower byte or the upper byte of a word during a memory access To keep things simple, we will use a single data strobe, DS* The timing of DS* in a read cycle is the same as the address strobe, AS*
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The data strobe, is asserted at the same time as AS* in a read cycle
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The Data Bus
During a read cycle the memory provides the CPU with data The next slide shows the data bus and the timing of the data signal Note that valid data does not appear on the data bus until near the end of the read cycle
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Data from the memory appears near the end of the read cycle
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Analyzing the Timing Diagram
We are going to redraw the timing diagram to remove clutter We aren't interested in the signal paths themselves, only in the relationship between the signals
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We are interested in the relationship between the clock, AS*/DS* and the data in a read cycle
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The earliest time at which the memory can begin to access data is measured from the point at which the address is first valid
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Data Address becomes valid becomes valid The time between address valid
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and data valid is the memory's access time, tacc
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Calculating the Access Time
We need to calculate the memory's access time By knowing the access time, we can use the appropriate memory component Equally, if we select a given memory component, we can calculate whether its access time is adequate for a particular system
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Data from the memory is latched into the 68000 by the falling edge of the clock in state S6.
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Data must be valid tDICL seconds before the falling edge of S6
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We know that the time between the address valid and data valid is tacc
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The address becomes valid tCLAV seconds after the falling edge of S0
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From the falling the address becomes valid edge of S0 to the the data is accessed falling edge of S6: the data is captured
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The falling edge of S0 to the falling edge of S6 is three clock cycles
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3 tcyc = tCLAV + tacc + tDICL
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Timing Example
68000 clock 8 MHz 68000 CPU 68000 CPU What is the minimum tacc? 3 tCYC = tCLAV + tacc + tDICL 375 = 70 + tacc + 15 tacc = 290 ns tCYC = 125 ns tCLAV = 70 ns tDICL = 15 ns
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Figure 4.14 CPE/EE 421/521 Microcomputers
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A 68000 Read Cycle
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DTACK* did no...