(Spring EE4243 09)
HW #5
Due 4/28/2009
1. In a cache system where a block size is equal to 32 words, for each of the following combinations (K denotes the bandwidth between memory and cache in words, and M denotes the degree of interleaving) calculate the miss penalty in clock cycles and use a simple time-graph to indicate which block from which memory module is being sent to cache in which clock cycle during a complete miss penalty period: (access time = 6cc, transfer time = 1cc/word for K = 1) (a) K = 1, M = 1 (b) K = 4, M = 1 (c) K = 1, M = 4 (d) K = 4, M = 2 (e) K = 2, M = 4
2. In a main memory of 64 words and block size (b) of 8 words, for of each the following combinations (K denotes the bandwidth between memory and cache in words, and M denotes the degree of interleaving), for each of the following arrangement (a) K = 2, M = 2 (b) K = 4, M = 2 (c) K = 2, M = 4 draw a complete physical memory map showing all memory modules with all physical addresses indicated in the map, bus connections from modules to the MUX and connect...