of Foundations Embedded Systems A Term Fall 2005 Lecture #18: Memory Organization in the PIC 16F877 Reading for Today: Reading for Next Class: Homework #4 is on web: PIC Lab #1: PIC Data sheet Sect 12, PIC Ref. Manual 46 Data sheet Sect 4,1415, PIC Ref. Manual 29, 32, 9 Due Monday 10/03/05
Signoff and Report due in you lab section next Weds. (Remember: Bonus points for Early Signoff/Submission!)
Last class: Introduced PIC 16F87X Microcontroller family This class: Discuss memory organization, data memory access, registers
Organization of Program Memory PC is13 bits wide
PC = Holds address of next instruction to be fetched PIC16F874A has 4K program memory. Only needs 12 of the address bits. (MSB ignored) PIC16F877A has 8K program memory. Needs all 13 address bits
Special Addresses in Program Memory: 0000h = RESET Vector = 1st instruction executed on powerup/reset Within first 4 instructions (00000003h) >> Will likely be a jump (GOTO) or branch to start of Main Code 0004h = INTERRUPT Vector = When interrupt occurs PC is set to 0004h >> From here it can jump to Interrupt Service Routine (ISR) Program Memory is Paged >> Program memory subdivided in to 2048 byte (2KB) pages >> Bits 4 and 3 of PCLATH register selects code memory page
>> PC will automatically increment across page boundaries in sequential operations Programmer DOES NOT have to set high bits in PCLATH >> For jumps/calls that cross page boundaries the PROGRAMMER MUST MODIFY bits <4:3> of PCLATH
Example: Structure of a general instruction and a call/goto instruction
HW Stack is 8 (and only 8!) instructions deep
Calls and Interrupts copy 13 bit address of next instruction (after call) from PC onto stack and pop it upon Return >> No direct programmer access to stack (i.e. no push or pop instructions) >> Stack is a Circular Buffer! >> If more than 8 addresses are pushed, the most recent will overwrite oldest!
Data memory organization: Spec >> Sheet a bit confusing.... says 16F877 has 368 bytes of data memory (RAM)
>> Actually has 512 bytes of RAM but only 368 bytes available for user data (i.e. General Purpose Registers, GPR ) >> Other 144 bytes are reserved for special function registers (SFR)
>> REMEMBER: Except for W, all registers actually locations in RAM! >> Even PC (i.e. PCL & PCLATH) and STATUS
Data memory is arranged into four 128 byte BANKS
Need 9 address bits to access 512 data memory locations 2 bits to select bank | 7 bits to index from 0 to 128 (007Fh) within bank >> Banks selected by using bits RP1: RP0 and IRP in the STATUS register (see Ref. Manual pg 57 for other STATUS bit definitions) STATUS:
Example: Direct Addressing
; define a variable named Temp in Bank0 cblock Bank0Ram Temp ; is at 0x20 = 20h in Bank0 endc
CLRF
STATUS
; Clear STATUS register (RP1:RP0=0 0 selects Bank0) ; Set RP0=1 and select Bank1 ; Clear RP0 and select Bank0 again ; MOV contents of W register to address 20h in Bank0 ; Clear RP0 and select Bank0 again ; Set RP1 = 0 and select Bank2 ; Both RP1:PR0 = 00 selects Bank3 ; selects Bank2 again
BSF STATUS, RP0 BCF STATUS, RP0 MOVWF Temp
BCF STATUS, RP0 BSF STATUS, RP1 BSF STATUS, RP0
BCF STATUS, RP0
Indirect Addressing: >> INDF register not a physical register. Just flags indirect addressing to be used. >> When INDF used in an instruction, the PIC forms the 9 bit address of the operand using the IRP bit from STATUS register and contents of File Select Register (FSR)
BCF MOVLW MOVWF CLRF INCF .... BSF CLRF MOVLW MOVWF
STATUS, IRP ; IRP = 0, select Bank0/1 for indirect addr 0x30 ; move 30h into W FSR ; move 30h into FSR INDF ; sets contents of addr 30h (Bank0) to 0 INDF ; increments contents at address 030h to 1
STATUS, IRP ; IPR = 1 select Bank2/3 INDF ; clears register at addr 1 00110000 = 130h 0x05 ; W = 5 INDF ; register at address 130h now equals 5