Assembly Introductory Language
Thorne : Chapter 3, Sections 7.1, 13.1, Appendix V.A (Irvine, Edition IV : 4.1, 4.2, 6.2 7.2, 7.3, 7.4)
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Intel 8086 Assembly Instructions
Assembly instructions are readable forms of machine instructions They use mnemonics to specify operations in a human-oriented short form Examples MOV (move) SUB (subtract) JMP (jump) Instructions have two aspects : operation and operands Operation (Opcode): how to use state variable values operands: which state variables to us Operands can be specified in a variety of ways that are called addressing modes Simple modes: register, immediate, direct More powerful: indirect
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Sample Instructions
Syntax MOV ADD SUB INC NOP AX, BX DX, CX DX, AX AX Semantics AX := BX DX := DX + CX DX := DX AX AX := AX + 1 (2 ops) (2 ops) (2 ops) (1 op) (0 op)
Instructions with two operands : destination (dest), source (src) MOV AX, BX Operation operand (dest), operand (src) (Opcode) (Order of dest and src is important, Must know on exams) ( p , )
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Instruction Syntax : Operand Compatibility
For all instructions with two operands, the two operands must be compatible (same size). In high level languages : type checking In assembly : same size Examples : MOV AH, CL 8-bit src and dest MOV AL, CX ?????
Example uses register mode, mode but compatibility is required for all addressing modes to come.
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Addressing Modes g
Syntax MOV ADD SUB SUB INC MOV MOV MOV AX, BX DX, 1 DX, [1] DX, var Semantics AX := BX DX := DX + 0001 DX := DX m[DS:0001] DX :=DX m[DS:var] Addresssing Mode Register,Register Register,Immediate Register,Direct Memory Register,Direct Memory
A variable declared in data segment (more later) g ( )
[BX] m[DS:BX]:= m[DS:BX]+1 Register Indirect AX, [BX+1] AX := m[DS:BX+1] Based Indirect AX, [BX+SI] AX := m[DS:BX+SI] Based-Index Indirect d d di AX, [BX+SI+1] AX := m[DS:BX+SI+1] Based-Index Indirect with Displacement p
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Addressing Mode : (1) Register
Register mode allows a register to be specified as an operand As a source operand : Instruction will copy register value As destination: write value to register A a d ti ti it l t it Example : p MOV AX, DX , AX := DX Contents of DX is copied to AX
register addressing mode for both dest and src
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Addressing Mode : (2) Immediate
Immediate mode allows a constant to be specified as source Constant value is encoded as part of the instruction E ample : MOV AL 5 Example AL, Because AL is an 8-bit destination, the instruction encoding includes 8-bit value 05h Example : MOV AX, 5 Because AX is a 16-bit destination, the instruction encoding includes the 16 bit value 0005h 16-bit Question : Is this possible ? MOV 4, BH ????
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Addressing Mode : (3) Direct Memory
Direct memory mode allows the address offset of a memory variable to be specified as an operand A constant address offset is encoded as part of the instruction The address offset is static : It must be known at assemblytime and remains constant through execution ... but the contents of that address may be dynamic During execution, the address offset is implicitly combined with DS Example : MOV AL, [5] Reads contents of byte at address DS:0005 BEWARE : Compare To Example : MOV var, AX Immediate Mode!! Assumes a variable is declared in data segment MOV AL, 5 Write contents of word at address DS:var
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Addressing Mode : (4a) Register Indirect
A register holds the address offset of the operand The register can only be : BX SI DI BP BX, SI, DI, DS is default segment for: BX, SI, DI SS is default segment for BP (later!) Syntax : [ register ]
Value in BX is used as address offset to a memory operand CPU loads AX with contents of contents of that memory
I di t Example: Indirect E l MOV AX, [ BX ] , [ ] = MOV AX, DS:[BX] AX:= m[DS:BX]
Indirect addressing mode use registers as a pointer, which is a convenient way to handle an array! (later) hi h i i t t h dl ! (l t )
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Addressing Mode : (4b) Indirect Indexed or Based Like register indirect, except you also specify a constant
e.g. [ BX + constant ] During execution, the processor uses a temporary register to calculate BX + constant It then accesses memory addressed by BX + constant y y Restriction: may only use BP, BX, SI or DI same as register indirect Example : MOV AX, [ BX +2 ] In both cases : = MOV AX, 2[BX] CPU computes address = Value in AX = MOV AX, [BX][2] BX+2 MOV AX, [ BX +var ] = MOV AX, var[BX]
CPU loads AX with of that address
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Addressing Mode (4c) : Indirect Based-Indexed Based Indexed
It is like indexed, except you use a second register instead of a constant
e.g. [ BX + SI ] During execution, the processor uses a temporary register to calculate sum of register values It then accesses memory addressed by sum Restrictions: one must be base register: BX (or BP later!) one must be index register: SI or DI The only legal forms: [ BX + SI ] [ BP + SI ] [ BX + DI ] [ BP + DI ]
base = BX base = BP
Default DS Default SS
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Addressing Mode (4c) : Indirect Based Indexed with Based-Indexed Displacement
It is like based-indexed mode, except includes a constant too , p e.g. [ BX + SI + constant ] During execution, the processor uses a temporary register to calculate sum of values It then accesses memory addressed by sum Restrictions: same as based mode
MOV = MOV = MOV MOV = MOV AX, [ BX + SI + 2 ] AX, [BX][SI+2] AX, AX 2[BX+SI] AX, [ BX + SI + var ] AX, var[BX][SI]
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In both cases : CPU computes address = Value in BX+SI+2 CPU loads AX with of that address
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Loading Registers with Addresses
Before most instructions that use indirect addressing, the registers have to be loaded with address. Two alternatives : MOV BX, OFFSET W
Functionally equivalent!
LEA BX, W Both calculate and load the 16-bit effective address a of memory operand.
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Segment Override
Required for exam : Restricted uses of registers MOV [DX], AX Marks will be deducted. Recall : DS is default segment for: BX, SI, DI SS is default segment for BP (later!) MOV [BX], AL = = MOV DS:[BX], AL MOV [BP], AL = = MOV SS:[BP], AL
At times, you may run out of registers and need to use either the index registers or the segment registers outside of their assigned default roles (eg. duplicating data structures), MOV SS:[BX], AL MOV ES:[BX], AL MOV DS:[BP], AL DS [BP]
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Operand Compatibility with Memory Operands
Clear and unambiguous Examples MOV [0BCh], AX MOV [BX], AL [BX] Why ? Because the other REGISTER operand determines size Ambiguous Examples : MOV [0BCh], 1 MOV [BX], 0 Why ? The immediate operand could be 8 bits or 16 bits ? How does the assembler decide ?
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Operand Compatibility with Memory Operands
Memory Access Qualifiers WORD PTR BYTE PTR word pointer 16-bit operand byte pointer 8-bit operand
Example : l MOV BYTE PTR [0FF3E], 1 8 bit destination, no ambiguity g y MOV WORD PTR [BX], 0 16-bit destination, 16 bit destination no ambiguity
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Assembler Tip About Operand Compatibility
W DW 0AA33h ... MOV AL W AL,
16-bit memory src operand 8-bit 8 bit register dest operand
g The assembler will generate an error Basic "type checking"
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Programs to do simple arithmetic
Problem : Write a code fragment to add the values of memory locations at DS:0, DS:01, and DS:02, and save the result at DS:10h. Solution: Step 1 Processor Memory AL m[DS:00] Step 2 DS:00 10h AL AL + m[DS:01] DS:01 20h AL=10h/30h/44h Step 3 AL AL + m[DS:02] [DS 02] DS:02 14h Step 4 DS:10 AL MOV AL, [0000] ADD AL, [0001] , [0002] ] ADD AL, [ MOV [0010h], AL
DS:10h FFh 44h
DS is default!
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Learning how to read a reference manual on assembly instructions
We've seen that instructions often have restrictions registers, addressing mode For each instruction whether in textbook or in processor s programming processor's manual - the permitted operands and the side-effects are given
Thorne text, Appendix V.A "Instruction set summary text V A Instruction summary"
ADD Instruction Formats : ADD reg, reg ADD reg, immed ADD mem, reg ADD mem, immed ADD reg, mem ADD accum, immed Is this permitted : ADD X, Y ?
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Flag status affected: AF, PF, CF, SF, OF, AF PF CF SF OF ZF
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Learning how to read a reference manual on assembly instructions
MOV Instruction Formats : MOV reg, reg MOV mem, reg g, MOV reg, mem MOV reg16, segreg MOV segreg, reg16
Flag t t Fl status affected: ff t d None
MOV reg,immed i d MOV mem, immed MOV mem16, segreg , g g MOV segreg, mem16
Segment registers (CS, DS, SS, ES) are 16-bit!
Question: Suppose we want to initialize DS with a constant value 45DFh ?
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Understanding High-Level Control Flow at Machine Level
Execution of data transfer/manipulation instruction advances CS:IP to next q sequential instruction. Execution of control flow instructions changes address for fetch of next instruction. For example : If condition is true, continue sequentially then skip to next_statements next statements If condition is false, skip to false_statements, then continue sequentially Skip = control flow or jumps Conditions depend on the status flags ( (zero, carry, overflow, sign, parity) , y, , g , p y) ( ZF, CF, OF, SF, PF)
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Conditional Statements : if ( condition ) { true_statements; } else { false_statements; _ } next_statem...