10
2/17/08
Lecture Today we will continue with Analog-toDigital Converters Remember
Quiz #2 next Thursday (2/19/09) Lab material will be fair game for any quiz or test
General Comments
Use the correct measurement equipment (eg scope vs. DMM) Use the equipment correctly. grounding, connections, etc. Ask questions. Make sure you know how the hardware works. Adjust voltages before you apply power to the circuits you built. Make you circuit boards neat. It will be a lot easier to debug. Use a logical approach when debugging. Be like the SAR on the SA ADC and cut the problem in half, then again in half, etc.
We were looking at types of ADCs
Investigate the operation of the converters And then briefly compare the basic properties
Next one we will look at is the Flash or Parallel ADC
Fastest of all ADC 100s GHz conversion rates Consist of a bank of comparators ( 2n ) Extensive decoding logic in some cases High power dissipation No clock necessary Major disadvantages power consumption and complexity
FLASH ADCs - Most high-speed oscilloscopes and some RF test instruments use flash ADCs because of their fast digitizing rate, which now reaches 5 Gsamples/s for offthe-shelf devices and 100s Gsamples/s for proprietary designs. - The typical flash converter resolves analog voltages to 8 bits, although sizes are continuing to increase and some flash converters can resolve 10+ bits.
3-Bit Flash ADC
Typical Waveforms
Conversion takes place when input changes by approximately one LSB.
Conversion rate limited by the propagation delay through the device
Flash ADC circuit configuration
Outputs are not binary so decoding is necessary
Flash ADC circuit configuration
Example 2 bit flash ADC
Heres an example of the logic in a two bit flash converter Note if Vref is 8 volts,
Then resolution is 2 volts Transitions occur at 1, 3, and 5 volts. Maximum digital output is 11
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Change the VTC
Note the Voltage Transfer Characteristic (VTC) of the device can be easily altered by simply changing resistor values, so the switch points can be changed to create whatever profile you want.
Flash ADC circuit configuration
Sub-ranging Flash ADC
Combining parallel conversion for moderate number of bits (eg. 8) with iteration it is possible to strike a compromise that gives
Better resolution than a full parallel approach Less complex structure Improved speed over a counter type ADC Uses a clock (strobe) to synchronize operations
Called by different names
Two step flash ADC Subranging ADC
Sub-ranging Flash ADC
Operation similar to flash except: Conversion produces most significant portion of output word. This portion is stored and converted to analog value with a fast DAC Analog result is subtracted from the input, and resulting residue is amplified, converted to digital value and combined with first part to form total output word.
Sub-ranging Flash ADC
Example of a Sub-ranging Flash Converter Design
Sigma Delta
ADC
Features: high resolution , high accuracy , low noise, low cost. Good for applications such as speech, audio.
Sigma-delta ADCs
Sigma-delta converters , also called oversampling converters, consist of 2 major blocks: modulator and digital filter . The modulator, whose architecture is similar to that of a dual-slope ADC, includes an integrator and a comparator with a feedback loop that contains a 1-bit DAC. The modulator oversamples the input signal, transforming it to a serial bit stream with a frequency well above the required sampling rate. The higher the clock, the higher the precision of the sigma-delta converter. In real world applications the flip-flop clock rate is typically 64 times higher than the sampling rate (an over-sampling rate of 64)
Sigma-delta ADCs
The output filter then converts the bit stream to a sequence of parallel digital words at the sampling rate. The delta-sigma converters perform high-speed, low resolution (1-bit) A/D conversions, and then remove the resulting high-level quantization noise by passing the signal through analog and/or digital filters. Called noise shaping, due to over-sampling, the quantization noise is moved to the high frequencies and not spread all over the spectrum as it occurs other with designs. With the noise concentrated in a specific portion of the spectrum at frequencies above the sampling rate, it is quite easy to construct a filter to remove the noise improving the SNR of the system.
The bit-stream is a one-bit serial signal with a bit rate much higher than the data rate of the ADC
Its major property is that its average level represents the average input signal level
The low pass filter at the output is required because you have to gain the average signal level out of the bitstream
Modulator
This is equivalent to the DAC
Counter C1 keeps track of clock periods, while counter C2 counts the number of pulses when the switch is closed. Suppose C1 is 1000. By the time it gets the final count, the number in C2 is proportional to the average level of the input signal during the time of 1000 clock pulses.
Delta-Sigma () ADC
In a converter, the analog input voltage signal is connected to the input of an integrator, producing a voltage rate-of-change, or slope, at the output, corresponding to input magnitude which is the difference between the input and the DAC output. This ramping voltage is then compared against ground potential (0 volts) by a comparator. The comparator acts as a sort of 1-bit ADC, producing 1 bit of output ("high" or "low") depending on whether the integrator output is positive or negative. The comparator's output is then latched through a D-type flip-flop clocked at a high frequency, and fed back to to a DAC whose output is fed to another input channel on the integrator, to drive the integrator in the direction of a 0 volt output.
The bit stream average level represents the analog input signal average voltage. Since the clock rate used at the flip-flop is very high, data is sample many times over the desired sampling rate (oversampled).
The low pass filter at the output is required because you have to gain the average signal level out of the bitstream
As shown in the schematic, the input analog voltage drives an integrator, whose output is compared with a ground voltage level by a comparator. D-latch controls a switch turning on/off a reference voltage, they both are composing a 1-bit DAC. As the input voltage increases or decreases, the comparator turns on and off the reference voltage, that is subtracted from the input signal, aiming to maintain zero on the output of the integrator. A counter (say C1) keeps track of clock periods, while another counter (C2) counts the number of pulses when the switch is closed. Supp...