68000 THE CPU HARDWARE MODEL
Outline
Emphasis on the 68000's interface to
memory and its read and write cycles. protocols required to ensure a reliable exchange between the CPU and its memory.
Introducing the timing diagram and the
CPUs spend most of the time reading data from memory and writing data to memory.
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1
68000 INTERFACE
The 68000 has 64 pins arranged in 9 groups. Each group of pins is labeled by the function it
performs.
The 9 groups are divided into 3 categories:
1. The system support pins 2. The memory and peripheral interface pins 3. The special-purpose pins
A pin can act as an input, output, or
input/output pin.
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68000 INTERFACE CONT'D
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2
Convention
An asterisk following a name indicates that the
signal is active-low; i.e. the electrically low level (e.g. 0 V) is the true level.
Asserted : Means that the signal is placed in
its active state.
Negated : Means that the signal is placed in
its inactive state.
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Some Terminologies
A memory access is called a bus cycle and
consists of a minimum of 4 clock cycles.
Executing an instruction consists of one or
more bus cycles.
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System Support Pins
The system support pins comprise
the following functions: Power supply (4 pins) 1 pin each for:
Clock Reset Halt
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System Support Pins Cont'd
Power Supply : Is a single power supply of
5 0.05 Volts.
Two Vcc pins and two ground pins are
provided to reduce the voltage drop between the Vcc terminals of the chip and Vcc conductors within the chip itself. signal, should be free running!
Clock : A single phase, TTL compatible
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4
System Support Pins Cont'd
An implementation of Power (VCC, GND) and CLK pins.
COE...
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