Computer Parallel Architectures
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Parallel Computer Architectures
(a) On-chip parallelism. (b) A coprocessor. (c) A multiprocessor. (d) A multicomputer. (e) A grid.
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Instruction-Level Parallelism
(a) A CPU pipeline. (b) A sequence of VLIW instructions. (c) An instruction stream with bundles marked.
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The TriMedia VLIW CPU (1)
A typical TriMedia instruction, showing five possible operations.
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The TriMedia VLIW CPU (2)
The TM3260 functional units, their quantity, latency, and which instruction slots they can use.
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The TriMedia VLIW CPU (3)
The major groups of TriMedia custom operations.
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The TriMedia VLIW CPU (4)
(a) An array of 8-bit elements. (b) The transposed array. (c) The original array fetched into four registers. (d) The transposed array in four registers.
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On-Chip Multithreading (1)
(a) (c) Three threads. The empty boxes indicated that the thread has stalled waiting for memory. (d) Fine-grained multithreading. (e) Coarse-grained multithreading.
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On-Chip Multithreading (2)
Multithreading with a dual-issue superscalar CPU. (a) Fine-grained multithreading. (b) Coarse-grained multithreading. (c) Simultaneous multithreading.
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Hyperthreading on the Pentium 4
Resource sharing between threads in the Pentium 4 NetBurst microarchitecture.
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Homogeneous Multiprocessors on a Chip
Single-chip multiprocessors. (a) A dual-pipeline chip. (b) A chip with two cores.
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Heterogeneous Multiprocessors on a Chip (1)
The logical structure of a simple DVD player contains a heterogeneous multiprocessor containing multiple cores for different functions.
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Heterogeneous Multiprocessors on a Chip (2)
An example of the IBM CoreConnect architecture.
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Introduction to Networking (1)
How users are connected to servers on the Internet.
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Introduction to Network Processors
A typical network processor board and chip.
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The Nexperia Media Processor
The Nexperia heterogeneous multiprocessor on a chip.
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Design Issues
What is the nature, size, and number of the processing elements From ALUs CPUS If a processing element is very small (fractions of a chip) can use vast quantities But, trend is to use COTS components which influence design a) b) What are the nature, size, and number of memory modules? Elaborate caching schemes are used to speed-up systems (multi-level caching) Sizes in Giga-bytes
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Design Issues
How are processing & Memory elements interconnected? In two ways: Static (ring,star,grid) or Dynamic (switching network that can dynamically route msgs)
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Design Issues
EXS: Big time-sharing system (8 n CPUs): can handle thousands of users, immense Transaction systems. Single Job consisting of many parallel processes: (chess game) Grain Size: refers to algorithms and s/w a) Coarse-grained parallelism: running large s/w modules in parallel with little or no communication amongst them Fine-grained parallelism: complete opposite.
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b)
Design Issues
EXS:
CPUs: a) Loosely coupled: systems with small number of large, independent CPUs that have low-speed connections b) Tightly coupled: opposite of loosely coupled
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Design Issues
a) Notes: Generally, problems with coarse grained parallelism work best on loosely-coupled systems, and the opposite is also true. This is only a very general view, real world apps. can be really different. Fine-grained parallelism works best in tightly-coupled systems, again this is a general view. Today's systems range over a vast number of specialized architectures.
a)
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Communication Models
a) Multiprocessors - (also shared memory system; all CPUs share a common physical memory) * Any process can r/w a mem. word by exec'ing a LOAD/STORE. * Fig. 8-17. A multiprocessor with 16 CPUs each processing a piece of the image via a dedicated process. Note each process may have access to entire image if needed. * Exs: Sun E-25k, Sequent NUMA, SGI Origin
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Communication Models
Multi-computers - (also distributed memory system; each CPU has its own private memory) a) They may be loosely-coupled, cannot communicate with just r/w. b) Fig. 8-18. A multicomputer with 16 CPUs. Image split-up req'd. Exs: Wisconsin COW, IBM SP/2, Intel O-Red
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Multiprocessors
(a) A multiprocessor with 16 CPUs sharing a common memory. (b) An image partitioned into 16 sections, each being analyzed by a different CPU.
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Multicomputers (1)
(a) A multicomputer with 16 CPUs, each with its own private memory.
(b) The bit-map image of Fig. 8-17 split up among the 16 memories.
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Communication Models
Communication betw. processes often uses primitives, send/recv, thus the s/w architecture is very complex. Why use it? Cheap and easy to build... a) The trick is to design/find architectures that are truly scalable. b) Scalability - designs that continue to perform well as CPUs are added. c) Hybrid systems - some combination of multi-computer / multiprocessor.
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Communication Models
Hybrid System Types: a) Implement shared memory at any of the architecture layers/levels Fig. 8-19, the H/W layer, b) OS layer c) Compiler run-time system.
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Multicomputers (2)
Various layers where shared memory can be implemented. (a) The hardware. (b) The operating system. (c) The language runtime system.
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Communication Models
a) Distributed shared memory (DSM) - Single, system-wide paged shared virtual address space spread across the CPUs by the OS, not the multi-computer h/w. b) If a CPU does LOAD/STORE on a page it doesn't have, a trap to the OS occurs OS will carry out VM algorithms... c) User-level Runtime Shared Memory - Programming language provides some shared memory abstraction API, which is implemented by the compiler and runtime system.(ISA) a) * Exs: Linda runtime system, ORCA model of shared objects
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Taxonomy of Parallel Computers (1)
Flynn's taxonomy of parallel computers.
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Taxonomy of Parallel Computers (2)
A taxonomy of parallel computers.
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Taxonomy of Parallel Computers
a) Fig 8-20 - Flynn's classification is based on two things (pretty much independent of each other): a) Instruction Streams: corresponds to a program counter, i.e. a system with n CPUs has n program counters n instruction streams. a) Data Streams: consists of a set of operands and instructions.
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Taxonomy of Parallel Computers
a) SISD = Von Neumann architecure b) SIMD = single CU that issues one instruction at a time, but has multiple ALUs to carry out on multi-data sets simultaneously. c) MISD = multiple instructions operating on same data. Pipelined machines may fit this model. d) MIMD = independent multi-CPUs operating as part of a larger one.
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Taxonomy of Parallel Computers
a) Fig 8-21 - Flynn's classification extensions: a) SIMD = split in 2 subgroups: one is for numeric supercomputers and vector processing systems, a 2nd one is for parallel-type systems with a master CU that feeds instructions to many independent ALUs a) MIMD = split into multiprocessors (shared memory) and multi-computers (message passing).
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Taxonomy of Parallel Computers
a) Multiprocessors = (based on shared memory implementation), UMA (uniform Mem Access), NUMA (non-uniform Mem Access), and COMA ( cache only Mem access). a) Multi-computers = MPPs (massively parallel computers), NOW (network of workstations), and COW (cluster of workstations)
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Memory Semantics Sequential Consistency
(a) Two CPUs writing and two CPUs reading a common memory word. (b) - (d) Three possible ways the two writes and four reads might be interleaved in time.
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Weak Consistency
Weakly consistent memory uses synchronization operations to divide time into sequential epochs.
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Release Consistency
Release consistency memory alleviates the inefficiency of Weak consistency by adopting a model akin to critical sections of code When a process exists a critical region, it's not necessary to force all writes to completion immediately. The key is that all writes should complete before the next critical section is entered.
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UMA Symmetric Multiprocessor Architectures
Three bus-based (a) multiprocessors. Without caching. (b) With caching. (c) With caching and private memories.
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Snooping Caches
The write through cache coherence protocol. The empty boxes indicate that no action is taken.
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The MESI Cache Coherence Protocol
The MESI cache coherence protocol.
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UMA Multiprocessors Using Crossbar Switches
(a) An 8 8 crossbar switch. (b) An open crosspoint. (c) A closed crosspoint.
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UMA Multiprocessors Using Multistage Switching Networks (1)
(a) A 2 2 switch. (b) A message format.
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UMA Multiprocessors Using Multistage Switching Networks (2)
An omega switching network.
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NUMA Multiprocessors
A NUMA machine based on two levels of buses. The Cm* was the first multiprocessor to use this design.
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Cache Coherent NUMA Multiprocessors
(a) A 256-node directory-based multiprocessor. (b) Division of a 32-bit memory address into fields. (c) The directory at node 36.
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The Sun Fire E25K NUMA Multiprocessor (1)
The Sun Microsystems E25K multiprocessor.
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The Sun Fire E25K NUMA Multiprocessor (2)
The SunFire E25K uses a four-level interconnect. Dashed lines are address paths. Solid lines are data paths.
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Message-Passing Multicomputers
A generic multicomputer.
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Interconnection Nets
a) Fig. 8-18 showed multi-computers using interconnection networks. Often, multiprocessors have a number of mem. Modules that work with one another + CPUs. Message Passing is implied... b) Components of interconnection network: 1. CPUs 2. Memory modules 3. Interfaces: drive msgs I/O to/from CPUs and Mems. 4. Links: Physical busses/channels with bandwidth and comm modes (duplex, simplex, etc) as the properties 5. Switches: Multi-I/O port devices -> similar to doublymultiplexor functions.
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Interconnection Nets
Network topologies: Describes how an I-Net links and switches are arranged. Properties: - Number of links is known as the degree of the node or fanout - Diameter of the I-Net dictates the worst-case msgs delay distance between 2 nodes that are farthest apart. - Transmission Capacity is how much data it can move per second bisection bandwidth metric which is the minimum of all possible partitions (one of the most important metric) - Dimensionality: number of choices to go from source to destination. Zero-d when there is only one choice, 2-d if east-west or north-south
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Interconnection Nets
Network topologies (fig 8-35) examples: (a) zero-d STAR, central node does the switching (b) zero-d FULL Interconnect. This design maximizes bisection bandwidth, every node has direct connection to every other node. The number of links = k(k-1)/2 (c) zero-d TREE has bisection bandwidth = link capacity (not good) (d) 1-d RING can send packets left or right.
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Interconnection Nets
Network topologies (fig 8-35) examples: (e) 2-d GRID or MESH has a diameter that increases as the SQRT(number of nodes). Very popular. (f) DOUBLE TORUS is a grid with edges connected. More fault tolerant and smaller diameter. (g) CUBE and others have diameter = base 2 Log of node count. So, a 10-dimension hypercube has 1k nodes with diameter=10 only
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Topology
Various topologies. The heavy dots represent switches. The CPUs and memories are not shown. (a) A star. (b) A complete interconnect. (c) A tree. (d) A ring. (e) A grid. (f) A double torus. (g) A cube. (h) A 4D hypercube.
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MPPs - BlueGene (1)
The BlueGene/L custom processor chip.
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BlueGene (2)
The BlueGene/L. (a) Chip. (b) Card. (c) Board. (d) Cabinet. (e) System.
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Red Storm (1)
Packaging of the Red Storm components.
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Red Storm (2)
The Red Storm system as viewed from above.
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A Comparison of BlueGene/L and Red Storm
A comparison of BlueGene/L and Red Storm.
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Clusters - Google (1)
Processing of a Google query.
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Google (2)
A typical Google cluster.
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Scheduling
Scheduling a cluster. (a) FIFO. (b) Without head-of-line blocking. (c) Tiling. The shaded areas indicate idle CPUs.
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Distributed Shared Memory (1)
A virtual address space consisting of 16 pages spread over four nodes of a multicomputer. (a) The initial situation. ....
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Distributed Shared Memory (2)
A virtual address space consisting of 16 pages spread over four nodes of a multicomputer. ... (b) After CPU 0 references page 10. ...
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Distributed Shared Memory (3)
A virtual address space consisting of 16 pages spread over four nodes of a multicomputer. ... (c) After CPU 1 references page 10, here assumed to be a read-only page.
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Linda
Three Linda tuples.
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Orca
A simplified ORCA stack object, with internal data and two operations.
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Performance H/W Metrics
a)Latency - time it takes for a CPU to send a packet and get a reply. a)Circuit Switching: 1-way latency = Ts + p/b; full-duplex latency = Ts + 2 (p/b) where Ts = Total setup time, p = packet size in bits, b = bandwidth bits/sec c) Packet Switching:
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Performance H/W Metrics
a) Packet Switching: 1-way latency = Ta + p/b (this is up to 1st switch only) 1-way laten. = Ta + n(p/b + Td) + p/b (for n switches, last term is for last switch to destination) Td = processing and time and queuing delay Ta = internal setup time p = packet size in bits b = bandwidth in bits/sec n = number of switches
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Performance H/W Metrics
a) Virtual cut through and wormhole routing: in best cases: 1-way latency = Ta + p/b (no probe packet and no store-and-forward delay either) Ta = internal setup time b) Bandwidth: number of bytes/sec that a system can move. c) Bisection Bandwidth: (reviewed in previous section)
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Performance H/W Metrics
a) Aggregate Bandwidth: Calculated by adding up the capacities of all the links. - provides the maximum number of bits that can be moving at once b) Average Bandwidth: CPU capability, if 1MB/sec, a 1GB/sec I-Net will be of no help...
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Performance S/W Metrics
a) Small packet size means low latency and low bandwidth, whereas Large packet size means high latency and high bandwidth. a) Speedup: how much faster a program runs on an nprocessor system than on a single cpu. - Next Fig. Sublinear speedup for real programs even with n-processors. Speedup = n / [ 1 + (n-1) f ] where n = # cpus, f = fraction of time from T sec runtime required per program. c) Fig. after, Amdahl's Law. ( for f > zero then perfect speedup is not possible due to in-series components).
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Software Metrics (1)
Real programs achieve less than the perfect speedup indicated by the dotted line.
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Software Metrics (2)
(a) A program has a sequential part and a parallelizable part. (b) Effect of running part of the program in parallel.
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Achieving High Performance
(a) A 4-CPU bus-based system. (b) A 16-CPU bus-based system. (c) A 4-CPU grid-based system. (d) A 16-CPU grid-based system.
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Grid Computing
The grid layers.
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Open Grid Services Architecture
Infrastructure communication services. (communication between resources. Resource management services (reserve/deploy assets) Data services (move/copy data where it is needed) Context services (described required resources and usage) Information services (resource availability information) Self-management services (maintain quality of service) Security services Execution management services (manage workflow)
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LA-Grid Computing
The grid layers.
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LA-Grid Computing
Computer Network Security Research Biochemical-Based Defense Research Biometrics Patterns Analysis Research
Collaboration with Universities
Collaboration with Industry
GEM
Medical and Bioinformatics Financial Market Data Analysis
Information Integration and Analysis Research
Text and Linguistic Information Retrieval
Software Security Analysis Research
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