3 Pages

2002p8q5

Course: CL 0405, Fall 2009
School: East Los Angeles College
Rating:
 
 
 
 
 

Word Count: 623

Document Preview

Studies Business 2002 Paper 8 Question 5 (a) Distinguish between top-down, bottom-up and spiral (rapid prototype) development methodologies. Illustrate your answer with reference to an example of designing a building. Top down methodologies start with a high-level view of the problem, and, at each iteration break it down into smaller steps, until the individual module is capable of implementation. For example a...

Register Now

Unformatted Document Excerpt

Coursehero >> California >> East Los Angeles College >> CL 0405

Course Hero has millions of student submitted documents similar to the one
below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.

Course Hero has millions of student submitted documents similar to the one below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.
Studies Business 2002 Paper 8 Question 5 (a) Distinguish between top-down, bottom-up and spiral (rapid prototype) development methodologies. Illustrate your answer with reference to an example of designing a building. Top down methodologies start with a high-level view of the problem, and, at each iteration break it down into smaller steps, until the individual module is capable of implementation. For example a software task might, at the top level, be decomposed into - Initialise - Do work - Clean up And then Initialise be further decomposed into Initialise static variables Initialise dynamic variables Parnas claimed that each level of decomposition should embody a single design decision for each module. Bottom up, by contrast, starts at the lowest level of decomposition and designs successively larger aggregations, with each layer implemented using the "metamachine" of the layer beneath. This design style is used, for example, for objectoriented programming To use a building analogy, top-down starts with the grand vision of the building and adds detail, whilst bottom-up starts with basic modules, such as doors and windows, then builds room-modules, eventually combining them make the building design. One problem with both top-down and bottom-up approaches is that they are juggernauts: a mistaken decision earlier in the process is hard to correct later. Another problem is that the level of detail makes it difficult to comprehend the design at intermediate stages. To overcome these difficulties spiral development or rapid prototype methodology was developed by Bohm and others. Here a small subset of the project is first developed, and then incremental additions are made to this stable core. For example the major screens of the user interface could be mocked up, and then progressively implemented. The advantage of this method is that here is always a stable fall-back position, and good visibility, assuring better real-world fit.. In terms of a building, the analogy might be, as most buildings of any age are, collection a of extensions and alterations to the original smaller core. (b) You are in charge of commissioning the design of a new building, such as the new Computer Laboratory building. Draw up a high-level GANTT chart for this task up to the letting of the building contract. [10 marks] (N.B. Marking guidelines: Candidates are not expected to know the details of how to design a building, but should demonstrate that they know what a GANTT chart is, and using common sense produce a reasonable and logical sequence, including periods for user consultation. The exact details and time estimates in the chart aren't important. Marking the critical path would be a bonus..) 4th Quarter 1st Quarter 2nd Quarter 3rd Quarter 4th Quarter 1st Quarter 2nd Quarter 3rd Quarter 4th Quarter 1st Quarter ID Task Name Duration Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan 1 Prepare Brief 160 days 2 3 4 5 6 7 8 9 Gather Requirements Consult users Consult others Gather constraints Budget Prepare brief Check Brief with users 60 days 3 mons 3 mons 60 days 1 mon 2 mons 1 mon 1 mon 1 mon 200 days 3 mons 1 mon 3 mons 6 mons 220 days 4 mons 4 mons 4 mons 3 mons 1 mon 1 mon 1 mon 2 ...

Find millions of documents on Course Hero - Study Guides, Lecture Notes, Reference Materials, Practice Exams and more. Course Hero has millions of course specific materials providing students with the best way to expand their education.

Below is a small sample set of documents:

East Los Angeles College - CL - 0405
Business Studies 2004 Paper 7 Question 13 A software project has two phases, each with three tasks. They are expected to take the following amount of effort: Phase 1: Analysis: 3 weeks Code: 2 weeks Test: 1 week Phase 2: Analysis: 1 week Code: 2 week
East Los Angeles College - CL - 0405
2.q Money and Tools for it's managementProfit and Loss Cash flow Balance Sheet BudgetsIntroduction to accountingq qSources of finance Stocks, Shares, Futures and OptionsIntroduction to accounting qWhy have accounts? Instruments
East Los Angeles College - CL - 0405
4.People"There go my people. I must follow them, for I am their leader." (M. Gandhi, quoting Alexandre Ledru-Rollin, (1848) "Eh! Je suis leur chef, il fallait bien les suivre")q q q q q qMotivating factors Groups and Teams Ego Hiring and firi
East Los Angeles College - CL - 0405
5.q q q qProject planning and managementRole of a manager Charts and Critical Path Analysis Estimation Techniques MonitoringRole of a managerq qDirects resources for the achievement of goals LEADER also provides Vision Inspiration Ri
East Los Angeles College - CL - 0405
6.q q q q qQuality, maintenance and documentation Development cycle Productisation Plan for quality Plan for maintenance; Plan for documentation: Development cycle: EffortTimeSpecificationAnalysisBuild TestAlpha Beta Maintain
East Los Angeles College - CL - 0405
7.q q q q qMarketing and Selling: Sales and marketing are different Basic economics Marketing; Channels ; Market Communications Stages in Selling Control and CommissionsSales and marketing are differentq q qMarketing: What and how to sell
East Los Angeles College - CL - 0405
8.q q q q q qGrowth and Exit routesNew markets: horizontal and vertical expansion Problems of growth; second system effects Communication Exit routes: acquisition, floatation, MBO or liquidation. Places to look for new enterprises Conclusion:
N.C. State - CS - 746
Marker-Assisted Selection for Quantitative Traits Readings: Bernardo, R. 2001. What if we knew all the genes for a quantitative trait in hybrid crops? Crop Sci. 41:1-4. Eathington, S.R., J.W. Dudley, and G.K. Rufener II. 1997. Usefulness of marker-QT
Western Washington - GEOL - 406
Naming/Describing Igneous Rocks(Much of this document comes from one by Sue DeBari) In this context, "naming" means assigning a full name to a rock, based generally on the classi cation (root name) and other observations in the rock. is should give
Western Washington - GEOL - 406
Name_Review Questions for Chapters 13-14 (MORB & OIB)1. What is wrong with this early model of the mid-ocean ridge?2. Given Figure 13.5, how deep would we expect peridotite to be found beneath the ridge? In what kind of mid-ocean ridge do we fin
Washington - CHEM - 239
Exam3 (histogram)40Minimum 25% Percentile Median 75% Percentile Maximum Mean Std. Deviation Std. Error Lower 95% CI of mean Upper 95% CI of mean6.0 46.5 60.0 72.75 98.0 58.4036 18.0605 1.0774 56.2827 60.524430# in that bin20100Bin Ce
University of California, Merced - CSE - 140
Chapter 5Large and Fast: Exploiting Memory Hierarchy5.1 IntroductionMemory TechnologyStatic RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Implemented with inverting gates or CMOS technology 50ns 70ns, $20 $75 per GB Implemented with capac
University of California, Merced - CSE - 140
Chapter 6Storage and Other I/O Topics6.1 IntroductionIntroductionI/O devices can be characterized by Behaviour: input, output, storage Partner: human or machine Data rate: bytes/sec, transfers/sec Example: keyboard, sound output, network
University of California, Merced - CSE - 140
Chapter 7Multicores, Multiprocessors, and Clusters9.1 IntroductionIntroductionGoal: connecting multiple computers to get higher performance Multiprocessors Scalability, availability, power efficiency High throughput for independent jobsSi
Washington - MATH - 407
MATH 407 QUIZ January 11, 2007NAME (Please print):There are 2 problems. Stop now and make sure you have both problems. If you do not have them both, then request a new quiz. The first problem is worth 30 points and the second is worth 45 points f
Wisc La Crosse - SOC - 225
RELIGIOUS MINORITY Definition: An ethnic group whose religious obligations result in patterns of behavior among its members that result in discriminatory treatment by the mainstream society.Four Patterns-1) Full Social Assimilation of the religious
Washington - LING - 200
Core linguistics Phonology MorphoSyntax Neurolx evidence PSE vs. ASLThe need for empiricism Spatial morphology Nonmanual featuresASL linguistics quick bitSarah Churng for lx200 instructional purposes Please feel free to add/comment, and rememb
Michigan - SMC - 435
In this class we discussed how the readings (sets 1-3), text and lectures ( first 2 chapters and lectures) informed you about the women's sport product. One important concept is that knowledge consists of four components. These four components are il
Michigan - SMC - 435
LAB ASSIGNMENT #1: Identifying key attributes considered by consumers using three different approaches For each research approach interview two people A. Direct solicitation Please tell me what factors you usually consider when deciding to attend a
Brookdale - CS - 3136
Summer 2009 Faculty of Computer ScienceCSCI 3136 - Principles of Programming LanguagesAssignment 3Due: Monday, May 25, 2008 9pm Worth: 6% of the final grade Instructor: A.Sedgwick Assignment Instructions: Please note that assignments are marked f
Brookdale - CS - 3136
ParsingCSCI 3136: Principles of Programming Languages1Class Notes 7Derivations and Parse Trees Nested constructs require recursion A given language may be defined by several e.g. arithmetic expressions<expression> <identifier> | <number
Brookdale - CS - 3136
Faculty of Computer ScienceCSCI 3136 Principles of Programming LanguagesSummer 2009Instructor: Vlado Keelj s Notes contributors: Vlado Keelj, Evangelos Milios, and Phil Cox s(empty page)i Note: These course notes are not meant to be a substi
Washington - SIG - 20040210
France Cordova ' Mary ClutterMichael GazzanigaThomas Insel Story LandisAlan LeshnerJohn MazziottaKathie Olsen Aristides PatrinosCelebrating the Human Brain Project, Neuroinformatics Initiatives' Tenth Anniversary with a special program of
Texas A&M - BIOL - 213
Chapter 9 How Genes and Genomes EvolveEukaryotic gene structure Evolutionary trees Structure, simple interpretation Sequence changes Selection Drift Gene structure sequence change and conservation Coding v. non-coding Ex
USC - EE - 577
96/01/25 15:39:30D-Memory Module Dmem.v1/ / / Dmem: A Data Memory module example / Parameter List: / clk: the memory clock (input) / address: the instruction address (input) / accType: the type of memory transaction (input) / data: the data (in
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: Dmem.v %CreationDate: Thu Jan 25 15:47:54 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for tex
USC - EE - 577
96/01/25 02:06:13/ / / / / / / / /D-Memory Test Module DmemTest.vDmemTest: Test module for Dmem Author: Nestoras Tzartzanis Date: 1/25/96 EE577b: Verilog Example1module DmemTest; reg reg wire Dmem [7:0] [7:0] clk, accType; address, dataTmp; d
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: DmemTest.v %CreationDate: Thu Jan 25 15:53:00 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for
USC - EE - 577
96/01/25 15:02:20 / / / / / / / / / / / / /I-Memory Module Imem.vImem: The Instruction Parameter List: clk: address: instruction: Memory module the memory clock (input) the instruction address (input) the instruction (output)1Author: Nestoras
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: Imem.v %CreationDate: Thu Jan 25 15:27:39 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for tex
USC - EE - 577
96/01/24 23:21:17 / / / / / / / / / / / / / / / /ALU Module alu.valu: The ALU module. It executes the instructions. Parameter List: clk: the clock (input) opA: instruction operand (input) opB: instruction operand (input) aluOp: the ALU control sig
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: alu.v %CreationDate: Thu Jan 25 15:28:11 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for text
USC - EE - 577
96/01/24 22:01:56 / / / / / / / / `define `define `defineControl Signal Definition control.hDefinition of the control signal values Author: Nestoras Tzartzanis Date: 1/25/96 EE577b Verilog Example ALU control signals aluMv 2'b00 aluAdd 2'b10 aluXo
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: control.h %CreationDate: Thu Jan 25 15:28:38 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for
USC - EE - 577
96/01/24 22:50:17 / / / / / / / / / / / / / / / /Counter Module counter.vcounter: The counter module. The counter plays the role of PC since the instruction set doesn't include any control transfer instructions. Parameter List: clk: the clock (inp
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: counter.v %CreationDate: Thu Jan 25 15:29:05 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for
USC - EE - 577
96/01/25 00:15:37/ / / / / / / / / t) / / / / / /CPU Module cpu.v/ The Register File rf rfTran wrA, rd0, rd1, wr); the microprocessor component the the the the1(clk, instr[2:0], instr[5:3],cpu:/ The multiplexor clock (input) mux multiplexo
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: cpu.v %CreationDate: Thu Jan 25 16:04:30 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for text
USC - EE - 577
96/01/25 00:13:34Decoder Module decoder.v1/ / / decoder: The Instruction Decoder module. / It decodes the instructions and / generates the control signals that / are going to be used throughout the pi peline. / Parameter List: / clk: the clock
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: decoder.v %CreationDate: Thu Jan 25 16:05:45 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: mux.v %CreationDate: Thu Jan 25 15:30:16 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for text
USC - EE - 577
96/01/24 16:31:37 / / / / / / /Opcode Definition opcodes.h1Definition of the op-codes, as they are in the instuction format. Author: Nestoras Tzartzanis Date: 1/25/96 EE577b Verilog Example 2'b0? 2'b10 2'b11`define MV `define ADD `define XOR
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: opcodes.h %CreationDate: Thu Jan 25 15:30:42 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for
USC - EE - 577
96/01/24 23:04:15 / / / / / / / / / / / / /Register Module register.vregister: A variable-size register Parameter List: clk: the clock input d: the input data q: the output of the register Author: Nestoras Tzartzanis Date: 1/25/96 EE577b Verilog E
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: register.v %CreationDate: Thu Jan 25 15:31:16 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for
USC - EE - 577
96/01/25 15:30:29 / / / / / / / / / / / / / / rf:Register File Module rf.vThe Register File module It includes the Register File transactions. Parameter List: clk: the clock (input) rd0A: the address for the read port 0 (input) rd1A: the address f
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: rf.v %CreationDate: Thu Jan 25 15:38:44 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for text
USC - EE - 577
96/01/25 15:12:20 / / / / / / / / /Top-Level Module topLevel.vtopLevel: It includes the cpu and the Imem Author: Nestoras Tzartzanis Date: 1/25/96 EE577b: Verilog Example1module topLevel; reg wire Imem cpu [7:0] clk, reset; instruction, PC;I
USC - EE - 577
%!PS-Adobe-1.0 %Creator: watt.isi.edu:nestoras (Nestoras Tzartzanis,949M; DIV8) %Title: topLevel.v %CreationDate: Thu Jan 25 15:33:59 1996 %DocumentFonts: Courier-Bold Courier Times-Roman Times-Bold Helvetica-Bold % Start of enscript.pro - prolog for
USC - EE - 577
%!PS-Adobe-3.0 %BoundingBox: (atend) %Pages: (atend) %PageOrder: (atend) %DocumentFonts: (atend) %Creator: Frame 5.0 %DocumentData: Clean7Bit %EndComments %BeginProlog % % Frame ps_prolog 5.0, for use with Frame 5.0 products % This ps_prolog file is
USC - EE - 577
%!PS-Adobe-3.0 %BoundingBox: (atend) %Pages: (atend) %PageOrder: (atend) %DocumentFonts: (atend) %Creator: Frame 4.0 %DocumentData: Clean7Bit %EndComments %BeginProlog % % Frame ps_prolog 4.0, for use with Frame 4.0 products % This ps_prolog file is
Arizona - ECE - 473
ECE-473/573 - Software Engineering Concepts (Spring 2002)Homework # 1 Due Date: 01 /29/02 (at the start of the lecture)Cash-Cards are like currency notes in value and can be used for the payment of purchases. The bank can issue one or more single C
Arizona - ECE - 473
ECE 473/573 Software Engineering Concepts Spring 20022001-02 Catalog Data: Software Engineering Concepts (3) II In-depth consideration of each of the phases of the software project life code. Object-oriented design and programming. Includes a large-
Arizona - ECE - 473
ECE 473/573 Software Engineering Concepts Spring 20022001-02 Catalog Data: Software Engineering Concepts (3) II In-depth consideration of each of the phases of the software project life code. Object-oriented design and programming. Includes a large-
Arizona - ECE - 473
ECE 473/573 Software Engineering Concepts Spring 20022001-02 Catalog Data: Software Engineering Concepts (3) II In-depth consideration of each of the phases of the software project life code. Object-oriented design and programming. Includes a large-
Arizona - ECE - 473
Procedure for OO AnalysisWrite system/software requirements descriptionIdentify candidate objects of the problem domain(nouns in requirements description)Categorize objectsDown select objects into classesCreate CRC model Iterate until all r
Arizona - ECE - 473
10 Ordered Containers and Their ImplementationWe continue with the second branch of the containers specification hierarchy, that of ordered containers (Figure 1). Consideration starts with class order, which is general enough to serve as a base cla
Arizona - ECE - 473
11 Testing Based on Behavior SpecificationWhile "getting it right the first time" is an admirable goal, no one is able to write code that is guaranteed to work as intended without testing and debugging. Testing is the process of uncovering errors o
Arizona - ECE - 473
ECE 473/573Software Engineering ConceptsCourse NotesBernard P. Zeigler ACIMS, ECE Dept. UA The Author 2002Software Engineering Concepts1Software Engineering: Disciplined Software DevelopmentWhy is software engineering different from progr
Arizona - ECE - 473
2 Coordination in Team-based Software Development: Role of the "Blueprint"Team Work: The Need for CoordinationWhy is organization is needed and how does it relate to the progress that a group of individuals can make in developing software ? If wri
Arizona - ECE - 473
17 Integrating Hierarchical Modular Coupled System LevelIn the last chapter we saw how systems concepts could augment the UML design process by providing a more encompassing perspective in which design of engineering systems takes place. The leve