646: ENEE Digital Computer Design
Fall 2004 Handout #20
Problem Set # 3
Due: November 23
Complex Pipelining and Caching
Problem 1
H&P 3.10
Problem 2
In this problem, we will look at how a common vector loop runs on two processors, one that implements scoreboarding and another that implements Tomasulo's algorithm. The loop is the so-called SAXPY loop and is the central operation in Gaussian elimination. The loop implements the vector operation Y = a * X + Y for a vector of length 100. The code is shown in H&P Problem 3.6. You will be asked to specify the state of the processor after some number of instructions from the SAXPY loop have executed. When doing this, use the structure on page 1 of handout #12 for scoreboarding, and the structure on page 2 of handout #12 for Tomasulo's algorithm. Before drawing the processor state, you must first draw the pipeline diagram. In order to do this, you will need some rules about how to draw the pipeline diagrams. These rules are given at the end of this problem. a. Using the SAXPY code, show the state of the scoreboard when the DSGTUI instruction reaches write result. Assume that there is one integer functional unit. Assume the FP unit configuration of H&P Figure A.51 with the FP latencies of H&P Figure 4.1 (see below for modifications to these latencies). The branch should not be included in the scoreboard. b. Use the SAXPY code and a fully pipelined FPU with the latencies of H&P Figure 4.1 (see below for modifications to these latencies). Assume Tomasulo's algorithm for the hardware with one integer unit. Show the state of the reservation stations and register file ready bits when the DSGTUI writes its result on the CDB. Do not include the branch. c. Using the SAXPY code, assume a scoreboard with the FP functional units described in H&P Figure A.51, plus one integer functional unit (also used for load-store). Assume the latencies shown in H&P Figure 3.63 (see below for modifications to these latencies). Show the state of the scoreboard when the branch issues for the second time. Assume the branch was correctly predicted 1
taken and took 1 cycle. How many clock cycles does each loop iteration take? You may ignore any register port/bus conflicts. d. Use the SAXPY code. Assume Tomasulo's algorithm for the hardware using one fully pipelined FP unit and one integer unit. Assume the latencies shown in H&P Figure 3.63 (see below for modifications to these latencies). Show the state of the reservation stations and register file ready bits when the branch is executed for the second time. Assume the branch was correctly predicted as taken and took 1 cycle. How many clock does cycles each loop iteration take? As mentioned earlier, you must draw the pipeline diagrams before specifying the state of the processor. Here are some rules that will help you draw the pipeline diagrams. For all the rules, assume all units are fully pipelined. Also, assume there is no forwarding in scoreboarding, but there is forwarding in Tomasulo. 1. For scoreboarding, issue and register read happen on two separate cycles. For instance, the DADDUI instruction would look like the following: F D I R E W And the store double instruction would look like: F D I R M W Also, in scoreboarding, WAR hazards are detected and stalled during the writeback stage, as discussed in class. 2. For Tomasulo, register read happens in the same cycle as issue. For instance, the DADDUI instruction would look like the following: F D I E W And the store double instruction would look like: F D I M W 3. H&P Figure 4.1 gives the *latencies* of various instructions. The latency is the number of intervening cycles required between two dependent instructions: MUL.D f4, f2, f0 ADD.D f6, f4, f6 means that you need the following pipeline diagram for scoreboarding: 2
MUL.D ADD.D
F D I R E E E W F D I - - - R E E E W
because there is no forwarding in scoreboarding. For Tomasulo, you would have: MUL.D ADD.D F D I E E E E W F D I - - - E E E E W
4. In H&P Figure 4.1, the book claims FPop Store has latency 2 cycles. Change this to latency 3 cycles. This is an inconsistency that cannot be rectified if you assume that FPop FPop is 3 cycles: MUL.D S.D F D I R E E E W F D I - - - R M W
5. For scoreboar...