6 I/O 16550 Programmable Communications Interface
PHY 4635/5635 Spring 2009
16550 Programmable Communications Interface
Connects to virtually any type of serial interface A UART (Universal asynchronous receiver/transmitter) Operates at 0-1.5M baud rate (baud = bits/sec) Asynchronous serial data transmitted/received without the use of a clock or timing signal Frame = 1 start bit, 7 data bits, 1 parity bit,1 stop bit. Most dialups use this method some protocols use 8 data bits with no parity bit.
16550 Design
Transmitter & receiver are completely separateit can operate in
Simplex mode: RCVR or XMTR is used by itself (e.g. FM radio station is a simplex system) Half-duplex mode: RCVR & XMTR take turns (e.g. keyed HAM radios) Full duplex mode: RCVR & XMTR can operate simultaneously (e.g. voice telephone)
RCVR & XMTR have 16byte FIFO caches each.
Used to control MODEM, for example
Some terminology
16550 (UART) = Data terminal
A.k.a. DTE (Data Terminal Equipment) Governs TTL-level interface from CPU to DCE Hubs & routers are also DTEs
Modem = Data set
A.k.a. DCE (Data Communications Equipment) Interfaces terminal (DTE) to communications medium (twisted pair, coax, etc) Governed by: DTE/DCE devices are EIA (Electronic Industries Association) RS-232-C and RS-232-D and EIA RS-366-A, as well as the CCITT X.20, X.21, and V.35 standards.
A0,A1,A2: Selects internal register for programming ADS: Latches address and chip select lines (Intel systems, connect to GND). BAUDOUT: CLK signal generated by internal baud rate generator is made available here (Tied to RCLK so that XMTR & RCVR clocks are the same). CSO,CS1,CS2: All must be active to select UART CTS: Clear to send. Active indicates modem (data set) is ready to exchange info. Used mostly in duplex. D7-D0: CPU data bus connections DCD: Data carrier detect. Used by modem to tell UART that a carrier is present. DDIS: Disable driver. Logic 0 says that the CPU is reading data from the UART (Can be used to change direction of data flow through buffer). DSR: Data set ready. Input to UART says that the modem (data set) is ready to operate DTR: Data terminal (UART;16550) ready to function. Output from UART saying it is ready to function. INTR: Interrupt request is output to CPU when (1) an error occurred, (2) UART has received data, UART XMTR is empty.
MR: Master reset. Tied to system RESET. OUT1, OUT2: User-defined output pins (to be used by modem or other device). RCLK: Receiver clock. Input to the receiver section. Always 16X BAUD desired RD,RD: Causes data to be read from UART register defined on address pins RI: Ring indicator. Becomes logic 0 by the modem to indicate that the telephone is ringing. RTS: Request to send. Output to modem, indicating UART (16550) is ready to send data. SIN,SOUT: Serial data pins. SIN accepts serial data, SOUT transmits serial data. RXRDY. Receiver ready. Used to transfer data via DMA. TXRDY. Transmitter ready. Used to transfer data via DMA. WR,WR. Write strobe from CPU to UART. XIN, XOUT. Main clock connections. XTAL is connected across these pins or an external (PCLK) clock is tied to XIN.
Programming the 16550
After RESET, the system must define the:
Line Control Register : defines
# of data bits # of stop bits Parity (even or odd, sent as a 0 or 1)
Baud Rate Generator
A divisor that determines the Baud rate of the transmitter section
FIFO Control Register
Enables receiver & transmitter and clears FIFO buffers
Line control register
Write to x...x011 No parity is common for internet connections A break is 2 consecutive frames of 0s (SW controlled)
Baud rate generator
Write to
x..x000 (MS byte) x..x001 (LS byte)
Value written depends on external system clock
Table at right is for a 18.432 MHz XTAL 4800 = 18.432M/(16 x 240)
What value must be written to get 115,200 Baud on a 1.6 GHz crystal?
ANS: 868 (verify this)
FIFO Control Register
To enable, set
bit 0 = 1
To clear, set
bit 1, bit 2 = 1
Example
Initialize a system that requires:
7 data bits Odd parity Baud=96...