- 6.012 Electronic Devices and Circuits
Lecture 21 - Linear Amp. Analysis and Design II - Outline
Announcements
Handouts - Lecture Outline and Summary
Design Problem - Answer sheet and final specs out Wed.
Review - Non-linear and active loads
Non-linear loads: large reff @ large I, small V (Use biased BJT or MOSFET) Active loads: current mirror, Lee load (Reduced common-mode gain) Expressing gain in terms of device parameters and constraints
General Multi-stage Amplifiers - using design problem as example
Gain and bias analysis
Input and output voltage swings
Output stages: output resistance, loading on gain stage
Specialty stages
Emitter-/source-coupled pairs (diff amps)
Push-pull or Totem pole output
Cascode
Darlington
Clif Fonstad, 11/03 Lecture 21 - Slide 1
Current Source Loads: a higher maximum gain
- current source loads eliminate the compromise between voltage gain and output voltage swing V+
ILOAD CO + vout IBIAS CE
Maximum Voltage gain
+ vin -
V-
Clif Fonstad, 11/03
VA ,eff gm qIC kT Bipolar : A
= = v,max = goL + goQ IC VAL + IC VAQ Vthermal 2VA,eff 2 ID [VGS VT ] gm MOSFET* : Av,max = =
goL + goQ ID VAL + ID VAQ [VGS VT ] min VALVAQ with VA,eff Typically VA,eff >> [I RL]max VAL + VAQ ] [
Lecture 21 - Slide 2
Achieving the maximum gain: Comparing linear
resistors, current sources, and active loads MAXIMUM GAIN
Linear loads Linear resistor resistor
Current Current source source loads
Difference mode Active load, Av,diff
Bipolar [ IC RL ] max
Vthermal 2VA ,eff Vthermal VA ,eff
Bipolar
[VGS
MOSFET [ ID RL ] max
MOSFET
VT ] min
2VA ,eff [VGS VT ] min VA ,eff
Active loads
Common mode v,com Active load, A
Vthermal V thermal VA,bias
[VGS [VGS
VT ] min
VT ] min
VA ,bias
Observations: - Non-linear (current source) loads typically yield higher gain than linear resistors, i.e. VA,eff >> [IDRL]max - Bias level is not important to BJT stage gain - A MOSFET should be biased at low level for high gain - For active loads what increases Avd, decreases Avc
Clif Fonstad, 11/03 Lecture 21 - Slide 3
6.012 - Electronic Devices and Circuits
Fall 2003 Design Problem Circuit
Full schematic
+ 1.5 V Q1 A Q2 Q3 Q4 Q5 Q8 Q10 Q11 Q9 R1 Q6 Q7 + vIN2 Q19 B Q20 B R2 Q12 Q13 R3 Q14 Q22 B Q15 Q17 Q21 B Q24 Q16 + vOUT A Q23
+ vIN1 B
B
Q18
Bias chain Common-source gain stage with Lee load Source- - 1.5 V Common-source follower stage with gain stage with degeneration current mirror load to provide level shift Emitterfollower output stage Push-pull output stage
Clif Fonstad, 11/03
Lecture 21 - Slide 4
6.012 - Electronic Devices and Circuits
Fall 2003 Design Problem Circuit
Conceptual schematic: full circuit
+ 1.5 V Q2 Q3 Q4 Q5 Q8 Q10 Current mirror load IBIAS5 Q11 Q9 R3 Q12 Q13 Q14 Q15 Q17 IBIAS3 IBIAS4 IBIAS6
Emitterfollower output stage Push-pull output stage
Lee load
+ vIN1 -
Q6
Q7 + vIN2 -
R2
Q16 + vOUT -
IBIAS1
Common-source gain stage with Lee load
IBIAS2
Source- - 1.5 V follower Common-source stage with gain stage with degeneration current mirror to provide load level shift
Clif Fonstad, 11/03
Lecture 21 - Slide 5
Fall 2003 Design Problem Analysis
Breaking out the individual stages
+ 1.5 V Q2 Q3 Q4 Q5 Q8 + vIN R2 + + vOUT vIN1 B Q20 B Q12 Q13 + vIN2 Q10 Q11 A + 1.5 V + 1.5 V Q23 + 1.5V
+ vOUT1 -
+ vIN1 -
Q6
Q7 + vIN2 -
+ vOUT2 -
+ vOUT + vIN Q14 B
Q16 Q15 + vOUT Q17 -
RL
B
Q19
Q21
Q24
- 1.5 V
- 1.5 V
- 1.5 V
- 1.5V
Common-source gain stage with Lee load
Sourcefollower stage with degeneration to provide level shift
Common-source gain stage with current mirror load
Emitterfollower output stage
Push-pull output stage
We'll next look at the issues associated with each stage.
Clif Fonstad, 11/03 Lecture 21 - Slide 6
Fall 2003 Design Problem Analysis
+ 1.5 V Q2 Q3 Q4 Q5
The first stage:
uses the Lee Load to get
large common-mode
rejection in a fully-
differential stage
We find:
+ vOUT1 -
+ vIN1 -
Q6
Q7 + vIN2 -
+ vOUT2 -
v out1 = v out 2 =
go19 [v in1 + v in 2 ] gm 6 [v in1 v in 2 ] + 2 4 gm 2 2 go6 + 2go2
B
Q19
go19 [v in1 + v in 2 ] 4gm 2 2
gm 6 [v in1 v in 2 ] go6 + 2go2 2
- 1.5 V
[VSG 2 VT ] ID19 VA19 go19 = = And also see: 4gm 2 4 2ID 2 [VSG 2 VT ] 2VA19 2ID 6 [VGS 6 VT ] 2VA 6 1 gm 6 = = go6 + 2go2 ID 6 VA 6 + 2ID 2 VA 2 [VGS 6 VT ] 1+ VA 6 VA 2
Clif Fonstad, 11/03
There is only so much you can do (but you can do a few things)!
Lecture 21 - Slide 7
Fall 2003 Design Problem Analysis
+ 1.5 V Q8
+ vIN R2 + vOUT B Q20
The second stage:
a source-follower with
degeneration to shift the level of the input to the third stage. We find the voltage gain of this stage is: ro20 v out [ro20 + R2 ] Hopefully this can be made close to one. The DC level shift is:
- 1.5 V
VOUT = VIN
[VGS 8
VT ]
R2 ID 20
Your job is to figure out why you want to shift the level, and by how much.
Clif Fonstad, 11/03 Lecture 21 - Slide 8
Fall 2003 Design Problem Analysis
+ 1.5 V
The third stage:
uses the Current Mirror Load to convert efficiently from a double-ended to single-ended output and to get more differential gain and common-mode rejection. find:
Q10
Q11
+ We vIN1 B
Q12
Q13
+ vOUT + vIN2 -
v out =
go21 [v in1 + v in 2 ] 2 gm13 [v in1 v in 2 ] + 2 gm10 2 go13 + go11 + GL 3 2
Q21
[VSG10 VT ] go21 ID 21 VA 21 = = 2gm10 2 2ID10 [VSG10 VT ] 2VA 21 2 2ID13 [VGS13 VT ] 4VA13 1 2gm13 = =
go13 + go11 + GL 3 ID13
VA13 + ID11 VA11 + GL 3 [VGS13 VT ] 1+ VA13 VA11 + VA13GL 3 ID11
and:
To maximize this gain we make VA11 larger and the bias current
ID13 large to reduce the impact of GL3.
Clif Fonstad, 11/03 What is GL3? Look at Stages 4 and 5. Lecture 21 - Slide 9
- 1.5 V
Fall 2003 Design Problem Analysis
The fourth and fifth stages:
Two parallel paths, one active when
the output goes positive, the other
when it goes negative. Each path
consists of two emitter follower
stages.
You will find that these two stages
+ impact many aspects of your
design, including: vIN 1. The DC level at the output 2. The output voltage swing 3. The output resistance 4. The load seen by stage 3 5. The power dissipation
A Q23
+ 1.5V
Q16 Q14 B Q15 +
vOUT Q17 -
RL
Q24
- 1.5V
To begin, Q16 and Q17 have to be large enough to supply the current needed to RL at a modest vBE, and the current sources Q23 and Q24 need to be large enough to supply the base currents Q16 and Q17 demand when at peak swing.
Clif Fonstad, 11/03 Lecture 21 - Slide 10
+V
Fall 2003 Design Problem Analysis
Output resistance:
we begin with a single emitter
follower
We have
vt + -
rt Q1 rout IBIAS1 -V
+V
rout
[r 1 + rt ] [ r 1 + rt
] [ 1 + 1]
1
Next look at the pair of emitter followers recognizing that the rout of one is the rt of the other: now:
r 1+ rout
[ r 2 + rt ] [ 2 + 1] [ 1 + 1]
IBIAS2
r1
1
+
r
2
+
rt
1 2
Q1 rt vt + Q2 IBIAS1 -V rout
1 2
In the design problem we have two
paths in parallel and thus have:
r r r 16 r 17 rout + 14 + 15 +
16 16 14 17 17 15
rt
16 14
with
rt
1 go11 + go13
Lecture 21 - Slide 11
Clif Fonstad, 11/03
Remember: r =
gm = kT qIC
This is an important design tool.
Fall 2003 Design Problem Analysis
+V
Load resistance on Stage 3:
again begin with a single emitter follower We have
Q1 rin RL
rin
r 1+[
1
+ 1] RL
r 1+
1
RL
IBIAS1 -V
+V IBIAS2 Q1 Q2 IBIAS1 -V RL
Next look at the pair of emitter followers recognizing that the rin of one is the RL
of the other:
now: rin
r 2 + [ 2 + 1]{r 1 + [ 1 + 1] RL } r 2 + [ 2 + 1] r 1 + [ 2 + 1][ 1
+ 1] RL r 2 + 2 r 1 +
1 2 RL
rin
In the design problem we again have
two paths in parallel and thus have:
RL 3
{r 14 + [
14
+ 1] r 16}
{r 15 + [
15
+ 1] r 17} +
[
16
+ 1][
14
+ 1] RL
Lecture 21 - Slide 12
Notice that some of what makes RL3 big, makes Clif Fonstad, 11/03 rout big also, so compromise may be needed.
Fall 2003 Design Problem Analysis
DC off-set at the output:
DC off-set: The transfer characteristic, vOUT vs vIN1 - vIN2, will not in general go through the origin, i.e., vOUT = Avd(vIN1 - vIN2) + VOFFSET In the example in the figure Avd is -2 x 106, and VOFFSET is 0.1 V. R
V OUT 1V -A vd = 2x10 0.5 V
6
V IN2 - V IN1 V OUT
-50nV
0.1V V IN2 - V IN1 N
R V IN1 V IN2 A vd V OUT RL
In use (with shunt feedback, for example) the off-set with zero input is negligible. In this example, with R = R, VOUT(0) is only 0.1 mV.
Lecture 21 - Slide 13
Clif Fonstad, 11/03
Multi-stage amplifier analysis/design - special pair stages
Push-pull output stages:
High input resistance, low output
resistance, large drive capability
+ 3V + 3V
+3V A Q1
+ vIN -
Q1 Q2 +
vOUT -
+ vIN
RL
B D1 D2
Q1 Q2 + vOUT Q3 Q4
Q4 + vIN Q2 B Q3 + vOUT Q5 -
RL
RL
R1 B Q4
Q6
- 3V Emitter-follower output: negative swing imposes constraint on DC power.
Clif Fonstad, 11/03
- 3V Conventional push-pull: limited in voltage swing by the two B-E diode drops.
-3V Variation on push-pull: larger
voltage swing possible; some
power cost.
Lecture 21 - Slide 14
Multi-stage amplifier analysis/design - special pair stages
The Darlington connection:
A bipolar stage used to get a high
input resistance
+3V A Q15 Q18
rin rout
2
r
17
=2
2
/gm17
+ Q16 Q17
+ vOUT -
1/(1.5go17 + go15)
vIN -
vout = -(gm17/2[1.5go17 + go15 + gin18]) vin
where gin18 = 1/[r
18+(
+1)r
19 +(
+1)2RLOAD]
-3V
Clif Fonstad, 11/03 Lecture 21 - Slide 15
6.012 - Electronic Devices and Circuits
Lecture 21 - Linear Amp. Analysis and Design II - Summary
The Design Problem Circuit - continued discussion
Gains: expressing gain in terms of bounds on devices (Identifying the constraints) Output specs: increased bias currents and larger device sizes in output stages Input/output swings: transistors must remain active
General Multi-stage Amplifier Design -
Issues/stage choices: matching DC levels, loading, buffering
Examples: the A 741, design problem circuit
Specialty stages
Emitter-/source-coupled pairs
- our familiar differential amplifier building block
Push-pull
- large output swing with reduced quiescent power
Cascode
- used to get large Rout; also good high freq. Performance - will discuss more in Lecture 23
Darlington
- used to get large Rin bipolar stages
Clif Fonstad, 11/03 Lecture 21 - Slide 16