Major/Minor L10: FSMs, ,
Lab 3, and RAM/ROM Instantiation Instantiation
Courtesy of Rex Min. Used with permission.
L10: 6.111 Spring 2004
Introductory Digital Systems Laboratory
1
Toward FSM Modularity Modularity
Consider the following abstract FSM:
S0 S1
a1
b1
S2
d1 c1
S3
S4
a2
b2
S5
d2 c2
S6
a3
b3
S7
d3 c3
S8
S9
Suppose Can
that each set of states ax...dx is a "sub-FSM" that produces exactly the same outputs.
No! The outputs may be the same, but the next-state transitions are not.
we simplify the FSM by removing equivalent states?
This situation closely resembles a procedure call or function call in software...how can we apply this concept to FSMs?
Introductory Digital Systems Laboratory 2
L10: 6.111 Spring 2004
The Major/Minor FSM Abstraction Abstraction
STARTA BUSYA
Minor FSM A
RESET CLK
Major FSM
RESET CLK
STARTB BUSYB
Minor FSM B
Subtasks are encapsulated in minor FSMs with common reset and clock Simple communication abstraction:
START:
tells the minor FSM to begin operation (the call) BUSY: tells the major FSM whether the minor is done (the return)
The major/minor abstraction is great for...
Modular
designs (always a good thing) Tasks that occur often but in different contexts Tasks that require a variable/unknown period of time Event-driven systems
L10: 6.111 Spring 2004 Introductory Digital Systems Laboratory 3
Inside the Major FSM FSM
BUSY BUSY BUSY BUSY BUSY BUSY
...
S1 1. Wait until the minor FSM is ready
START
S2
S3
S4
2. Trigger the minor FSM
(and make sure it's started)
3. Wait until the minor FSM is done
Major FSM State START BUSY CLK
S1
S2
S2
S3
S3
S3
S4
L10: 6.111 Spring 2004
Introductory Digital Systems Laboratory
4
Inside the Minor FSM FSM
1. Wait for a trigger from the major FSM
START
T1
BUSY
START
BUSY
T2
BUSY
T3
BUSY
T4
3. Signal to the major FSM that work is done
2. Do some useful work
Major FSM State START BUSY CLK Minor FSM State
S1
S2
S2
S3
S3
S3
S4
can we speed this up?
T1
T1
T2
T3
T4
T1
T1
L10: 6.111 Spring 2004
Introductory Digital Systems Laboratory
5
Optimizing the Minor FSM FSM
Good idea: de-assert BUSY one cycle early
START
T1
BUSY
START
BUSY
T2
BUSY
T3
T4
BUSY
Bad idea #1:
T4 may not immediately return to T1
START
Bad idea #2:
BUSY never asserts!
START
T1
BUSY
START
BUSY
T2
BUSY
T3
T4
BUSY
T1
BUSY
START
T2
BUSY
L10: 6.111 Spring 2004
Introductory Digital Systems Laboratory
6
A Four-FSM Example Example
TICK STARTA BUSYA STARTB
Minor FSM A Minor FSM B Minor FSM C
Operating Scenario:
Major FSM
BUSYB STARTC BUSYC
Major FSM is triggered by TICK Minors A and B are started simultaneously Minor C is started once both A and B complete TICKs arriving before the completion of C are ignored
TICK
Assume that BUSYA and BUSYB both rise before either minor FSM completes. Otherwise, we loop forever!
TICK
BUSYA+BUSYB
BUSYA+BUSYB
IDLE
STARTA STARTB
STAB
BUSYABUSYB
WTAB
BUSYABUSYB
BUSYC
WTC
BUSYC
L10: 6.111 Spring 2004
BUSYC
STARTC
STC
BUSYC
Introductory Digital Systems Laboratory 7
Four-FSM Sample Waveform Waveform
TICK STARTA BUSYA
Minor FSM A Minor FSM B Minor FSM C
Major FSM
STARTB BUSYB STARTC BUSYC
state tick STARTA BUSYA STARTB BUSYB STARTC BUSYC
L10: 6.111 Spring 2004
IDLE IDLE STAB STAB WTAB WTAB WTAB STC STC WTC WTC WTC IDLE IDLE STAB
Introductory Digital Systems Laboratory
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Lab3 Block Diagram Diagram
RESET status Synchronizer CONTROL UNIT MAJOR FSM
A/D AD 670
control(CE, CS, R/W) MINOR FSM 1 MINOR FSM 2 ...
Must choose a shared bus for the A/D and DA A/D output in twos complement and ROM in sign/magnitude
Bypass
LE_DAC
L E_ADC RAM Control and A ddress
8
8
Bidirectional I/O 8
D
A/D Reg
LD Q
ALU CONTROL
RO M Control and Address
Use on-chip SRAM and ROM Sample rate is fixed at 20kHz Must use a memory based approach to FIR, not tapped delay line (i.e., registers) Must use Major/Minor FSM structure
9
8 SW
control (CE, CS)
D/A Reg LD
D
Q
LE_DAC
SRAM
Impulse Response ROM
8
D/A AD 558
CLK
8
Switches
2 SW
8
Arithmetic Unit (MAC)
L10: 6.111 Spring 2004
Introductory Digital Systems Flow Laboratory
Control for Lab3 Lab3
Reset
Wait
Initialize
for a fixed time interval.
Wait Sample
Output what was computed on the last sample. the previous A/D sample into memory. Start the next A/D conversion. the FIR filter algorithm which is a convolution. back for more...
Sample
Store
Output Computed Sample to DAC
Store A/D Sample
Do
Initiate A/D
Go
Convolve
Introductory Digital Systems Laboratory 10
L10: 6.111 Spring 2004
Use LPM to Create ROM/RAM ROM/RAM
Click on File MegaWizard Plug-In Manager
This
z z
starts up a series of windows so that you can specify parameters of the LPM module. You can choose
ROM RAM dp - Dual Ported dq - Separate Inputs and Outputs io - TriState Inputs and Outputs (like the 6264)
You
size. You should specify a file to set the values of the ROM.
You can choose registered or unregistered inputs,
outputs, and addresses.
choose the number of address bits and the word
L10: 6.111 Spring 2004
Introductory Digital Systems Laboratory
11
ROM Contents Contents
Prepare a .dat file.
You can type this in, write a computer program, get it from another
application (speech or graphics, etc.)
This has numbers separated by white space.
z
The default base is HEX but you can use binary or decimal if you include the following statement (before the numbers).
# BASE = BINARY;
Insert, # SET_ADDRESS = 0; (specifies that data should start at address 0)
Run dat2ntl on Athena to format your .dat file into Intel HEX
for details, after `setup 6.111' type `man dat2ntl' dat2ntl <filename>.dat <filename>.ntl
rom8x8.dat: # SET_ADDRESS = 0;
7
6
5 4
3
2 1
0
L10: 6.111 Spring 2004
dat2ntl
rom8x8.ntl: :080000000706050403020100DC :00000001FF
tool on athena
3 8
address
ROM
data
Introductory Digital Systems Laboratory
12
rom8x8.v (generated automatically) automatically)
//============================================= // File Name: rom8x8.v // Megafunction Name(s): // lpm_rom //============================================= module rom8x8 ( address, q); input [2:0] address; output [7:0] q; wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
lpm_rom defparam
lpm_rom_component.lpm_width = 8,
lpm_rom_component.lpm_widthad = 3,
lpm_rom_component.lpm_address_control = "UNREGISTERED",
lpm_rom_component.lpm_outdata = "UNREGISTERED",
lpm_rom_component.lpm_file = "rom8x8.ntl";
endmodule lpm_rom_component (
.address (address),
.q (sub_wire0));
Example: 8 deep by 8 bits wide 3 8
Path to location of Rom data
ROM delay
L10: 6.111 Spring 2004 Introductory Digital Systems Laboratory 13
ram4x2.v ram4x2.v
// megafunction wizard: %LPM_RAM_DQ% module ram4x2 ( address, we, data, q); input input input output [1:0] address;
we; [1:0] data;
[1:0] q;
address data we
2 2 RAM 2 q
wire [1:0] sub_wire0;
wire [1:0] q = sub_wire0[1:0];
lpm_ram_dqlpm_ram_dq_component (
.address (address),
.data (data),
.we (we),
.q (sub_wire0));
defparam
lpm_ram_dq_component.lpm_width = 2,
lpm_ram_dq_component.lpm_widthad = 2,
lpm_ram_dq_component.lpm_indata = "UNREGISTERED",
lpm_ram_dq_component.lpm_address_control = "UNREGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
endmodule
L10: 6.111 Spring 2004
Introductory Digital Systems Laboratory
14
Asynchronous RAM Simulation Simulation
module ram4x2 ( address, we, data, q); input input input output endmodule [1:0] address; we; [1:0] data; [1:0] q;
address data we
2 2 RAM 2 q
Latch interface: Data must be setup and held around the falling edge of the clock. Address must be setup before rising edge and held after falling edge
L10: 6.111 Spring 2004 Introductory Digital Systems Laboratory 15
SRAM with Registered Address and and
Data (Synchronous) (Synchronous)
Register interface: Address, data and we should be setup and held on the rising edge of clock If we=1 on the rising edge, a write operation takes place If we=0 on the rising edge, a read operation takes place
L10: 6.111 Spring 2004
Introductory Digital Systems Laboratory
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