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### Components of CPU Performance

Course: EE 4720, Spring 2001
School: LSU
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Word Count: 2036

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of 02-1 Components CPU Performance and Performance Equation 02-1 Why is my computer fast (or slow)? ? Would it help to improve CPU performance equation is one way to start answering these questions. 02-1 EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02. 02-1 02-2 02-2 CPU Performance Decomposed into Three Components: Clock Frequency () Determined by technology and influenced...

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LSU - EE - 4720
NameComputer Architecture EE 4720 Final Examination8 May 2000, 10:0012:00 CDTProblem 1 Problem 2 Problem 3 Problem 4 Problem 5 Alias Good Luck!(20 pts) (10 pts) (10 pts) (21 pts) (39 pts) (100 pts)Exam TotalProblem 1: An extended DLX ISA,
LSU - EE - 4720
10-1Dynamic Scheduling10-1 10-2Dynamic Scheduling10-2This Set Scheduling:Organizing instructions to improve execution efficiency. Scheduling and Dynamic Execution Definitions From various parts of Chapter 4. Static Scheduling:Organizing
LSU - EE - 4720
01-1EE 4720-Computer Architecture01-1URL: http:/www.ece.lsu.edu/ee4720/RSS: http:/www.ece.lsu.edu/ee4720/rss home.xmlOffered by:David M. Koppelman349 EE Building, 578-5482, koppel@ece.lsu.edu, http:/www.ece.lsu.edu/koppelOffice Hours:
LSU - EE - 4720
01-1EE 4720-Computer Architecture01-1Call Number 1825 (Fall 2002)URL: http:/www.ece.lsu.edu/ee4720Offered by:David M. Koppelman349 EE Building578-5482, koppel@ece.lsu.edu, http:/www.ece.lsu.edu/koppel/koppel.htmlTentative office hou
LSU - EE - 4720
fr-1Fall 2003 Final Exam Reviewfr-1When / WhereTuesday, 9 December 2003, 10:00-12:00 CST (Here).ConditionsClosed Book, Closed NotesBring one 215 280 mm note sheet.Cannot use communication devices.FormatTwo or three or maybe four p
LSU - EE - 4720
mr-1Fall 2005 Midterm Exam Reviewmr-1When / WhereMonday, 24 October 2005, 12:40-13:30 CDTCEBA 2142 (Here)ConditionsClosed Book, Closed NotesBring one sheet of notes (both sides), 216 mm 280 mm.No use of communication devices.Forma
LSU - EE - 4720
mr-1Fall 2007 Midterm Exam Reviewmr-1When / WhereWednesday, 7 November 2007, 10:40-11:30 CSTTaylor 3142 (Here)ConditionsClosed Book, Closed NotesBring one sheet of notes (both sides), 216 mm 280 mm.No use of communication devices.
LSU - EE - 4720
mr-1Fall 2008 Midterm Exam Reviewmr-1When / WhereFriday, 31 October 2008, 10:40-11:30 Central Daylight TimeTaylor Hall 3142 (Here)ConditionsClosed Book, Closed NotesBring one sheet of notes (both sides), 216 mm 280 mm.No use of comm
LSU - EE - 4720
NameSolutionComputer Architecture EE 4720 Final Examination13 December 2005, 12:3014:30 CSTProblem 1 Problem 2 Problem 3 Problem 4 Problem 5 Alias Out-of-order graduation? Good Luck!(15 pts) (20 pts) (17 pts) (15 pts) (33 pts) (100 pts)Exa
LSU - EE - 4720
NameComputer Architecture EE 4720 Final Examination14 May 2003, 15:0017:00 CDTProblem 1 Problem 2 Problem 3 Problem 4 Problem 5 Alias Good Luck!(20 pts) (15 pts) (15 pts) (20 pts) (30 pts) (100 pts)Exam TotalProblem 1: The execution of a M
LSU - EE - 4720
NameSolutionComputer Architecture EE 4720 Final Examination8 May 2000, 10:0012:00 CDTProblem 1 Problem 2 Problem 3 Problem 4 Problem 5 Alias MPL phone home! Good Luck!(20 pts) (10 pts) (10 pts) (21 pts) (39 pts) (100 pts)Exam TotalProble
LSU - EE - 4720
NameComputer Architecture EE 4720 Final Examination10 May 1997, 12:3014:30 CDTProblem 1 Problem 2 Problem 3 Problem 4 Alias Good Luck!(25 pts) (25 pts) (25 pts) (25 pts) (100 pts)Exam TotalProblem 1: DLX's immediate instructions use 16-bit
LSU - EE - 4720
EE 4720Problem 1:Homework 2Compare the coding of the DLX instructions:Due: 22 September 2000add r1, r2, r3 addi r4, r5, #6 to the corresponding Sun SPARC V8 instructions: add %g3, %g2, %g1 add %g5, 6, %g4 ! g1 = g2 + g3 ! g4 = g5 + 6The de
LSU - EE - 4720
EE 4720Problem 1:Homework 3Due: 2 October 2000What changes would have to be made to the pipeline below to add the DLX-BAM indexed addressing instructions (from homework 2). Hint: The load is easy and inexpensive, the store requires a substant
LSU - EE - 4720
LSU EE 4720Problem 1:Homework 3Due: 15 March 2004The MIPS program below copies a region of memory and runs on the illustrated implementation. In the sub-problems below use only the bypass connections shown in the illustration. (a) Show a pipel
LSU - EE - 4720
LSU EE 4720Problem 1:Homework 3Due: 3 November 2004Do Problems 1 and 2 From Spring 2004 Homework 3 http:/www.ece.lsu.edu/ee4720/2004/hw03.pdf. After completing the problems look at the solution and assign yourself a grade. The maximum grade sh
LSU - EE - 4720
EE 4720Problem 1:Homework 3 SolutionDue: 2 October 2000What changes would have to be made to the pipeline below to add the DLX-BAM indexed addressing instructions (from homework 2). Hint: The load is easy and inexpensive, the store requires a
LSU - EE - 4720
LSU EE 4720Problem 1:Homework 4 SolutionDue: 22 March 2004Suppose code like the memory copy program below (from Homework 3) appears frequently enough in the execution of programs so that new instructions should be added to the ISA to allow imp
LSU - EE - 4720
LSU EE 4720Homework 4 SolutionDue: 27 November 2002Problem 1: Consider the solution to Spring 2002 Homework 4, shown on the next page. (The solution was updated 19 November 2002, the PED is shown in dynamic order instead of the nearly-impossibl
LSU - EE - 4720
LSU EE 4720Problem 1:Homework 4Due: 22 March 2004Suppose code like the memory copy program above (from Homework 3) appears frequently enough in the execution of programs so that new instructions should be added to the ISA to allow improved exe
LSU - EE - 4720
EE 4720Problem 1:Homework 5Due: 5 December 2001An ISA has a character size of c = 9 bits (one more than most other ISA's!) and a 30-bit address space (A). An implementation has a bus width of w = 72 bits and has no cache. Show how 220 36 memo
LSU - EE - 4720
LSU EE 4720Homework 5 Solution Due: 3 December 2002To answer the questions below you need to use the PSE dataset viewer program. PSE (pronounced see) runs on Solaris and Linux; you can use the computer accounts distributed in class to run it, a L
LSU - EE - 4720
EE 4720Homework 6Due: Not CollectedIf you only have time for one of these problems, do problem three (the one on connecting memory devices to implement a cache). If you have or are hoping to get a job interview with a company that makes process
LSU - EE - 4720
LSU EE 4720Homework 1 SolutionDue: 17 September 2003Problem 1: Look at the following SPEC CINT2000 disclosures for these Dell and HP Itanium 2 systems: HP: http:/www.spec.org/osg/cpu2000/results/res2003q3/cpu2000-20030711-02389.html Dell: http:
LSU - EE - 4720
LSU EE 4720Homework 1Due: 3 October 2006Problem 1: Without looking at the solution solve Spring 2002 Homework 2 Problem 2 parts a-c. Then, look at the solution and assign yourself a grade in the range [0,1].
LSU - EE - 4720
LSU EE 4720Homework 1Due: 2 March 2007Problem 1: Without looking at the solution solve Spring 2002 Homework 2 Problem 2 parts a-c. Then, look at the solution and assign yourself a grade in the range [0,1]. Problem 2: If the value in register r2
LSU - EE - 4720
LSU EE 4720Homework 1Due: 20 February 2008Problem 1: Solve Fall 2007 Homework 2 without looking at the solution. Then look at the solution and give yourself a grade on a scale of [0, 1]. Warning: test questions are based on the assumption that
LSU - EE - 4720
LSU EE 4720Homework 1 Solution Due: 29 September 2008To answer the first question below see the MIPS32 Architecture manual linked to the course references page.Problem 1: The MIPS I bgtz and bltz instructions compare a register to zero, but can
LSU - EE - 4720
EE 4720Problem 1:Homework 1 Solution2 pts Just plug the run times into these equations AM =Assigned: Spring 1997GM =n i=1 i1XtnHM = X !,1n i=1 ti1n1vY u u t tnni=1ito obtain 42.6, 13.8, and 27.7 for the arithmetic,
LSU - EE - 4720
LSU EE 4720Homework 1 SolutionDue: 11 February 2005Problem 1: POWER is an IBM ISA developed for engineering workstations, PowerPC is an ISA developed by IBM, Apple, and Motorola for personal computers and is based on POWER. POWER and PowerPC ha
LSU - EE - 4720
LSU EE 4720Homework 1Due: 29 September 2008To answer the first question below see the MIPS32 Architecture manual linked to the course references page.Problem 1: The MIPS I bgtz and bltz instructions compare a register to zero, but can't compa
LSU - EE - 4720
LSU EE 4720Homework 2 SolutionDue: 9 March 2005For answers to the questions below refer to the PowerPC description Book I which can be found on the class references page, http:/www.ece.lsu.edu/ee4720/reference.html. Problem 1: One instruction t
LSU - EE - 4720
LSU EE 4720Homework 2 SolutionDue: 29 February 2008For the answers to these questions look at the ARM Architecture Reference Manual linked to the course references page, http:/www.ece.lsu.edu/ee4720/reference.html. Problem 1: The register field
LSU - EE - 4720
EE 4720Homework 2Due: 19 February 1999The SPARC assembly language program below is used in the problems that follow. SPARC register names are %g0-%g7, %i0-%i7, %l0-%l7, and %o0-%o7; and %g0 is a zero register (like r0 in DLX). The destination f
LSU - EE - 4720
LSU EE 4720Homework 2 SolutionDue: 1 October 2007For lecture material relevant to this assignment see http:/www.ece.lsu.edu/ee4720/2007f/lsli06.pdf. For some background and a list of similar problems see the statically scheduled study guide, ht
LSU - EE - 4720
LSU EE 4720Problem 1:Homework 3 SolutionDue: 3 November 2004Do Problems 1 and 2 From Spring 2004 Homework 3 http:/www.ece.lsu.edu/ee4720/2004/hw03.pdf. After completing the problems look at the solution and assign yourself a grade. The maximum
LSU - EE - 4720
LSU EE 4720Homework 3 SolutionDue: 15 October 2007The problems below ask about VAX instructions, which were not yet covered in class. For information on these instructions see the VAX Macro and Instruction Set manual linked to the EE 4720 refer
LSU - EE - 4720
LSU EE 4720Homework 3 SolutionDue: 29 October 2008Problem 1: Two MIPS implementations appear below, the first is the one presented in class, it will be called the mux-in-EX implementation. The second, the mux-in-ID implementation, has the ALU i
LSU - EE - 4720
LSU EE 4720Homework 3 SolutionDue: 20 March 2006Review Fall 2004 Final Exam Problem 2, which was discussed in class on Monday, 13 March 2006. Problem 1: Using the solution to Fall 2004 Final Exam problem 2 parts a, b, and d (but not c) as a sta
LSU - EE - 4720
LSU EE 4720Homework 3Due: 29 October 2008Problem 1: Two MIPS implementations appear below, the first is the one presented in class, it will be called the mux-in-EX implementation. The second, the mux-in-ID implementation, has the ALU input mult
LSU - EE - 4720
03-1Instruction Set (ISA) Design and Addressing Modes03-1Material from sections 2.1, 2.2, and 2.3.OutlineISA Design ChoicesIt's more than just picking instructions.ISA Design Choice DetailsScrew up, and you'll be cursed for decades.
LSU - EE - 4720
04-1Instruction Usage04-1Usage of DLX Instructions By SPEC92 Integer Codeand 3% 4% 5% 9% 13% 14% 16% 26% 0% compress eqntott 5% 10% 15% Total dynamic count espresso 20% gcc li 25% shift or store int compare int add intconditional branch loa
LSU - EE - 4720
08-1Interrupts and Exceptions08-1NotesMaterial in this set from Section 3.6.The book uses &quot;exception&quot; as a general term for all interrupts . . . . . . in these notes interrupt is used as the general term . . . . . . and a narrower definitio
LSU - EE - 4720
03-1Instruction Set (ISA) Design and Addressing Modes03-1 03-2ISA Design DecisionsI. OrganizationA. Data types (supported by ISA). B. Memory and register organization. C. Addressing modes.03-2Material from sections 2.1, 2.2, and 2.3.Outl
LSU - EE - 4720
12-1This Set12-1Material from Section 4.3This set under construction.Outline Branch Prediction Overview One-Level Predictor Two-Level Correlating Predictor Other topics to be added. Sample Problems12-1EE 4720 Lecture Transpare
LSU - EE - 4720
10-1Dynamic Scheduling10-1This Set Scheduling and Dynamic Execution Definitions From various parts of Chapter 4. Description of Two Dynamic Scheduling MethodsNot yet complete.(Material below may repeat material above.) Tomasulo's Algo
LSU - EE - 4720
LSU EE 4720Problem 1:# Cycle add \$t1, \$t2, \$t3 sub \$t4, \$t5, \$t1 lw \$t6, 4(\$t1) sw 0(\$t4), \$t6 0 1 IF IDHomework 3 Solution Due: 19 March 2003Consider the code below.(a) Show a pipeline execution diagram for the code running on the following
LSU - EE - 4720
09-1Multicycle Pipeline Operations09-1Material may be added to this set.Material CoveredSection 3.7.Long-Latency Operations (Topics)Typical long-latency instructions: floating pointPipelined v. non-pipelined execution unitsInitiatio
LSU - EE - 4720
03-1Instruction Set (ISA) Design and Addressing Modes03-1Material from sections 2.1, 2.2, and 2.3.OutlineISA Design ChoicesIt's more than just picking instructions.ISA Design Choice DetailsScrew up, and you'll be cursed for decades.
LSU - EE - 4720
12-1This Set12-1Material from Section 4.3This set under construction.Outline Branch Prediction Overview One-Level Predictor Two-Level Correlating Predictor Other topics to be added. Sample Problems12-1EE 4720 Lecture Transpare
LSU - EE - 4720
13-1Memory and Caches13-1See also cache study guide.ContentsSupplement to material in section 5.2.Includes notation presented in class.13-1EE 4720 Lecture Transparency. Formatted 12:18, 4 December 2006 from lsli13.13-113-2Memory
LSU - EE - 4720
13-1Memory and Caches13-1See also cache study guide.ContentsSupplement to material in section 5.2.Includes notation presented in class.13-1EE 4720 Lecture Transparency. Formatted 8:55, 30 November 2004 from lsli13.13-113-2Memory
LSU - EE - 4720
13-1Memory and Caches13-1See also cache study guide.ContentsSupplement to material in section 5.2.Includes notation presented in class.13-1EE 4720 Lecture Transparency. Formatted 13:15, 9 December 2007 from lsli13.13-113-2Memory
LSU - EE - 4720
NameSolutionComputer Architecture EE 4720 Midterm Examination, Part IMonday, 16 October 2000, 12:4013:30 CDTProblem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Alias Lets go Mets!(17 pts) Mon. (17 pts) Mon. (16 pts) Mon. (13 pts) Wed
LSU - EE - 4720
NameComputer Architecture EE 4720 Midterm ExaminationFriday, 26 October 2001, 13:4014:30 CDTProblem 1 Problem 2 Problem 3 Problem 4 Alias Good Luck!(15 pts) (15 pts) (10 pts) (60 pts) (100 pts)Exam TotalProblem 1: The DLX implementation be
LSU - EE - 4720
NameSolutionComputer Architecture EE 4720 Midterm Examination22 March 2000, 13:4014:30 CSTProblem 1 Problem 2 Problem 3 Alias Good Luck!(35 pts) (20 pts) (45 pts) (100 pts)Exam TotalProblem 1: The DLX implementation below has six stages.
LSU - EE - 4720
NameComputer Architecture EE 4720 Midterm ExaminationFriday, 25 October 2002, 10:4011:30 CDTProblem 1 Problem 2 Problem 3 Problem 4 Alias Good Luck!(30 pts) (13 pts) (13 pts) (44 pts) (100 pts)Exam TotalProblem 1: A new MIPS branch instruc
LSU - EE - 4720
NameComputer Architecture EE 4720 Midterm ExaminationFriday, 27 October 2006, 12:4013:30 CDTProblem 1 Problem 2 Problem 3 Alias Good Luck!(50 pts) (20 pts) (30 pts) (100 pts)Exam TotalProblem 1: In the MIPS implementation below the data me
LSU - EE - 4720
NameComputer Architecture EE 4720 Midterm ExaminationWednesday, 29 March 2006, 11:4012:30 CSTProblem 1 Problem 2 Problem 3 Alias Good Luck!(10 pts) (40 pts) (50 pts) (100 pts)Exam TotalProblem 1: The MIPS code below runs on the illustrated
LSU - EE - 4720
MIPS32TM Architecture For Programmers Volume III: The MIPS32TM Privileged Resource ArchitectureDocument Number: MD00090 Revision 0.95 March 12, 2001MIPS Technologies, Inc. 1225 Charleston Road Mountain View, CA 94043-1353Copyright 2001 MIPS Te
LSU - EE - 4720
LSU EE 4720Statically Sched. MIPS Impl. Study GuideDavid M. KoppelmanSpring 20061.1 IntroductionAn important part of the course and a big chunk of midterm- and final-exam credit is on the statically scheduled MIPS implementations. Essentially