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Components CPU Performance and Performance Equation
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Why is my computer fast (or slow)? ?
Would it help to improve
CPU performance equation is one way to start answering these questions.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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CPU Performance Decomposed into Three Components:
Clock Frequency () Determined by technology and influenced by organization.
Clocks per Instruction (CPI) Determined by ISA, microarchitecture, compiler, and program.
Instruction Count (IC) Determined by program, compiler, and ISA.
These combined to form CPU Performance Equation
tT = ,
1 CPI IC
where tT denotes the execution time.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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CPU Performance: Simple System
Execution in program order . . . . . . one at a time.
1 80 Instr. 1 Instr. 2 Instr. 3 160 2 3 4 5 6 7 8 9 10 11 1,999,996 39,999,920 Instr. 500,000
Time/cycles:
0
Time/mms:
0
IC = 500, 000;
= 50 kHz;
CPI = 4.
Execution time: IC CPI. clock period.
Here (and only here) CPI is number of cycles for each instruction.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Execution: Pipelined, In Order
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To Run Faster: Overlap Instructions (Pipelined Execution)
Result must be same as one-at-a-time execution . . . . . . not too difficult to achieve.
0 0 Instr. 1 Instr. 5 20 40 3,750,000 Instr. 500,000 1 2 3 4 5 6 7 8 9 10 11 750,000
Time/cycles:
Time/mms:
Instr. 2
Instr. 6
Instr. 3
Instr. 7
Instr. 4
IC = 500, 000;
= 200 kHz;
CPI =
750000 500000
= 1.5.
Execution time at best: IC clock period . . . . . . assuming 1 cycle to start each instruction and . . . . . . instruction can start each cycle. (Slower in illustration.)
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Execution: Pipelined, Ideal Out of Order
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To Run Even Faster: Overlap Instructions and Start Out of Order
Sometimes skip an instruction and execute it later.
0 0 Instr. 1 Instr. 5 Instr. 9 4 8 500,000 Instr. 500,000 1 2 3 4 5 6 7 8 9 10 11 500,000
Time/cycles:
Time/mms:
Instr. 2
Instr. 6
Instr. 4
Instr. 8
Instr. 3
Instr. 7
IC = 500, 000;
= 200 kHz;
CPI = 1.
Execution time at best: IC clock period . . . . . . assuming 1 cycle to start each instruction . . . . . . instruction can start each cycle.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Execution: Pipelined, Ideal Out of Order, Superscalar
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To Run Fastest1 : Overlap, Out-of-Order, Start n per Tick (n-Way Superscalar).
Requires about n times as much hardware. (Below, n = 2.)
Time/cycles: 250,000 500 Instr. 17 Instr. 500,000 Time/mms: Instr. 1 Instr. 3 Instr. 5 Instr. 7 Instr. 2 Instr. 4 Instr. 6 Instr. 8 Instr. 16 Instr. 14 Instr. 12 Instr. 10 Instr. 18 Instr. 15 Instr. 13 Instr. 11 Instr. 9 0 .008 .016 0 1 2 3 4 5 6 7 8 9 10 11
IC = 500, 000;
= 500 MHz;
1 CPI = 2 .
1 Execution time at best: n IC clock period . . . . . . assuming 1 cycle to start each instruction instruction can start each cycle.
1
Using a conventional serial instruction set architecture.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Execution: Pipelined, Out of Order, Superscalar
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Data from a real program, perl. CPI is 0.44.
Processor can start four instructions per cycle.
Colors show the steps in processing an instruction, yellow is execution.
S_regmatch+104 0x001610d8 stw %o4, [ %l0 + 16 ] 0x001610dc cmp %o1, 2 0x001610e0 bne +3i {S_regmatch+109} 0x001610e4 lduw [ %l0 + 24 ], %l6 0x001610ec mov %o0, %i5 mov %i1 , %l3 0x001610f0 0x001610f4 cmp %i1, 0 0x001610f8 be -100i {S_regmatch+12} 0x001610fc sethi %hi(0x1f0800), %g2 0x00161100 lduh [ %l3 + 2 ], %g2 0x00161104 ldub [ %l3 + 1 ], %o0 0x00161108 sll %g2 , 2, %g2 0x0016110c add %l3 , %g2 , %i1 0x00161110 cmp %i1 , %l3 0x00161114 bne +3i {S_regmatch+122} 0x00161118 mov %o0, %l0 0x00161120 cmp %o0, 77 0x00161124 bgu +3509i {S_regmatch+3632 0x00161128 sethi %hi(0x219c00), %g2 0x0016112c sethi %hi(0x160c00), %g1 0x00161130 sll %o0, 2, %g3 0x00161134 add %g1, 512, %g2 {0x160e00} 0x00161138 lduw [ %g3 + %g2 ], %g3 0x0016113c jmp %g3 + %g2
EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Time 42,084,435
Grid 20 insn X 5 cyc
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Component of CPU Performance: Instruction Count
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Given a program there are two ways instructions could be tallied:
Static Instruction Count:
The number of instructions making up the program.
Dynamic Instruction Count (IC):
The number of instructions executed in a run of the program.
For estimating performance, dynamic instruction count is used.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Instruction Counts
9 i=0
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Example, assembler program that computes a = i.
Written in Simplescalar assembler.
IC 1 1 r5, r0 r3, r0 r5, r3, r2, r2, r5, r3, r3, r0, r3 1 10 ! r2 = r3 < 10 L23 ! Branch to L23 if r2 not equal 0. ! Branch label. ! Add unsigned. ! r0 is always zero.
10 10 10 10
move move L23: addu addu slt bne
Static count: 6 (number of instructions).
Dynamic count: 42.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Component of CPU Performance: Clock Frequency
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CPUs implemented using synchronous clocked logic.
Typical Clock Cycle
When clock switches from low to high work starts.
While clock is high work proceeds.
When clock goes from high to low work should be complete.
Clock frequency determined by critical path.
Critical Path:
Logic doing most time consuming work (in a cycle).
If clock frequency is too high work will not be completed . . . . . . and so system will not perform properly.
For high clock frequencies, keep critical paths short.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Component of CPU Performance: CPI
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Cycles (clocks) per Instruction (CPI)
Oversimplified definition: CPI:
Average number of cycles needed to execute an instruction.
Better definition: CPI:
Number of cycles to execute some code divided by number of instructions.
Difference:
Interested in rate at which instructions executed in program . . .
. . . not time time for any one instruction.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Review of CPU Performance Equation
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tT = ,
1 CPI IC
where tT denotes the execution time.
Clock Frequency () Determined by technology and influenced by organization.
Clocks per Instruction (CPI) Determined by organization and instruction mix.
Instruction Count (IC) Determined by program and ISA.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Interaction of Execution Time Components
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Tradeoffs between Clock Frequency, CPI, and Instruction Count
Increasing Clock Frequency . . .
. . . reduces the work that can be done in a clock cycle . . . . . . and possibly limiting instruction overlap, therefore increasing CPI.
Reducing IC (by adding "powerful" instructions to ISA) . . .
. . . may force implementors to increase CPI or lower clock frequency.
Balancing these is an important skill in computer design.
Since the ISA is usually fixed, IC is less of a factor.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Example: Trading off Execution Time Components
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Company X is considering two clock frequencies for its next processor, 500 MHz or 400 MHz. A 500 MHz implementation would execute instructions at 1.7 CPI, 400 the MHz part at 1.1 CPI. Which would be faster?.
Find time to execute 1 instruction.
1 500106
500 MHz execution time: 1.7 1 = 3.4 s 1.1 1 = 2.75 s.
1 400106
400 MHz execution time:
The lower clock rate would nevertheless take less time.
Perhaps because at 500 MHz too much work had to be split into multiple cycles.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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IC v. CPI Tradeoffs
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Assumption
IC is based on output of a good compiler.
Compiler is tuned for a particular implementation.
Two Cases
1. Same ISA, different implementation.
2. Different ISA, (and of course) different implementation.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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IC v. CPI Tradeoffs, continued.
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Case 1: Same ISA, different implementation.
Newer implementation may have lower CPI on existing code . . . . . . but even better performance attainable by recompiling . . . . . . which may increase CPI.
Compiler writer selects instructions based on performance of implementation.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Consider two implementations:
Implementation A: add CPI 1 cycle, mul CPI 5 cycles.
Implementation B: add CPI 1 cycle, mul CPI 2 cycles. Code computes 6x.
! Call original value of r1, x.
! Code For Implementation A add r1, r1, r1 ! r1 = 2x add r2, r1, r1 ! r2 = 4x add r1, r1, r2 ! r1 = 6x
! Code For Implementation B. mul r1, r1, 6 ! r1 = 6x.
Implementation A: IC = 3, CPI = 1 (Computing CPI will be covered later.)
Implementation B: IC = 1, CPI = 2.
Implementation B is faster despite higher CPI.
Code compiled for B will run slowly on A.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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IC v. CPI Tradeoffs, continued.
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Case 2: Different ISA, (and of course) different implementation.
Major tradeoffs in complexity and speed.
Consider two implementations:
Implementation A: CPI: load, 2; add and store, 1.
Implementation B: CPI: add (doing load and store), 4.
! Code for implementation A. load r1, [r2] ! Load r1 with data at address in r2. add r3, r1, r4 ! r3 = r1 + r4 store [r2], r3 ! Store r3 at address in r2.
! Code for implementation B. add [r2], r4, [r2]
Execution time same.
Implementation A: IC = 3, CPI = 4 . 3
Implementation B: IC = 1, CPI = 4.
EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Technological Change
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Golden Handcuffs:
The need to maintain compatibility in a successful product line.
Famously, Intel's IA-32. (Popularly referred to as 80x86.)
The ISA is the handcuffs. . . . . . and technological change brings the desire to move your arms.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Technological Change and Computer Designer
Technology determines "raw materials" for designer.
Raw material: number of gates and their speed.
ISA lifetime can be decades.
Raw materials greatly change over this time.
So, design ISA for now and future.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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How technological advancement affects processor.
Logic Speed, Clock Rate
No changes to organization or ISA.
Number of Transistors Available for Logic
Changes to organization and possible changes to ISA.
Memory Size
Change ISA to use larger address space.
Can use ISA having larger instruction codings.
Memory Speed Compared to Processor Speed
Include more sophisticated caching in organization.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Benchmarks
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Benchmark:
Program used to evaluate performance.
Uses
Guide computer design.
Guide purchasing decisions.
Marketing tool.
Guiding Computer Design
Measure overall performance.
Determine characteristics of programs.
E.g., frequency of floating-point operations.
Determine effect of design options.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Choosing Benchmark Programs
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Important: Choice of programs for evaluation.
Optimal but unrealistic:
The exact set of programs customer will run.
Problem: computers used for different applications.
Therefore, must model typical users' workload.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Options:
Real Programs: Programs chosen using surveys, for example.
+ Measured performance improvements apply to customer.
Large programs hard to run on simulator. (Before system built.)
Kernels: Use part of program responsible for most execution time.
+ Easier to study.
Not all program have small kernels.
Toy Benchmarks: Program performs simplified version of common task.
+ Easier to study.
May not be realistic.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Synthetic Benchmarks: Program "looks like" typical program, but does nothing useful.
+ Easier to study.
May not be realistic.
Commonly Used Option
Overall performance: real programs
Test specific features: synthetic benchmarks.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Benchmark Suites
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Benchmark Suite:
A named set of programs used to evaluate a system.
Typically:
Developed and managed by a publication or non-profit organization. E.g., Standard Performance Evaluation Corp., PC Magazine.
Tests clearly delineated aspects of system. E.g., CPU, graphics, I/O, application.
Specifies a set of programs and inputs for those programs.
Specifies reporting requirements for results.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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What Suites Might Measure
Application Performance E.g., productivity (office) applications, database programs. Usually tests entire system.
CPU and Memory Performance Ignores effect of I/O.
Graphics Performance
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Example, SPEC CPU2000 Suites
Respected measure of CPU performance.
Managed by Standard Performance Evaluation Corporation,. . .
. . .a non-profit organization funded by computer companies.
Measures CPU and memory performance on integer and FP code.
Uses common Unix programs such as perl, gcc, gzip.
Requires that results on each program be reported.
Programs compiled with publicly available compilers and libraries.
Programs compiled with and without expert tuning.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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SPEC CPU2000 Suites and Measures
Suite of integer programs run to determine:
SPECint2000, execution time of tuned code.
SPECint base2000, execution time of untuned code.
SPECint rate2000, throughput of tuned code.
SPECint rate base2000, throughput of untuned code.
Suite of floating programs run to determine:
SPECfp2000, execution time of tuned code.
SPECfp base2000, execution time of untuned code.
SPECfp rate2000, throughput of tuned code.
SPECfp rate rate2000, throughput of untuned code.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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Other Examples
(Fall 2001: This list is out of date.)
BAPCO Suites, measure productivity app. performance on Windows 95.
TPC, measure "transaction processing" system performance.
WinMARK, graphics performance.
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EE 4720 Lecture Transparency. Formatted 10:24, 21 January 2004 from lsli02.
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